XAUI v12.3 Product Guide
31
PG053 April 6, 2016
Chapter 2:
Product Specification
If you are migrating from a 7 series to an UltraScale device, the prefixes of the optional transceiver debug ports for
single-lane cores are changed from “gt0”, “gt1” to “gt”, and the suffix “_in” and “_out” are dropped. For multi-lane
cores, the prefixes of the optional transceiver debug ports gt(n) are aggregated into a single port. See
for more information.
MDIO Interface
The MDIO Interface signals are shown in
. More information on using this
interface can be found in
Chapter 5, Interfacing to the Core
gt_txprecursor[19:0]
in
Async
Transmitter post-cursor TX pre-emphasis control.
gt_txdiffctrl[19:0 or 15:0] in
Async
Driver Swing Control. The bus size is 20 bits for GTYE3 and
16 bits for GTHE3.
gt_txinhibit3:0]
in
clk156_out
When High, this signal blocks the transmission of data.
PRBS
gt_rxprbscntreset[3:0]
in
clk156_out
Resets the PRBS error counter.
gt_rxprbserr[3:0]
out
clk156_out
This non-sticky status output indicates that PRBS errors
have occurred.
gt_rxprbssel[15:0]
in
clk156_out
Receiver PRBS checker test pattern control.
gt_txprbssel[15:0]
in
clk156_out
Transmitter PRBS generator test pattern control.
gt_txprbsforceerr[3:0]
in
clk156_out
When this port is driven High, errors are forced in the PRBS
transmitter. While this port is asserted, the output data
pattern contains errors.
RX CDR
gt_rxcdrhold[3:0]
in
Async
Hold the CDR control loop frozen.
Digital Monitor
gt_dmonitorout[67:0]
out
Async
Digital Monitor Output Bus
Status
gt_rxdisperr[7:0]
out
clk156_out
Active-High indicates the corresponding byte of the
received data has a disparity error.
gt_rxnotintable[7:0]
out
clk156_out
Active-High indicates the corresponding byte of the
received data was not a valid character in the 8B/10B table.
gt_rxcommadet[3:0]
out
clk156_out
This signal is asserted when the comma alignment block
detects a comma.
Table 2
‐
9:
Transceiver Control and Status Ports — UltraScale Architectures
(Cont’d)
Signal Name
Direction
Clock
Domain
Description
Table 2
‐
10:
MDIO Management Interface Ports
Signal Name
Direction
Clock
Domain
Description
mdc
in
Async
Management clock
mdio_in
in
Async
MDIO input
