Sun Microelectronics
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14. Implementation Dependencies
The FPRS.DU and FPRS.DL may be set pessimistically, even though the instruc-
tion that modified the floating-point register file is nullified.
14.3.5 Floating-Point Status Register (FSR) (Impdep #13, 19, 22, 23, 24)
UltraSPARC supports precise-traps and implements all three exception fields
(TEM, cexc, and aexc) conforming to IEEE Std 754-1985. The state of the FSR after
reset is documented in Table 10-1, “Machine State After Reset and in RED_state,”
on page 172.
u:
Unused field, read as 0.
Note:
The LD{X}FSR instruction should write zeroes to the u fields; undefined
values (read as 0) of these fields are stored by the ST{X}FSR instruction.
fcc3, fcc2, fcc1, fcc0:
Four sets of 2-bit floating-point condition codes, which are
modified by the FCMP{E} (and LD{X}FSR) instructions. The FBfcc,
FMOVcc, and MOVcc instructions use one of these condition code sets to
determine conditional control transfers and conditional register moves.
Note:
fcc0 is the same as the fcc in SPARC-V8.
Table 14-7
Floating-Point Status Register Format
Bits
Field
Use
RW
<63:38>
Reserved
—
R
<37:36>
fcc3
Floating-point condition code (set 3)
RW
<35:34>
fcc2
Floating-point condition code (set 2)
RW
<33:32>
fcc1
Floating-point condition code (set 1)
RW
<31:30>
RD
Rounding direction
RW
<29:28>
u
Unused
R
<27:23>
TEM
IEEE-754 trap enable mask
RW
<22>
NS
Non-standard floating-point results
R
<21:20>
Reserved
—
R
<19:17>
ver
FPU version number
R
<16:14>
ftt
Floating-point trap type
RW
<13:>
qne
Floating-point deferred-trap queue (FQ) not empty
RW
<12>
u
Unused
R
<11:10>
fcc0
Floating-point condition code (set 0)
RW
<9:5>
aexc
Accumulated outstanding exceptions
RW
<4:0>
cexc
Current outstanding exceptions
RW
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