Sun Microelectronics
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10. Reset and RED_state
Note:
Each register must be initialized before it is used. For example, CWP
must be initialized before accessing any windowed registers, since the CWP
register selects which register window to access. Failure to properly initialize
registers or state prior to use may result in unpredicted or incorrect results.
10.1.2 Externally Initiated Reset (XIR)
An Externally Initiated Reset is sent to the CPU via the XIR pin; it causes a
SPARC-V9 XIR, which has a trap type of 003
16
at physical address offset 60
16
. It
has higher priority than all other resets except POR.
10.1.3 Software-Initiated Reset (SIR)
A Software-Initiated Reset is initiated by a SIR instruction within any processor.
This per-processor reset has a trap type of 004
16
at physical address offset 80
16
.
This reset affects only one processor, not the entire system.
10.1.4 Watchdog Reset (WDR) and error_state
A SPARC-V9 processor enters error_state when a trap occurs and TL = MAXTL.
The processor signals itself internally to take a
watchdog_reset
(WDR) trap at
physical address offset 40
16
. This reset affects only one processor, rather than the
entire system. CWP updates due to window traps that cause watchdog traps are
the same as the no watchdog trap case.
10.2 RED_state Trap Vector
When a SPARC-V9 processor processes a reset or trap that enters RED_state, it
takes a trap at an offset relative to the RED_state_trap_ vector base address
(RSTVaddr); in UltraSPARC this is at virtual address FFFF FFFF F000 0000
16
,
which passes through to physical address 1FF F000 0000
16
.
10.3 Machine State after Reset and in RED_state
Table 10-1 on page 172 shows the machine state created as a result of any reset, or
after entering RED_state.
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