Sun Microelectronics
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UltraSPARC User’s Manual
D.3.4 SELECT-IR-SCAN
A temporary state in which all test data registers retain their previous state.
D.3.5 CAPTURE IR/DR
In this state, the selected register (either instruction register or data register) loads
data into its parallel input.
For the instruction register, this corresponds to sampling the 8 bits of status infor-
mation and the loading of the constant ‘01’ pattern into the two least significant
bits.
D.3.6 SHIFT IR/DR
In this state, the IR/DR shift towards their serial output during each rising edge
of TCK.
D.3.7 EXIT-1 IR/DR
A temporary controller state in which the IR/DR retain their previous state.
D.3.8 PAUSE IR/DR
A temporary controller state in which the IR/DR retain their previous state.
This state is provided so that the shifting of data through the instruction register
or the test data register can be temporarily halted (without the need to stop TCK).
D.3.9 EXIT-2 IR/DR
A temporary controller state in which the IR/DR retain their previous state.
D.3.10 UPDATE IR/DR
Data is latched onto the parallel output of the IR/DR from the shift-register path
during this controller state.
The data held at the previous outputs of the instruction register or test data reg-
ister does not change other than in this controller state.
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