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11. Error Handling
If an E-Cache data parity error occurs while snooping, a bad ECC error is gener-
ated and sent to the requester. This causes an
instruction_access_error
or
data_access_error
trap at the master that requested the data. The slave processor
logs error information that can be read by the master during error handling. The
processor being snooped is not interrupted by this error condition.
If an E-Cache data parity error occurs during a write-back, uncorrectable ECC is
generated and sent to memory to prevent further use of the corrupted data. The
error information is logged in the AFSR and a disrupting
data_access_error
trap is
generated. Software should log the writeback error so that a subsequent uncor-
rectable ECC error can be correlated back to the cache parity error.
11.2.4 System ECC Error
UltraSPARC supports ECC generation and checking for all accesses to and from
the system bus. Correctable errors are fixed and the data transfer continues. Un-
correctable errors have bad parity forced before installing in the E-Cache. This
prevents using the bad data, or having the bad data written back to memory with
good ECC bits. Uncorrectable ECC errors on cache fills will be reported for any
ECC error in the cache block, not just the referenced word.
An Uncorrectable error detected during an instruction access causes an
instruction_access_error
deferred trap. An uncorrectable error detected during a
data access causes a
data_access_error
deferred trap. When multiple errors occur,
the trap type corresponds to the first detected error.
An uncorrectable ECC error during an interrupt vector transmission is not report-
ed to the issuing processor. When the interrupt-data is read by the destination
processor, a
data_access_error
trap is generated.
11.3 Memory Error Registers
Note:
MEMBAR
#Sync
is generally needed after stores to error ASI registers.
See Section 5.3.8, “Instruction Prefetch to Side-Effect Locations,” on page 38.
11.3.1 E-Cache Error Enable Register
Refer to Table 10-1, “Machine State After Reset and in RED_state,” on page 172
for the state of this register after reset.
Name
: ASI_ESTATE_ERROR_EN_REG
ASI=4B
16
, VA<63:0>=0
16
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