Sun Microelectronics
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6. MMU Internal Architecture
Note:
No reset of the TLB is performed by a chip reset or by entering
RED_state. Before the MMUs are enabled, the operating system software must
explicitly write each entry with either a valid TLB entry or an entry with the
valid bit set to zero. The operation of the I-MMU or D-MMU in enabled mode is
undefined if the TLB valid bits have not been set explicitly beforehand.
6.8 Compliance with the SPARC-V9 Annex F
The UltraSPARC MMU complies completely with Annex F, “SPARC-V9 MMU Re-
quirements,” in The SPARC Architecture Manual, Version 9. Table 6-9 shows how
various protection modes can be achieved, if necessary, through the presence or
absence of a translation in the I- or D-MMU. Note that this behavior requires spe-
cialized TLB miss handler code to guarantee these conditions.
6.9 MMU Internal Registers and ASI Operations
6.9.1 Accessing MMU Registers
All internal MMU registers can be accessed directly by the CPU through
UltraSPARC-defined ASIs. Several of the registers have been assigned their own
ASI because these registers are crucial to the speed of the TLB miss handler. Al-
lowing the use of
%g0
for the address reduces the number of instructions to per-
form the access to the alternate space (by eliminating address formation).
See Section 6.10, “MMU Bypass Mode,” on page 68 for details on the behavior of
the MMU during all other UltraSPARC ASI accesses. For instance, to facilitate an
access to the D-Cache, the MMU performs a bypass operation.
Table 6-9
MMU Compliance w/SPARC-V9 Annex
F
Protection Mode
Condition
Resultant
Protection Mode
TTE in
D-MMU
TTE in
I-MMU
Writable
Attribute Bit
Yes
No
0
Read-only
No
Yes
Don’t Care
Execute-only
Yes
No
1
Read/Write
Yes
Yes
0
Read-only/Execute
Yes
Yes
1
Read/Write/Execute
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