Sun Microelectronics
178
UltraSPARC User’s Manual
11.1.3 Disrupting Errors
Disrupting errors are due to Single-Bit ECC Errors (which are corrected by the
hardware) and E-Cache data parity errors during write back. Disrupting errors
should be handled by logging the error and resuming execution.
Recoverable ECC errors result from detection of a single-bit ECC error during a
system transaction. Memory read errors are logged in the Asynchronous Fault
Status Register (and possibly Asynchronous Fault Address Register). If the
Correctable_Error (CEEN) trap is enabled in the E-Cache Error Enable Register, a
corrected_ECC_error
trap is generated. This is trap type TT=63
16
and priority 33.
E-Cache data parity errors are discussed in Section 11.2.3, “E-Cache Data Parity
Error,” on page 178. An E-Cache data parity error during writeback is recoverable
because the processor is not reading the affected data. As a result, UltraSPARC
will take a disrupting
data_access_error
trap with priority 33 instead of a deferred
trap. This avoids panics when the system displaces corrupted user data from the
cache.
Note:
To prevent multiple traps from the same error, software should not
reenable interrupts until after the disrupting error status bit in AFSR is cleared.
11.2 Memory Errors
11.2.1 Module Parity Errors
Byte parity is generated and checked for all transfers between the UltraSPARC
and its external E-Cache and system data path. Both address tag and data are
protected.
11.2.2 E-Cache Tag Parity Error
Tag parity errors from internal or snoop transactions will cause a system fatal er-
ror as described in Section 11.1.1, “System Fatal Errors,” on page 175.
11.2.3 E-Cache Data Parity Error
An E-Cache data parity error detected during an instruction access causes an
instruction_access_error
deferred trap. An E-Cache parity error detected during a
data read access causes a
data_access_error
deferred trap. When multiple errors
occur, the trap type corresponds to the first detected error.
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