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14. Implementation Dependencies
Note:
The AG, IG, and MG bits are mutually exclusive. Attempting to set a
reserved encoding using a WRPR to PSTATE will generate an
illegal_instruction
trap. UltraSPARC does not check for a reserved encoding in TSTATE. This will
cause undefined results when a DONE or RETRY is executed.
14.5.10 Interrupt Vector Handling
Processors and I/O devices can interrupt a selected processor by assembling and
sending an interrupt packet consisting of three 64-bit interrupt data words. This
allows hardware interrupts and cross calls to have the same hardware mecha-
nism and to share a common software interface for processing. Interrupt vectors
are described in Section 9.1, “Interrupt Vectors,” on page 161.
14.5.11 Power Down Support and the SHUTDOWN Instruction
UltraSPARC supports power down mode to reduce power requirements during
idle periods. A privileged instruction, SHUTDOWN, has been added to facilitate
a software-controlled power down of the CPU and system. Power down support
is described in Appendix C, “Power Management,” on 327. The SHUTDOWN in-
struction is described in Section 13.2, “SHUTDOWN,” on page 195
14.5.12 UltraSPARC Instruction Set Extensions (Impdep #106)
The UltraSPARC CPU extends the standard SPARC-V9 instruction set with three
new classes of instructions. They have been designed to support power down
mode (see Section 13.2, “SHUTDOWN,” on page 195”), enhance graphics func-
tionality (see Section 13.5, “Graphics Instructions”), and improve the efficiency of
memory accesses (see Section 13.6, “Memory Access Instructions).
Unimplemented IMPDEP1 and IMPDEP2 opcodes encountered during execution
cause an
illegal_instruction
trap.
14.5.13 Performance Instrumentation
UltraSPARC performance instrumentation is described in Section B.4, “Perfor-
mance Instrumentation Counter Events,” on page 321.
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