Sun Microelectronics
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UltraSPARC User’s Manual
7.14.4 Blocked Issue of Reads with Writebacks
UltraSPARC delays issuing a read miss / Writeback transaction pair (both the
P_RD*_REQ with DVP=1, and the P_WRB_REQ) for any of the following reasons:
•
The read or the Writeback is constrained to not issue due to restrictions on the
allowed number of outstanding transactions in Class 0 or 1
•
Any other constraints on the issue of the Writeback, with respect to
outstanding transactions.
The Writeback also may be blocked because the E-Cache data bus is unavailable;
this condition does not block the read miss, however.
So, UltraSPARC will not issue a read miss / Writeback pair (either the read or the
Writeback) if there is any outstanding block store or interrupt, because the Write-
back is blocked. Therefore, for UltraSPARC-I, a read miss with Writeback can
have only prior noncacheable 16-byte stores outstanding. As noted before, there
is no requirement to complete these noncacheable stores before the Writeback.
Typical systems will, however, since they complete all Class 1 transactions in or-
der.
Additionally, UltraSPARC-I restricts the issue of a read with Writeback until any
prior read with Writeback has completed fully (both the prior read and Write-
back). A prior outstanding Writeback does not delay the issue of a clean read
miss (DVP=0).
7.14.5 Limiting the Number of Transactions in a Class
UltraSPARC-I limits the number of transactions in Class 1 and also limits the
number of outstanding 16-byte noncacheable stores and block stores.
UltraSPARC-II also has the ability to limit the number of outstanding Class 0 64-
byte reads, and the number of Writebacks in Class 1. See Section 8.3.3.2, “UPA
Configuration Register,” on page 154 for more information.
7.14.6 S_REPLY Timing Constraints
In asserting S_REPLYs, SC must guarantee that there is at least one dead cycle
whenever the bus driver changes (for example, from UltraSPARC to memory).
No dead cycle is required for multiple packets from the same driver, however.
S_OAK, S_RTO, and S_ERR have no data transfer; they can be issued at any time.
See Constraint #5 on page 121.
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