Sun Microelectronics
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UltraSPARC User’s Manual
Using the two counters to measure instruction completion and cycles allows cal-
culation of the average number of instructions completed per cycle.
B.4.2 Grouping (G) Stage Stall Counts
These are the major cause of pipeline stalls (bubbles) from the G Stage of the
pipeline. Stalls are counted for each clock that the associated condition is true.
Dispatch0_IC_miss [PIC0]
I-buffer is empty from I-Cache miss. This includes E-Cache miss processing if an
E-Cache miss also occurs.
Dispatch0_mispred [PIC1]
I-buffer is empty from Branch misprediction. Branch misprediction kills instruc-
tions after the dispatch point, so the total number of pipeline bubbles is approxi-
mately twice as big as measured from this count.
Dispatch0_storeBuf [PIC0]
Store buffer can not hold additional stores, and a store instruction is the first
instruction in the group.
Dispatch0_FP_use [PIC1]
First instruction in the group depends on an earlier floating point result that is
not yet available, but only while the earlier instruction is not stalled for a
Load_use (see B.4.3 ). Thus, Dispatch0_FP_use and Load_use are mutually
exclusive counts.
Some less common stalls (see Chapter 17, “Grouping Rules and Stalls”) are not
counted by any performance counter, including:
•
One cycle stalls for an FGA/FGM instruction entering the G stage following
an FDIV or FSQRT.
B.4.3 Load Use Stall Counts
Stalls are counted for each clock that the associated condition is true.
Load_use [PIC0]
An instruction in the execute stage depends on an earlier load result that is not
yet available. This stalls all instructions in the execute and grouping stages.
Load_use also counts cycles when no instructions are dispatched due to a one
cycle load-load dependency on the first instruction presented to the grouping
logic.
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