Sun Microelectronics
6
UltraSPARC User’s Manual
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Integer Execution Unit (IEU) with two Arithmetic and Logic Units (ALUs)
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Load/Store Unit (LSU) with a separate address generation adder
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Load buffer and store buffer, decoupling data accesses from the pipeline
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A 16Kb Data Cache (D-Cache)
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Floating-Point Unit (FPU) with independent add, multiply, and divide/square
root sub-units
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Graphics Unit (GRU) with two independent execution pipelines
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External Cache Unit (ECU), controlling accesses to the External Cache
(E-Cache)
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Memory Interface Unit (MIU), controlling accesses to main memory and I/O
space
1.3.1 Prefetch and Dispatch Unit (PDU)
The prefetch and dispatch unit fetches instructions before they are actually need-
ed in the pipeline, so the execution units do not starve for instructions. Instruc-
tions can be prefetched from all levels of the memory hierarchy; that is, from the
instruction cache, the external cache, and main memory. In order to prefetch
across conditional branches, a dynamic branch prediction scheme is implemented
in hardware. The outcome of a branch is based on a two-bit history of the branch.
A “next field” associated with every four instructions in the instruction cache
(I-Cache) points to the next I-Cache line to be fetched. The use of the next field
makes it possible to follow taken branches and to provide nearly the same in-
struction bandwidth achieved while running sequential code. Prefetched instruc-
tions are stored in the Instruction Buffer until they are sent to the rest of the
pipeline; up to 12 instructions can be buffered.
1.3.2 Instruction Cache (I-Cache)
The instruction cache is a 16 Kbyte two-way set associative cache with 32 byte
blocks. The cache is physically indexed and contains physical tags. The set is pre-
dicted as part of the “next field;” thus, only the index bits of an address (13 bits,
which matches the minimum page size) are needed to address the cache. The
I-Cache returns up to 4 instructions from an 8-instruction-wide cache line.
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