Sun Microelectronics
32
UltraSPARC User’s Manual
Note:
A MEMBAR
#MemIssue
or MEMBAR
#Sync
is needed if ordering of
cacheable accesses following noncacheable accesses must be maintained in PSO
or RMO.
Due to load and store buffers implemented in UltraSPARC, the above example
may not work in PSO and RMO modes without the MEMBARs shown in the pro-
gram segment.
In TSO mode, loads and stores (except block stores) cannot pass earlier loads, and
stores cannot pass earlier stores; therefore, no MEMBAR is needed.
In PSO mode, loads are completed in program order, but stores are allowed to
pass earlier stores; therefore, only the MEMBAR at #1 is needed between updat-
ing data and the flag.
In RMO mode, there is no implicit ordering between memory accesses; therefore,
the MEMBARs at both #1 and #2 are needed.
5.3.2 Memory Synchronization: MEMBAR and FLUSH
The MEMBAR (STBAR in SPARC-V8) and FLUSH instructions are provide for ex-
plicit control of memory ordering in program execution. MEMBAR has several
variations; their implementations in UltraSPARC are described below. See Section
A.31, “Memory Barrier,” Section 8.4.3, “The MEMBAR Instruction,” and Section J,
“Programming With the Memory Models,” in The SPARC Architecture Manual,
Version 9 for more information.
5.3.2.1 MEMBAR #LoadLoad
Forces all loads after the MEMBAR to wait until all loads before the MEMBAR
have reached global visibility.
5.3.2.2 MEMBAR #StoreLoad
Forces all loads after the MEMBAR to wait until all stores before the MEMBAR
have reached global visibility.
5.3.2.3 MEMBAR #LoadStore
Forces all stores after the MEMBAR to wait until all loads before the MEMBAR
have reached global visibility.
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