Sun Microelectronics
76
UltraSPARC User’s Manual
Figure 7-2 illustrates how data and ECC bytes are arranged and addressed within
a quadword (for big-endian accesses).
Figure 7-2
Data and ECC Byte Addresses Within a Quadword
For coherent block read and copyback transactions of 64-byte datums, the ad-
dressed quad-word (16 bytes) selected by physical address bits PA<5:4> is deliv-
ered first. Successive quadwords are delivered in the order shown below.
Noncached block reads and all block writes of 64-byte datums are always aligned
on a 64-byte block boundary (PA<5:4>=0).
7.3 Interaction Between E-Cache and UDB
7.3.1 Overview
The UDB isolates the UltraSPARC from SYSDATA(Figure 7-1). The UDB provides
data buffers to minimize the overhead of data transfers from UltraSPARC to the
system by hiding system latency (for example, for Writebacks and noncacheable
stores). The UDB supports multiple outstanding transactions to increase overall
bandwidth. The UDB also handles interrupt packets. Finally, the UDB generates
and checks ECC bits on each data transfer.
Table 7-2
Quadword Ordering
Address
PA<5:4>
1
st
Quadword
on SYSDATA
2
nd
Quadword
on SYSDATA
3
rd
Quadword
on SYSDATA
4
th
Quadword
on SYSDATA
0
16
Qword 0
Qword 1
Qword 2
Qword 3
1
16
Qword 1
Qword 0
Qword 3
Qword 2
2
16
Qword 2
Qword 3
Qword 0
Qword 1
3
16
Qword 3
Qword 2
Qword 1
Qword 0
0
7
8
15
0
7
8
15
16
23
24
31
32
39
40
47
48
55
56
63
64
71
72
79
80
87
88
95
96
103
104
111
112
119
120
127
Byte 0
Byte 1
Byte 7
Byte 6
Byte 2
Byte 3
Byte 4
Byte 5
Byte 8
Byte 9
Byte 15
Byte 14
Byte 10
Byte 11
Byte 12
Byte 13
For Bytes
For Bytes
0 - 7
8 - 15
ECC
ECC
Quad Lo Bytes
Quad Hi Bytes
ECC Bytes
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