Sun Microelectronics
60
UltraSPARC User’s Manual
FV
:
Fault Valid. Set when the MMU detects a fault; it is cleared only on an
explicit ASI write of 0 to the SFSR register. When FV is not set, the values
of the remaining fields in the SFSR and SFAR are undefined.
The SFSR and the Tag Access registers both maintain state concerning a previous
translation causing an exception. The update policy for the SFSR and the Tag Ac-
cess registers is shown in Table 6-4 on page 51.
Note:
A
fast_{instruction
,
data
}
_access_MMU_miss
trap does not cause the SFSR or
SFAR to be written. In this case the D-SFAR information can be obtained from the
D Tag Access register.
6.9.5 I-/D-MMU Synchronous Fault Address Registers (SFAR)
6.9.5.1 I-MMU Fault Address
There is no I-MMU Synchronous Fault Address register. Instead, software must
read the TPC register appropriately as discussed here.
For
instruction_access_MMU_miss
traps, TPC contains the virtual address that was
not found in the I-MMU TLB.
For
instruction_access_exception
traps, “privilege violation” fault type, TPC con-
tains the virtual address of the instruction in the privileged page that caused the
exception.
For
instruction_access_exception
traps, “VA out of range” fault types, note that the
TPC in these cases contains only a 44-bit virtual address, which is sign-extended
based on bit VA<43> for read. Therefore, use the following methods to compute
the virtual address that was out of range:
•
For the branch, CALL, and sequential exception case, the TPC contains the
lower 44 bits of the virtual address that is out of range. Because the hardware
sign-extends a read of the TPC register based on VA<43>, the contents of the
TPC register XORed with FFFF F000 0000 0000
16
will give the full 64-bit out-
of-range virtual address.
•
For the JMPL or RETURN exception case, the TPC contains the virtual address
of the JMPL or RETURN instruction itself. Software must disassemble the
instruction to compute the out-of-range virtual address of the target.
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