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7. UltraSPARC External Interfaces
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As an interconnect slave, UltraSPARC responds to noncached reads of its
interconnect port ID, which are generated by other UltraSPARCs on the
interconnect. Slave Writes to UltraSPARC are not supported.
UltraSPARC is both an interrupter and an interrupt receiver. It can generate inter-
rupt requests to other interrupt receivers, and it can receive interrupt requests
from other interrupters. UltraSPARC cannot send an interrupt to itself.
7.2.1 The System Data Bus (SYSDATA)
SYSDATA is a 128-bit bidirectional data bus, with 16 additional bits dedicated to
ECC. Each chip within the two-chip UDB handles 64 bits of SYSDATA. The ECC
bits are divided into two 8-bit halves, one for each 64-bit half of SYSDATA.
The ECC bits use Shigeo Kaneda’s 64-bit SEC-DED-SbED code. (Kaneda’s paper
discussing this algorithm is documented in the Bibliography.) The UDBs generate
ECC when sending data and check the ECC when receiving data.
The SYSDATA transaction set supports both 64-byte block transfers and 1..16-
byte single quadword noncached transfers. Single quadword transfers are quali-
fied with a 16-bit bytemask, included with the original transfer request. Data is
always transferred in units of 16 bytes/clock-cycle on SYSDATA.
Note:
In this chapter, 64-byte transfers on SYSDATA are called “block reads”
and “block writes.” Do not confuse these with “block loads” and “block stores,”
which are extended instructions in the UltraSPARC instruction set.
The system uses the S_REPLY pins to initiate the data part of data transfers be-
tween the System Data Bus and UltraSPARC. For block transfers, if the system
cannot read or write successive quadwords in successive clock cycles, it asserts
the Data_Stall signal to UltraSPARC.
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