Sun Microelectronics
283
17. Grouping Rules and Stalls
•
Floating-point/graphics
Note:
CALL
,
RETURN
,
JMPL
,
BPr
,
PST
and
FCMP{LE,NE,GT,EQ}{16,32}
belong to
multiple categories.
17.3 Instruction Availability
Instruction dispatch is limited to the number of instructions available in the in-
struction buffer. Several factors limit instruction availability. UltraSPARC fetches
up to four instructions per clock from an aligned group of eight instructions.
When the fetch address mod 32 is equal to 20, 24, or 28, then three, two, or one
instruction(s) respectively will be added to the instruction buffer. The next cache
line and set are predicted using a next field and set predictor for each aligned
four instructions in the instruction cache. When a set or next field mispredict oc-
curs, instructions are not added to the instruction buffer for two clocks.
When an I-Cache miss occurs, instructions are added to the instruction buffer as
data is returned from the E-Cache. For an E-Cache hit, this results in a five to six
clock delay in adding instructions to the buffer. Up to eight sequential instruc-
tions are added for each I-Cache miss. The next fetch from the I-Cache will not
add instructions to the instruction buffer for one to two clocks after the E-Cache
instructions are added. Back-to-back I-Cache misses will occur at a maximum rate
of eight clocks each for E-Cache hits.
E-Cache misses and arbitration for E-Cache cause additional delay in adding in-
structions to the buffer. An E-Cache miss has a delay of at least eleven clocks,
plus the System Interconnect latency for the first word of the block. An I-Cache
miss and E-Cache hit following an E-Cache miss returns instructions eight clocks
after the last word of data from the E-Cache miss is delivered on the system inter-
connect.
17.4 Single Group Instructions
Certain instructions are always dispatched by themselves to simplify the hard-
ware. These instructions are:
LDD(A)
,
STD(A)
, block load instructions (
LDDF{A}
with an ASI of 70
16
, 71
16
, 78,
16
79
16
, F0
16
, F1
16
, F8
16
, F9
16
),
ADDC{cc}
,
SUBC{cc}
,
{F}
MOVcc
,
{F}MOVr
,
SAVE
,
RESTORE
,
{U,S}MUL{cc)
,
MULX
,
MULScc
,
{U,S}DIV{X}
,
{U,S}DIVcc
,
LDSTUB{A}
,
SWAP{A}
,
CAS{X}A
,
LD{X}FSR
,
ST{X}FSR
,
SAVED
,
RESTORED
,
FLUSH{W}
,
ALIGNADDR
,
RETURN
,
DONE
,
RETRY
,
WR{PR}
,
RD{PR}
,
Tcc
,
SHUT-
DOWN
, and the second control transfer instruction of a DCTI couple.
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