Sun Microelectronics
61
6. MMU Internal Architecture
6.9.5.2 D-MMU Fault Address
The Synchronous Fault Address register contains the virtual memory address of
the fault recorded in the D-MMU Synchronous Fault Status register. There is no
I-SFAR, since the instruction fault address is found in the trap program counter
(TPC). The SFAR can be considered an additional field of the D-SFSR.
Figure 6-8 illustrates the D-SFAR.
Figure 6-8
D-MMU Synchronous Fault Address Register (SFAR) Format
Fault Address
: The virtual address associated with the translation fault recorded
in the D-SFSR. This field is valid only when the D-SFSR Fault Valid (FV)
bit is set. This field is sign-extended based on VA<43>, so bits VA<63:44>
do not correspond to the virtual address used in the translation for the
case of a VA-out-of-range
data_access_exception
trap. (For this case,
software must disassemble the trapping instruction.)
6.9.6 I-/D- Translation Storage Buffer (TSB) Registers
The TSB registers provide information for the hardware formation of TSB point-
ers and tag target, to assist software in handling TLB misses quickly. If the TSB
concept is not employed in the software memory management strategy, and
therefore the pointer and tag access registers are not used, then the TSB registers
need not contain valid data.
Figure 6-9 illustrates the TSB register.
Figure 6-9
I-/D-TSB Register Format
I/D TSB_Base<63:13>
: Provides the base virtual address of the Translation
Storage Buffer. Software must ensure that the TSB Base is aligned on a
boundary equal to the size of the TSB, or both TSBs in the case of a split
TSB.
Warning –
Stores to the TSB registers are not checked for out-of-range violations.
Reads from these registers are sign-extended based on TSB_Base<43>.
63
0
Fault Address (VA<63:0>)
63
3 2
0
TSB_Base<63:13> (virtual)
TSB_Size
13
12
Split
—
11
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
