Sun Microelectronics
80
UltraSPARC User’s Manual
Figure 7-4
Timing for Coherent Read Hit (2–2 Mode)
7.3.2.2 Coherent Write Hits (1–1–1 and 2–2 Modes)
Writes to the E-Cache are processed through independent tag and data transac-
tions. First, UltraSPARC reads the tag and state bits of the E-Cache line. If the ac-
cess is a hit and the tag state is Exclusive (E) or Modified (M), UltraSPARC writes
the data to the data RAM.
Figure 7-5 on page 81 shows the 1–1–1 Mode timing for three consecutive write
hits to M state lines. Access to the first tag (D0_tag) is started by asserting TOE_L
and by sending the tag address (A0_tag). In the cycle after the tag data (D0_tag)
comes back, UltraSPARC determines that the access is a hit and that the line is in
Modified (M) state. In the next clock, a request is made to write the data. The
data address is presented on the ECAD pins in the cycle after the request (cycle 6
for W0) and the data is sent in the following cycle (cycle 7). Separating the ad-
dress and the data by one cycle reduces the turn-around penalty when reads are
followed immediately by writes (discussed in Section 7.3.2.4, “Coherent Read
Followed by Coherent Write).
Figure 7-6 on page 81 shows the 2–2 Mode timing for three consecutive write hits
to M state lines. Access to the first tag (D0_tag) is started by asserting TOE_L and
by sending the tag address (A0_tag). In the cycle after the tag data (D0_tag)
comes back, UltraSPARC determines that the access is a hit and that the line is in
Modified (M) state. In the next clock, a request is made to write the data. The
SRAM CYCLE
0
1
2
3
4
5
6
TSYN_WR_L
R0
R1
R2
TOE_L
R0
R1
R2
ECAT
A0_tag
A1_tag
A2_tag
TDATA
D0_tag
D1_tag
D2_tag
DSYN_WR_L
R0
R1
R2
DOE_L
R0
R1
R2
ECAD
A0_data
A1_data
A2_data
EDATA
D0_data
D1_data
D2_data
CPU CLK
SRAM CLK
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