Sun Microelectronics
38
UltraSPARC User’s Manual
5.3.6 Block Loads and Stores
Block load and store instructions work like normal floating-point load and store
instructions, except that the data size (granularity) is 64 bytes per transfer. See
Section 13.6.4, “Block Load and Store Instructions,” on page 230 for a full descrip-
tion of the instructions.
5.3.7 I/O and Accesses with Side-effects
I/O locations may not behave with memory semantics. Loads and stores may
have side-effects; for example, a read access may clear a register or pop an entry
off a FIFO. A write access may set a register address port so that the next access
to that address will read or write a particular internal registers, etc. Such devices
are considered order sensitive. Also, such devices may only allow accesses of a
fixed size, so store buffer merging of adjacent stores or stores within a 16-byte re-
gion will cause an access error.
The UltraSPARC MMU includes an attribute bit (the E-Bit) in each page transla-
tion, which, when set, indicates that access to this page cause side effects. Access-
es other than block loads or stores to pages that have this bit set have the
following behavior:
•
Noncacheable accesses are strongly ordered with respect to each other
•
Noncacheable loads with the E-bit set will not be issued until all previous
control transfers (including exceptions) are resolved.
•
Store buffer compression is disabled for noncacheable accesses.
•
Non-faulting loads are not allowed and will cause a
data_access_exception
trap
(with SFSR.FT = 2, speculative load to page marked E-bit).
•
A MEMBAR may be needed between side-effect and non-side-effect accesses
while in PSO and RMO modes.
5.3.8 Instruction Prefetch to Side-Effect Locations
UltraSPARC does instruction prefetching and follows branches that it predicts
will be taken. Addresses mapped by the I-MMU may be accessed even though
they are not actually executed by the program. Normally, locations with side ef-
fects or those that generate time-outs or bus errors will not be mapped by the
I-MMU, so prefetching will not cause problems. When running with the I-MMU
disabled, however, software must avoid placing data in the path of a control
transfer instruction target or sequentially following a trap or conditional branch
instruction. Data can be placed sequentially following the delay slot of a BA(,pt),
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