Sun Microelectronics
177
11. Error Handling
destroyed, but no other state will be corrupted. If TPC is pointing to the
MEMBAR
#Sync
following the access, then the
data_access_error
trap handler
knows that a recoverable error has occurred and resumes execution after
setting a status flag. The trap handler must set TNPC to TPC + 4 before
resuming, because the contents of TNPC are otherwise undefined.
When a deferred error occurs, trap handler execution is delayed until all out-
standing accesses are completed. This delay avoids entering RED_state due to
multiple errors. Any subsequent errors detected during this waiting period will
be properly logged. Errors that occur after the trap handler begins will be due to
an access from inside the trap handler. The instruction and data caches are dis-
abled by clearing the IC and DC bits in the LSU_Control_Register. This is because
corrupted data may be placed in the cache if the access was cacheable. The caches
must be reenabled by software after flushing to remove the corrupted data. In
case of an instruction error, the instruction returned to the CPU is marked for ter-
mination (to be aborted). This means that a bad instruction will not create pro-
grammer-visible side-effects.
The following is a possible sequence for handling deferred errors. Within the trap
handler,
1.
Log the error(s).
2.
Reset the error logging bits in AFSR and UDB error registers if needed.
Perform a MEMBAR
#Sync
to complete internal ASI stores.
3.
If AFSR.PRIV is set and not performing an intentional peek/poke, panic;
otherwise, try to continue.
4.
Displacement flush the entire E-Cache. This will remove corrupted data
from I-, D-, and E-Caches. This step is not necessary for known non-
cacheable accesses.
5.
Reenable I- and D-Caches by setting the IC and DC bits of the
LSU_Control_Register. Perform a MEMBAR
#Sync
to complete internal
ASI stores.
6.
Abort the current process.
7.
If uncorrectable ECC error, and no other processes share the data, perform
a block store to the block address in AFAR to reset ECC. Perform a
MEMBAR
#Sync
to complete the block store.
8.
Resume execution.
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