Sun Microelectronics
262
UltraSPARC User’s Manual
16.2.2 Instruction Alignment
16.2.2.1 I-Cache Organization
The 16 Kb I-Cache is organized as a 2-way set associative cache, with each set
containing 256 eight-instruction lines (Figure 16-1). The 14 bits required to access
any location in the I-Cache are composed of the 13 least significant address bits
(since the minimum page size is 8K, these 13 bits are always part of the page off-
set and need not be translated) and 1 bit used to predict the associativity number
(way) in which instructions reside. Out of a line of 8 instructions, up to 4 instruc-
tions are sent to the instruction buffer, depending on the address. If the address
points to one of the last three instructions in the line, only that instruction and
the ones (0-2) until the end of the line are selected (for simplicity and timing con-
siderations, hardware support for getting instructions from two adjacent lines
was not included). Consequently, on average for random accesses, 3.25 instruc-
tions are fetched from the I-Cache. For sequential accesses, the fetching rate (4 in-
structions per cycle) equals or exceeds the consuming rate of the pipeline (up to 4
instructions per cycle).
Figure 16-1
I-Cache Organization
16.2.2.2 Branch Target Alignment
Given the restriction mentioned above regarding the number of instructions
fetched from an I-Cache access, it is desirable to align branch targets so that
enough instructions will be fetched to match the number of instructions issued in
the first group of the branch target. For instance, if the compiler scheduler indi-
cates that the target can only be grouped with one more instruction, the target
should be placed anywhere in the line except in the last slot, since only one in-
32 bytes
8 instructions
SET 0
SET 1
256 LINEs
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