Sun Microelectronics
324
UltraSPARC User’s Manual
Loads that hit the D-Cache may be placed in the load buffer for a number of rea-
sons; for example, the load buffer was not empty. Such loads may be turned into
misses if a snoop occurs during their stay in the load buffer (due to an external
request or to an E-Cache miss). In this case they do not count as D-Cache read
hits. See Section 16.3, “Data Stream Issues,” on page 272.
DC_wr [PIC0]
D-Cache write references (including accesses that subsequently trap).
NonD-Cacheable accesses are not counted.
DC_wr_hit [PIC1]
D-Cache write hits.
EC_ref [PIC0]
Total E-Cache references. Non-cacheable accesses are not counted.
EC_hit [PIC1]
Total E-Cache hits.
EC_write_hit_RDO [PIC0]
E-Cache hits that do a read for ownership UPA transaction.
EC_wb [PIC1]
E-Cache misses that do writebacks.
EC_snoop_inv [PIC0]
E-Cache invalidates from the following UPA transactions: S_INV_REQ,
S_CPI_REQS_INV_REQ, S_CPI_REQS_INV_REQ, S_CPI_REQ.
EC_snoop_cb [PIC1]
E-Cache snoop copy-backs from the following UPA transactions: S_CPB_REQ,
S_CPI_REQ, S_CPD_REQ, S_CPB_MSI_REQ.
EC_rd_hit [PIC0]
E-Cache read hits from D-Cache misses.
EC_ic_hit [PIC1]
E-Cache read hits from I-Cache misses.
The E-Cache write hit count is determined by subtracting the read hit and the
instruction hit count from the total E-Cache hit count. The E-Cache write refer-
ence count is determined by subtracting the D-Cache read miss (D-Cache read
references minus D-Cache read hits) and I-Cache misses (I-Cache references
minus I-Cache hits) from the total E-Cache references. Because of store buffer
compression, this is not the same as D-Cache write misses.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
