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CXD5602 User Manual

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79/1010

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3.1.4.3.23

SPI3

The following are settings that pin P1f_00, pin P1g_00, pin P1h_00, and pin P1i_{00,01,02} are assigned SPI

role.



IO_SPI3_MISO.ENZI



IOCSYS_IOMD1.SPI3_CS0_X



IOCSYS_IOMD1.SPI3_CS1_X



IOCSYS_IOMD1.SPI3_CS2_X



IOCSYS_IOMD1.SPI3

3.1.4.3.24

I2C0

The following are settings that pin P1j_{00,01} is assigned I2C role.



IO_I2C0_BCK.ENZI



IO_I2C0_BDT.ENZI



IOCSYS_IOMD1.I2C0

3.1.4.3.25

I2C1

The following are settings that pin P1l_{00,01} are assigned I2C role.



IO_PWM2.ENZI



IO_PWM3.ENZI



IOCSYS_IOMD1.PWMB

3.1.4.3.26

PWM

The following are settings that pin P1k_{00,01} and pin P1l_{00,01} are assigned PWM role.



IOCSYS_IOMD1.PWMA



IOCSYS_IOMD1.PWMB

Summary of Contents for CXD5602

Page 1: ...CXD5602 User Manual 1 1010 CXD5602 User Manual ...

Page 2: ... O Processor 38 2 6 Memory Mapping 40 2 6 1 Memory Map of Each Block 41 2 6 2 Main Memory 42 2 6 3 System Memory 43 2 6 4 Backup Memory 43 2 7 Clock and Reset 43 2 7 1 Overview 43 2 7 2 Clock Architecture 46 2 8 Power Management 48 2 8 1 Overview 48 2 8 2 Power Domain 48 2 8 3 Power Supply States 51 3 Function Details 53 3 1 I O Configuration 53 3 1 1 Outline 53 3 1 2 Function List 53 3 1 3 Switch...

Page 3: ...t Clock Reset Generator 158 3 5 1 Overview 158 3 5 2 Clock Scheme for CRG 158 3 5 3 Analog Circuits 160 3 5 4 Clock Setting Confirmation 163 3 5 5 Power Domain Reset 166 3 5 6 Reset by WDT 167 3 6 RTC 170 3 6 1 Outlines and Features 170 3 6 2 Clock Input 171 3 6 3 Function List 172 3 6 4 Function Block Diagrams 172 3 6 5 Detailed Function and Control Specification 175 3 7 I2C 212 3 7 1 Features an...

Page 4: ...9 14 Error Handling 856 3 9 15 Restrictions 857 3 10 SPI 873 3 10 1 Features and Overview 873 3 10 2 SPI0 874 3 10 3 SPI3 878 3 10 4 SPI4 880 3 10 5 SPI5 882 3 11 UART 884 3 11 1 Overview and Features 884 3 11 2 UART1 885 3 11 3 UART2 886 3 12 GNSS 889 3 13 APP 891 3 13 1 Function Overview 891 3 13 2 Power Supply Control 894 3 13 3 Clock Reset Control 895 3 13 4 Description of APP_DSP Function 906...

Page 5: ...et Control 962 3 21 7 Interrupt 962 3 21 8 FIFO writing Process 962 3 21 9 Gain Control 963 3 21 10 Performance Estimation 965 3 21 11 Synchronization Function with PWM 966 3 21 12 ADC Control Register Details 966 3 21 13 ADC Control Sequence 1002 3 21 14 Restrictions 1002 3 21 15 Error Handling 1003 4 Appendix 1004 4 1 Words and Terms 1004 4 1 1 Words and Terms Used in This User Manual 1004 4 2 R...

Page 6: ... Diagram of GPIO Event Detect Block 88 Figure General Purpose Input Output GPIO 17 Output Signal Route in the I O Function Controlled by GPIO Parameter 91 Figure General Purpose Input Output GPIO 18 Input Signal Route in the I O Function Controlled by GPIO Parameter 92 Figure General Purpose Input Output GPIO 19 GPIO Pin Selection 93 Figure General Purpose Input Output GPIO 20 External Interrupt S...

Page 7: ...igure SCU Sensor Control Unit 52 Memory Mapping from the Upper CPUs the CPU in the SYSIOP and the CPU in the GNSS hereinafter in the Chapter on SCU referred as upper CPUs 246 Figure SCU Sensor Control Unit 53 Memory Mapping within the SCU as seen from the Upper CPUs 247 Figure SCU Sensor Control Unit 54 Memory Mapping as seen from the Internal Sequencer 248 Figure SCU Sensor Control Unit 55 Memory...

Page 8: ...g ADC Timing as a Reference 303 Figure SCU Sensor Control Unit 85 ADC Data Capture Mode using the PWM Output Timing as a Reference 306 Figure SCU Sensor Control Unit 86 Processing Block Overview 354 Figure SCU Sensor Control Unit 87 Filter Overview 356 Figure SCU Sensor Control Unit 88 Excess Detection Overview 392 Figure SCU Sensor Control Unit 89 I2C Master Control Example 860 Figure SCU Sensor ...

Page 9: ... Exclusive Access 925 Figure APP 113 Failure Case 1 of Exclusive Access 926 Figure APP 114 Failure Case 2 of Exclusive Access 926 Figure APP 115 Failure Case 3 of Exclusive Access 926 Figure SYSIOP Clock and Reset Control 116 SYSIOP Clock Configuration Diagram 936 Figure SYSIOP Clock and Reset Control 117 SYSIOP Reset Configuration Diagram 950 Figure ADC 118 Block Diagram ADCIF module and around A...

Page 10: ...trollable I O Pins 67 Table I O Configuration 16 Overview of Registers for Selecting Output Function of I2S 68 Table I O Configuration 17 Overview of Register for Selecting PDM_CLK Output Function 68 Table I O Configuration 18 Overview of Registers for Selecting Input Value to SDIO 69 Table General Purpose Input Output GPIO 19 Function List 86 Table General Purpose Input Output GPIO 20 GPIO Contro...

Page 11: ... PMU Power Management Unit 49 Current Adjustment Setting 147 Table PMU Power Management Unit 50 SYSPLL Division Ratio Setting 149 Table Clock and Reset Clock Reset Generator 51 RCOSC Block Status Registers 160 Table Clock and Reset Clock Reset Generator 52 XOSC Block Status Register 161 Table Clock and Reset Clock Reset Generator 53 SYSPLL Frequency Confirmation 162 Table Clock and Reset Clock Res...

Page 12: ...tion Interrupts 257 Table SCU Sensor Control Unit 99 System Error Interrupts 258 Table SCU Sensor Control Unit 100 Interrupts for the Sequencers 259 Table SCU Sensor Control Unit 101 Internal Sequencer Interrupts 259 Table SCU Sensor Control Unit 102 Partition Name and Writing Port Readout Port 271 Table SCU Sensor Control Unit 103 Writing Port and Readout Port Addresses 272 Table SCU Sensor Contr...

Page 13: ...ontrol Unit 133 340 Table SCU Sensor Control Unit 134 341 Table SCU Sensor Control Unit 135 342 Table SCU Sensor Control Unit 136 343 Table SCU Sensor Control Unit 137 345 Table SCU Sensor Control Unit 138 347 Table SCU Sensor Control Unit 139 348 Table SCU Sensor Control Unit 140 348 Table SCU Sensor Control Unit 141 349 Table SCU Sensor Control Unit 142 351 Table SCU Sensor Control Unit 143 353 ...

Page 14: ...ontrol Unit 172 370 Table SCU Sensor Control Unit 173 370 Table SCU Sensor Control Unit 174 371 Table SCU Sensor Control Unit 175 371 Table SCU Sensor Control Unit 176 372 Table SCU Sensor Control Unit 177 372 Table SCU Sensor Control Unit 178 373 Table SCU Sensor Control Unit 179 373 Table SCU Sensor Control Unit 180 374 Table SCU Sensor Control Unit 181 375 Table SCU Sensor Control Unit 182 375 ...

Page 15: ...ontrol Unit 211 391 Table SCU Sensor Control Unit 212 391 Table SCU Sensor Control Unit 213 392 Table SCU Sensor Control Unit 214 393 Table SCU Sensor Control Unit 215 393 Table SCU Sensor Control Unit 216 394 Table SCU Sensor Control Unit 217 395 Table SCU Sensor Control Unit 218 396 Table SCU Sensor Control Unit 219 396 Table SCU Sensor Control Unit 220 397 Table SCU Sensor Control Unit 221 398 ...

Page 16: ...ontrol Unit 250 427 Table SCU Sensor Control Unit 251 429 Table SCU Sensor Control Unit 252 431 Table SCU Sensor Control Unit 253 432 Table SCU Sensor Control Unit 254 433 Table SCU Sensor Control Unit 255 434 Table SCU Sensor Control Unit 256 435 Table SCU Sensor Control Unit 257 436 Table SCU Sensor Control Unit 258 438 Table SCU Sensor Control Unit 259 440 Table SCU Sensor Control Unit 260 442 ...

Page 17: ...ontrol Unit 289 469 Table SCU Sensor Control Unit 290 470 Table SCU Sensor Control Unit 291 471 Table SCU Sensor Control Unit 292 472 Table SCU Sensor Control Unit 293 473 Table SCU Sensor Control Unit 294 474 Table SCU Sensor Control Unit 295 475 Table SCU Sensor Control Unit 296 476 Table SCU Sensor Control Unit 297 477 Table SCU Sensor Control Unit 298 478 Table SCU Sensor Control Unit 299 479 ...

Page 18: ...28 501 Table SCU Sensor Control Unit 329 502 Table SCU Sensor Control Unit 330 503 Table SCU Sensor Control Unit 331 504 Table SCU Sensor Control Unit 332 505 Table SCU Sensor Control Unit 333 505 Table SCU Sensor Control Unit 334 506 Table SCU Sensor Control Unit 335 507 Table SCU Sensor Control Unit 336 507 Table SCU Sensor Control Unit 337 SCU_FIFO_REG Register List 508 Table SCU Sensor Control...

Page 19: ...ontrol Unit 367 541 Table SCU Sensor Control Unit 368 542 Table SCU Sensor Control Unit 369 543 Table SCU Sensor Control Unit 370 544 Table SCU Sensor Control Unit 371 545 Table SCU Sensor Control Unit 372 545 Table SCU Sensor Control Unit 373 546 Table SCU Sensor Control Unit 374 547 Table SCU Sensor Control Unit 375 548 Table SCU Sensor Control Unit 376 549 Table SCU Sensor Control Unit 377 549 ...

Page 20: ...ontrol Unit 406 573 Table SCU Sensor Control Unit 407 573 Table SCU Sensor Control Unit 408 574 Table SCU Sensor Control Unit 409 575 Table SCU Sensor Control Unit 410 576 Table SCU Sensor Control Unit 411 577 Table SCU Sensor Control Unit 412 577 Table SCU Sensor Control Unit 413 578 Table SCU Sensor Control Unit 414 579 Table SCU Sensor Control Unit 415 580 Table SCU Sensor Control Unit 416 581 ...

Page 21: ...ontrol Unit 445 601 Table SCU Sensor Control Unit 446 602 Table SCU Sensor Control Unit 447 603 Table SCU Sensor Control Unit 448 604 Table SCU Sensor Control Unit 449 605 Table SCU Sensor Control Unit 450 605 Table SCU Sensor Control Unit 451 606 Table SCU Sensor Control Unit 452 606 Table SCU Sensor Control Unit 453 607 Table SCU Sensor Control Unit 454 608 Table SCU Sensor Control Unit 455 609 ...

Page 22: ...ontrol Unit 484 630 Table SCU Sensor Control Unit 485 630 Table SCU Sensor Control Unit 486 631 Table SCU Sensor Control Unit 487 631 Table SCU Sensor Control Unit 488 632 Table SCU Sensor Control Unit 489 633 Table SCU Sensor Control Unit 490 634 Table SCU Sensor Control Unit 491 635 Table SCU Sensor Control Unit 492 636 Table SCU Sensor Control Unit 493 636 Table SCU Sensor Control Unit 494 637 ...

Page 23: ...ontrol Unit 523 661 Table SCU Sensor Control Unit 524 662 Table SCU Sensor Control Unit 525 663 Table SCU Sensor Control Unit 526 664 Table SCU Sensor Control Unit 527 665 Table SCU Sensor Control Unit 528 666 Table SCU Sensor Control Unit 529 666 Table SCU Sensor Control Unit 530 667 Table SCU Sensor Control Unit 531 668 Table SCU Sensor Control Unit 532 669 Table SCU Sensor Control Unit 533 670 ...

Page 24: ...ontrol Unit 562 694 Table SCU Sensor Control Unit 563 695 Table SCU Sensor Control Unit 564 696 Table SCU Sensor Control Unit 565 696 Table SCU Sensor Control Unit 566 697 Table SCU Sensor Control Unit 567 698 Table SCU Sensor Control Unit 568 699 Table SCU Sensor Control Unit 569 700 Table SCU Sensor Control Unit 570 701 Table SCU Sensor Control Unit 571 701 Table SCU Sensor Control Unit 572 702 ...

Page 25: ...ontrol Unit 601 726 Table SCU Sensor Control Unit 602 727 Table SCU Sensor Control Unit 603 728 Table SCU Sensor Control Unit 604 729 Table SCU Sensor Control Unit 605 730 Table SCU Sensor Control Unit 606 731 Table SCU Sensor Control Unit 607 731 Table SCU Sensor Control Unit 608 732 Table SCU Sensor Control Unit 609 733 Table SCU Sensor Control Unit 610 734 Table SCU Sensor Control Unit 611 735 ...

Page 26: ...ontrol Unit 640 759 Table SCU Sensor Control Unit 641 760 Table SCU Sensor Control Unit 642 761 Table SCU Sensor Control Unit 643 761 Table SCU Sensor Control Unit 644 762 Table SCU Sensor Control Unit 645 763 Table SCU Sensor Control Unit 646 764 Table SCU Sensor Control Unit 647 765 Table SCU Sensor Control Unit 648 766 Table SCU Sensor Control Unit 649 766 Table SCU Sensor Control Unit 650 767 ...

Page 27: ...Unit 680 792 Table SCU Sensor Control Unit 681 793 Table SCU Sensor Control Unit 682 794 Table SCU Sensor Control Unit 683 795 Table SCU Sensor Control Unit 684 796 Table SCU Sensor Control Unit 685 796 Table SCU Sensor Control Unit 686 797 Table SCU Sensor Control Unit 687 798 Table SCU Sensor Control Unit 688 799 Table SCU Sensor Control Unit 689 800 Table SCU Sensor Control Unit 690 SCU_RAM Par...

Page 28: ...IFO Writing Side Initial Settings 836 Table SCU Sensor Control Unit 722 FIFO Readout Side Initial Settings 840 Table SCU Sensor Control Unit 723 FIFO Write Processing 844 Table SCU Sensor Control Unit 724 FIFO Readout Processing 846 Table SCU Sensor Control Unit 725 Transition Process to FIFO 8 KByte Retention 854 Table SCU Sensor Control Unit 726 Transition Process to FIFO 8 KByte All ON 855 Tabl...

Page 29: ...essor List 912 Table APP 787 WDTRES Register List 915 Table APP 788 SLEEPING Signal Register List 915 Table APP 789 Debug Function List 916 Table APP 790 Address Conversion Registers 921 Table APP 791 Exclusive Access Register 924 Table SYSIOP Clock and Reset Control 796 XOSC 26 MHz High Performance Mode 936 Table SYSIOP Clock and Reset Control 797 XOSC 26 MHz Low Power Mode 937 Table SYSIOP Clock...

Page 30: ...0 SCU_ADCIF_REG Register List 967 Table ADC 821 968 Table ADC 822 969 Table ADC 823 970 Table ADC 824 971 Table ADC 825 972 Table ADC 826 973 Table ADC 827 975 Table ADC 828 977 Table ADC 829 979 Table ADC 830 980 Table ADC 831 981 Table ADC 832 982 Table ADC 833 983 Table ADC 834 984 Table ADC 835 985 Table ADC 836 988 Table ADC 837 989 Table ADC 838 990 Table ADC 839 991 Table ADC 840 992 Table ...

Page 31: ...merical value only 256 Base 2 adds prefixed bit width b 4 b1010 Numerical numbers are noted in the format shown below when the status of the signal signed unsigned and the position of the decimal point should be indicated sign bit number of integer part bit number of decimal part In the sign U or S is described U represents unsigned and S signed When the sign is U bit number of integer part plus b...

Page 32: ...eger number is noted as U5 0 5 bit unsigned signal with decimal point 1 0 position is noted as U4 1 5 bit unsigned signal with decimal point 1 2 position is noted as U6 1 5 bit signed signal with integer number is noted as S4 0 5 bit signed signal with decimal point 1 0 position is noted as S3 1 ...

Page 33: ... GNSS Domain Audio Codec Domain and Sensor Domain Integrated Audio Codec Domain supports digital noise cancelling and digital equalizer Sensor Domain provides the specialized engine for sensor processing Eliminating the need for a discrete sensor hub these features enable various sensor applications activity recognition voice recognition etc low power audio applications such as music playback MP3 ...

Page 34: ... at 1 0 V 256 KByte SRAM 128 KByte ROM for secure booting System and IOP Domain multi layer bus 32 bit Multi layer bus architecture SYSIOP for Arm Cortex M0 32 bit RISC PMU GNSS Sensor engine HostIF Configurable IO Power management I2C and GPIO interface connections to Power Management IC assuming CXD5247GF power on reset power gate control Clock and Reset management X tal RTC RCOSC PLL 64 KByte B...

Page 35: ...it RISC Operating frequency up to 98 208 MHz 64 KByte ROM 640 KByte SRAM CORDIC engine for GNSS support Multi GNSS receiver GPS L1 C A GLONASS L1OF QZSS L1 C A L1 SAIF SBAS L1 C A WAAS EGNOS MSAS BeiDou B1 Galileo E1 CBOC Configurable I O I2C SPI GPIO Interfaces Debug Serial wire debug SWD Embedded Trace Macrocell UART supported ...

Page 36: ...CXD5602 User Manual 36 1010 2 3 Block Diagram Figure Block Diagram 1 CXD5602 Block Diagram ...

Page 37: ...ex M4 for the APP The CXD5602 has a bus architecture using the Bus Matrix so that eight CPUs and the other bus masters can independently access to each slave not affected by any bus traffic By Round robin arbitration inside the Bus Matrix bus master need not to wait for a long time to access to slave even if access competition occurs As Figure Block Diagram 1 shows each bus in the APP SYSIOP GNSS ...

Page 38: ...sor system peripherals Programmable Interrupts Controller 128 channel peripheral Interrupt support for each processor Timers AMBA Design Kit ADK SP804 Two channel supported One Timer module for each processor Total Six Timers Watchdog Timer AMBA Design Kit ADK SP805 One channel for each processor Total Six Watchdog Timers 2 5 2 System and I O Processor The I O processor integrates Cortex M0 to mee...

Page 39: ...ssor system peripherals Inter processor communication unit communication FIFO Tx Rx support 16 binary semaphores support Programmable Interrupts Controller One channel software Generated Interrupt for each processor 128 channel shared peripheral Interrupts for the application processors Timers AMBA Design Kit ADK SP804 Two channel supported Watchdog Timer AMBA Design Kit ADK SP805 One channel supp...

Page 40: ...own processor The SYS Window defines addresses of the master device and the slave device inside the SYSIOP and the SCU The GNSS Window defines addresses of the master device and the slave device inside the GNSS the APP Window inside the APP as well Figure Memory Mapping 2 shows memory map configuration APP Window GNSS Window SYS Window SYS View APP Window GNSS Window SYS Window GNSS View APP Windo...

Page 41: ...4121000 0x04121FFF 4K SYDMAC 0x04122000 0x04122FFF 4K SYSUBDMAC 0x04123000 0x04123FFF 4K Reserved Reserved 0x04124000 0x0417FFFF 368K SCU FIFO Control 0x04180000 0x04182FFF 12K FIFO 40K 0x04183000 0x0418CFFF 40K SPI3 0x0418D000 0x0418D3FF 1K I2C0 0x0418D400 0x0418D7FF 1K I2C1 0x0418D800 0x0418DBFF 1K HPADC LPADC 0x0418DC00 0x0418DFFF 1K Reserved 0x0418E000 0x0418FFFF 8K Sensor Engine 0x04190000 0x...

Page 42: ... made up of 128 KByte Logic Tiles Each of them has the AHB I F individually In addition the Logic Tile is the unit for the SRAM access protection function You can use protection feature that keeps masters with specific Master ID from accessing specific SRAM Logic Tiles The protection feature can be controlled via buses Power domain of Main Memory is PWD_APP When PWD_APP is turned off this memory c...

Page 43: ... two operation modes for the SRAM power off Retention mode and Shutdown mode They can be set by system control registers 2 6 4 Backup Memory There is 64 KByte SRAM in total which is connected to the AHB in System and IOP Domain for backup You can use protection feature that keeps masters with specific Master ID from accessing specific SRAM Logic Tiles The protection feature can be controlled via b...

Page 44: ...lock incorporates POR system XOSC X tal Oscillator Clock X tal 26MHz can be used as CPU operation clock in addition can be supplied to SYSPLL and RFPLL as reference clock SYSPLL Clock incorporates low power PLL which realizes high CPU operation frequency without any input of high speed clock from outside Following frequencies can be selected as SYSPLL clock according to the combination of suitable...

Page 45: ...602 User Manual 45 1010 System reset from Watchdog Timer WDT It is a whole chip reset controlled by the WDT of the SYSCPU You can enable disable whole chip reset controlled by the WDT with register setting ...

Page 46: ...s the SYSPLL the XOSC the RCOSC and the RTC can be selected and can be switched dynamically in accordance with the use case The System and I O Processor can change the frequency dynamically with the frequency divider Sensor Domain Three clock sources the RTC XOSC and RCOSC can be selected GNSS Domain The clock selected by the System and I O Processor in the System and IOP Domain is distributed to ...

Page 47: ... and IOP Domain System and I O Processor SYSIOP Bus Peripheral Debug Sensor Domain GNSS Domain GNSS DSP BB ITP PMU RTC Divider Divider 66 4MHz RFPLL 65 472MHz SYSPLL 16 6MHz RFPLL 16 368MHz SYSPLL APP Bus Peripheral AHB Divider 49 104MHz Divider 49 104MHz 100MHz High performance mode 32MHz Low Power mode Divider Divider Divider Divider AHB APB 100MHz High performance mode 32MHz Low Power mode Divi...

Page 48: ... Power Domain The 11 power domains comprise a layer structure as shown in Figure Power Management 4 The lower layer power domains cannot be turned ON when the upper layer power domains are OFF Furthermore PWD_GNSS can be turned ON only when both PWD_GNSS_ITP and PWD_SYSIOP are ON VDD_CORE PWD_PMU PWD_SCU PWD_CORE PWD_GNSS_ITP PWD_SYSIOP PWD_SYSIOP_SUB PWD_GNSS PWD_APP PWD_APP_DSP PWD_APP_SUB PWD_A...

Page 49: ...M H P A D C L P A D C S P I 2 I 2 C 3 U A R T 0 S P I 0 I 2 C 2 Async Async Async Async USB RTC1 CRG FREQDISC Audio Codec GPIO PDM I2S0 ADMAC debugger I F APB INTCTL Power Management Clock Reset P W M 4 e fuse RCOSC XOSC SysPLL I2C4 SRAM 256KB RTC Clock I2S1 IOCTRL APB Async Sync Up Down AHB to AHB U A R T 1 IDMAC Sync Sync SPI Flash Controller SYSUB DMAC Sync PWD_PMU PWD_APP PWD_APP_DSP PWD_APP_S...

Page 50: ...main Including 256 KByte SRAM in System and I O Processor Memory Including 640 KByte SRAM in GNSS Memory Including ALIVE I O I2C GPIO Including GNSS RF Including Key generation in System and IOP Domain ALIVE I2C GNSS Domain PWD_GNSS Components of GNSS Domain Excluding RF and 640 KByte SRAM in GNSS Memory PWD_GNSS_ITP ITP Block in GNSS Domain Sensor Domain PWD_SCU Components of sensor engine Includ...

Page 51: ...e LSI is being reset 4 Normal The LSI and the CXD5247 are both ON and the System Control PWD_SYSIOP turns ON enabling power supply control of each Domain The state begins from Power OFF and after the CXD5247 starts power is supplied to the LSI and a reset is enabled changing the state to Reset After releasing the reset of the LSI the System Control of the System and IOP Domain is automatically sta...

Page 52: ... PMIC State Deep Sleep Application Domain ON GNSS Domain OFF Sensor Domain OFF CXD5602 ON Application Domain OFF GNSS Domain ON Sensor Domain OFF CXD5602 ON Application Domain ON GNSS Domain ON Sensor Domain OFF CXD5602 ON Application Domain OFF GNSS Domain OFF Sensor Domain ON CXD5602 ON Application Domain ON GNSS Domain OFF Sensor Domain ON CXD5602 ON Application Domain OFF GNSS Domain ON Sensor...

Page 53: ...I O Configuration 5 shows I O Configuration function list Table I O Configuration 5 Function List No Function Name Description 1 Switching between HOST I F select function and SWD function This function decides communication tools After it decides a HOST I F it switches SYSTEM0 1 pin to use as SWD 2 Pin Multiplexer To a pin Pin Multiplexer can assign a role selecting from up to four options Multip...

Page 54: ...SWD control HOSTIFC I2C UART SPI Hold SYSTEM0 1 CXD5602 Debugger Host I F select signal 0 1 POR Delay 0 1 Hold SYSTEM0 1 SWD control HOSTIFC I2C UART SPI Select Host I F Switched to SWD control SYSTEM0 1 switched to SWD control Host I F select signal LL HL LH LL HL LH Figure I O Configuration 7 Switching between HOST I F Function and SWD Function Table I O Configuration 6 shows HOST I F decided in...

Page 55: ...IO when SDIO function is not used Table I O Configuration 7 List of Registers for Controlling Pin Multiplexer Address Register Name Attrib ute Function Initial Value 0x041007C0 IOCSYS_IOMD0 RW selects pin function System 0x00000000 0x041007C4 IOCSYS_IOMD1 RW selects pin function System 0x00000000 0x041014A0 IOCAPP_IOMD RW selects pin function Application 0x00000000 Table I O Configuration 8 List o...

Page 56: ...100 0x04100880 IO_HIF_GPIO0 RW IOCELL setting for pin P03_00 0x01010100 0x04100884 0x04100890 Reserved R0 Reserved 0x00000000 0x04100894 IO_SEN_IRQ_IN RW IOCELL setting for pin P1e_00 0x01010100 0x04100898 IO_SPI3_CS0_X RW IOCELL setting for pin P1f_00 0x01010100 0x0410089C IO_SPI3_CS1_X RW IOCELL setting for pin P1g_00 0x01010100 0x041008A0 IO_SPI3_CS2_X RW IOCELL setting for pin P1h_00 0x0101010...

Page 57: ...OCELL setting for pin P1o_02 0x01010100 0x04100928 IO_SPI4_MISO RW IOCELL setting for pin P1o_03 0x01010100 0x0410092C IO_EMMC_CLK RW IOCELL setting for pin P1p_00 0x01010100 0x04100930 IO_EMMC_CMD RW IOCELL setting for pin P1p_01 0x01010100 0x04100934 IO_EMMC_DATA0 RW IOCELL setting for pin P1p_02 0x01010100 0x04100938 IO_EMMC_DATA1 RW IOCELL setting for pin P1p_03 0x01010100 0x0410093C IO_EMMC_D...

Page 58: ..._I2S1_DATA_OUT RW IOCELL setting for pin P1w_03 0x01010100 0x04100994 IO_MCLK RW IOCELL setting for pin P1x_00 0x01010100 0x04100998 IO_PDM_CLK RW IOCELL setting for pin P1y_00 0x01010100 0x0410099C IO_PDM_IN RW IOCELL setting for pin P1y_01 0x01010100 0x041009A0 IO_PDM_OUT RW IOCELL setting for pin P1y_02 0x01010100 0x041009A4 IO_USB_VBUSINT RW IOCELL setting for pin P1z_00 0x01010100 Table I O C...

Page 59: ...r Name Bit Field Name Type Bit Initial Value Description 0x041007C0 IOCSYS_ IOMD0 Reserved 31 28 For pin functions selected by IOCSYS_IOMOD1 0 refer to Table I O Configuration 11 HIFEXT RW 27 26 0 HIFIRQ RW 25 24 0 SPI2B RW 23 22 0 SPI2A RW 21 20 0 SPI1B RW 19 18 0 SPI1A RW 17 16 0 SPI0B RW 15 14 0 SPI0A RW 13 12 0 Reserved 11 10 GNSS_1PPS_OUT RW 9 8 0 AP_CLK RW 7 6 0 RTC_IRQ_OUT RW 5 4 0 PMIC_INT...

Page 60: ...d P17_00 IOCSYS_IOMD0 SPI0B GPIO I2C2_BCK SPI0_MOSI Reserved P17_01 GPIO I2C2_BDT SPI0_MISO Reserved P18_00 IOCSYS_IOMD0 SPI1A GPIO SPI1_CS_X SPI0_CS_X Reserved P18_01 GPIO SPI1_SCK SPI0_SCK Reserved P18_02 GPIO SPI0_IO0 SPI0_MOSI Reserved P18_03 GPIO SPI0_IO1 SPI0_MISO Reserved P19_00 IOCSYS_IOMD0 SPI1B GPIO SPI1_IO2 GPIO Reserved P19_01 GPIO SPI1_IO3 GPIO Reserved P00_00 IOCSYS_IOMD0 SPI2A GPIO ...

Page 61: ... Reserved P1i_02 GPIO SPI3_MISO Reserved Reserved P1j_00 IOCSYS_IOMD1 I2C0 GPIO I2C0_BCK Reserved Reserved P1j_01 GPIO I2C0_BDT Reserved Reserved P1k_00 IOCSYS_IOMD1 PWMA GPIO PWM0 Reserved Reserved P1k_01 GPIO PWM1 GPIO Reserved P1l_00 IOCSYS_IOMD1 PWMB GPIO PWM2 I2C1_BCK Reserved P1l_01 GPIO PWM3 I2C1_BDT Reserved ...

Page 62: ...12 Overview of Registers for Selecting a Role of the I O Pins Belonging to APP Group Address Register Name Bit Field Name Type Bit Initial Value Description 0x041014A0 IOCAPP_ IOMD Reserved 31 28 For pin functions selected by IOCAPP_IOMD refer to Table I O Configuration 13 USBVBUS RW 27 26 0 PDM RW 25 24 0 MCLK RW 23 22 0 I2S1 RW 21 20 0 I2S0 RW 19 18 0 SDIOD RW 17 16 0 SDIOC RW 15 14 0 SDIOB RW 1...

Page 63: ...rved GPIO P1n_01 GPIO UART2_RXD Reserved GPIO P1n_02 GPIO UART2_CTS Reserved GPIO P1n_03 GPIO UART2_RTS Reserved GPIO P1o_00 IOCAPP_IOMD SPI4 GPIO SPI4_CS_X Reserved GPIO P1o_01 GPIO SPI4_SCK Reserved GPIO P1o_02 GPIO SPI4_MOSI Reserved GPIO P1o_03 GPIO SPI4_MISO Reserved GPIO P1p_00 IOCAPP_IOMD EMMCA GPIO EMMC_CLK SPI5_SCK GPIO P1p_01 GPIO EMMC_CMD SPI5_CS_X GPIO P1p_02 GPIO EMMC_DATA0 SPI5_MOSI ...

Page 64: ...eserved GPIO P1v_02 GPIO I2S0_DATA_IN Reserved GPIO P1v_03 GPIO I2S0_DATA_OUT Reserved GPIO P1w_00 IOCAPP_IOMD I2S1 GPIO I2S1_BCK Reserved GPIO P1w_01 GPIO I2S1_LRCK Reserved GPIO P1w_02 GPIO I2S1_DATA_IN Reserved GPIO P1w_03 GPIO I2S1_DATA_OUT Reserved GPIO P1x_00 IOCAPP_IOMD MCLK GPIO MCLK Reserved GPIO P1y_00 IOCAPP_IOMD PDM GPIO PDM_CLK Reserved GPIO P1y_01 GPIO PDM_IN GPIO GPIO P1y_02 GPIO PD...

Page 65: ...IO_ 1 Reserved 31 25 LOWEMI RW 24 1 Output Current Control 0 4mA Max64MHz 1 2mA Max32MHz Reserved 23 17 PDN RW 16 1 Pulldown Control 0 Pulldown 1 Normal Reserved 15 9 PUN RW 8 1 Pullup Control 0 Pullup 1 Normal Reserved 7 1 ENZI RW 0 0 Input Enable Control 0 Input Disable 1 Input Enable 1 For pin names corresponding to registers refer to Table I O Configuration 15 The following IOCELL control regi...

Page 66: ...n State GPIO Regs IOCELL LOWEMI IOCELL PDN IOCELL PUP 2 IO Pin Alternate Function Output Alternate Function Input GPIO Regs IOCELL ENZI Output Enable IOCSYS 0 1 IOCAPP Figure I O Configuration 8 Visualized Function inside IOCELL Controlled by IOCELL Control Register ...

Page 67: ...SPI1_SCK P18_01 IO_IS_DATA2 P1m_05 IO_SDIO_DIR0 P1t_01 IO_SPI1_IO0 P18_02 IO_IS_DATA3 P1m_06 IO_SDIO_DIR1_3 P1t_02 IO_SPI1_IO1 P18_03 IO_IS_DATA4 P1m_07 IO_SDIO_CLKI P1u_00 IO_SPI1_IO2 P19_00 IO_IS_DATA5 P1m_08 IO_I2S0_BCK P1v_00 IO_SPI1_IO3 P19_01 IO_IS_DATA6 P1m_09 IO_I2S0_LRCK P1v_01 IO_SPI2_CS_X P00_00 IO_IS_DATA7 P1m_10 IO_I2S0_DATA_IN P1v_02 IO_SPI2_SCK P00_01 IO_UART2_TXD P1n_00 IO_I2S0_DAT...

Page 68: ...e Bit Field Name Type Bit Initial Value Description 0x04101474 IOOEN_APP Reserved 31 8 I2S1_LRCK RW 5 1 0 Output Enable 1 Output Disable I2S1_BCK RW 4 1 0 Output Enable 1 Output Disable Reserved 3 2 I2S0_LRCK RW 1 1 0 Output Enable 1 Output Disable I2S0_BCK RW 0 1 0 Output Enable 1 Output Disable 3 1 4 2 5 PDM_CLK Selection Register This register selects output signals when pin P1y_00 is used as P...

Page 69: ... Initial Value Description 0x04101478 IOFIX_APP Reserved 31 2 SDIO_WP RW 1 1 input value to SDIO_WP when SDIO function is not used SDIO_CD RW 0 1 input value to SDIO_CD when SDIO function is not used 3 1 4 3 Function Details To each pin Pin Multiplexer can assign a role selecting from up to four options Multiple roles cannot be played at a time You can assign roles by setting IOCSYS_IMOD0 1 IOCAPP...

Page 70: ...nout 0 1 2 3 0 IO Configuration IO_SDIO_DATA0 ENZI 2 IOCAPP_IMOD SDIOA 1 SDIO SPI5 0 1 2 3 GPIO Select SDIO_DATA0 inout 0 1 2 3 0 IO Configuration IO_SDIO_DATA0 ENZI 2 IOCAPP_IMOD SDIOA 2 SDIO SPI5 0 1 2 3 GPIO Select SPI5_MOSI output 0 1 2 3 0 1 2 3 1 2 3 Figure I O Configuration 9 Examples of Assigning Roles to the Pin P1r_02 ...

Page 71: ... IOCSYS_IOMD0 I2C4 1 3 1 4 3 2 PMIC_INT The following are settings that pin P11_00 is assigned PMIC_INT role IO_PMIC_INT ENZI 1 IOCSYS_IOMD0 PMIC_INT 1 Note Before receiving PMIC_INT by using the register of RTC 0 1 set External Alarm Output Select Signal to External Interrupt RTC 0 1 _RTC_CTL SYNC_SEL 2 Figure I O Configuration 10 shows the signal routes ...

Page 72: ...2 3 1 GP_PMIC_INT DIR IO_RTC_IRQ_OUT ENZI 2 0 1 2 3 1 2 3 0 1 2 3 1 P12_00 0 0 GP_PMIC_INT OUT IOCSYS_IMOD0 RTC_IRQ_OUT GP_PMIC_INT IN RTC1 OExtAlarm PMIC_INT ExternalAlerm2 ExternalAlerm1 ExternalAlerm0 GP_RTC_IRQ_OUT DIR GP_RTC_IRQ_OUT OUT 0 OPEN OPEN GP_RTC_IRQ_OUT IN OPEN OPEN select PMIC_INT Interrupt to CPU PMIC_INT Figure I O Configuration 10 PMIC_INT Signal Routes MODE 1 ...

Page 73: ...RTC 0 1 _RTC_CTL SYNC_SEL 2 Figure I O Configuration 11 shows the signal routes Besides when you want to use PMIC_INT as CPU interrupt select pin P11_00 using GPIO External Interrupt selection Section 3 2 4 3 GPIO External Interrupt function IO Configuration IO_PMIC_INT ENZI 2 P11_00 IOCSYS_IMOD0 PMIC_INT RTC0 OExtAlarm PMIC_INT ExternalAlerm2 ExternalAlerm1 ExternalAlerm0 0 1 2 3 1 2 3 0 1 2 3 1 ...

Page 74: ...C0_RTC_CTL EXTALM_POL 1 IOCSYS_IOMD0 RTC_IRQ_OUT 2 IO Configuration IO_PMIC_INT ENZI 2 P11_00 IOCSYS_IMOD0 PMIC_INT RTC0 OExtAlarm PMIC_INT ExternalAlerm2 ExternalAlerm2 ExternalAlerm2 0 1 2 3 1 2 3 0 1 2 3 1 GP_PMIC_INT DIR IO_RTC_IRQ_OUT ENZI 2 0 1 2 3 1 2 3 0 1 2 3 1 P12_00 0 0 GP_PMIC_INT OUT IOCSYS_IMOD0 RTC_IRQ_OUT GP_PMIC_INT IN RTC1 OExtAlarm PMIC_INT ExternalAlerm2 ExternalAlerm1 External...

Page 75: ...rain and outputs in negative logic IOCSYS_IOMD0 AP_CLK 3 3 1 4 3 9 GNSS_1PPS_OUT The following is a setting that pin P14_00 is assigned GNSS_1PPS_OUT role IOCSYS_IOMD0 GNSS_1PPS_OUT 1 The following is a setting that pin P02_00 is assigned GNSS_1PPS_OUT role IOCSYS_IOMD1 HIFIRQ 3 3 1 4 3 10 CPU_WDT The following is a setting that pin P14_00 is assigned CPU_WDT role IOCSYS_IOMD0 GNSS_1PPS_OUT 2 3 1 ...

Page 76: ..._MISO ENZI 1 IOCSYS_IOMD0 SPI0A 2 IOCSYS_IOMD0 SPI0B 2 A function for pin P16_ 00 01 are selected by IOCSYS_IOMD0 SPI0A A function for pin P17_ 00 01 are selected by IOCSYS_IOMD0 SPI0B The following are settings that pin P18_ 00 01 02 03 are assigned SPI role IO_SPI1_IO1 ENZI 1 IOCSYS_IOMD0 SPI1A 2 Note SPI0 must not be assigned to both of the two pins 3 1 4 3 15 SPI1 The following are settings th...

Page 77: ...K ENZI 1 IO_SPI2_MOSI ENZI 1 IOCSYS_IOMD0 SPI2A 1 IOCSYS_IOMD0 SPI2B 1 3 1 4 3 17 UART0 If the pin SYSTEM0 is High and the pin SYSTEM1 is Low when POR is released pin P00_ 00 01 are assigned UART role automatically For this reason usually UART0 role cannot be set by registers The following is a setting that pin P01_ 00 01 are used as URAT0_CTS or UART0_RTS IOCSYS_IOMD0 SPI2B 2 The following are se...

Page 78: ... 1 IO_SPI2_SCK ENZI 1 IOCSYS_IOMD0 SPI2A 3 3 1 4 3 19 HIF_IRQ_OUT The following is a setting that pin P02_00 is assigned HIF_IRQ_OUT role IOCSYS_IOMD0 HIFIRQ 1 3 1 4 3 20 HIF_IRQ_OUT Open Drain The following is a setting that pin P02_00 is assigned HIF_IRQ_OUT role The pin becomes to operate as Open Drain and outputs in negative logic IOCSYS_IOMD0 HIFIRQ 2 3 1 4 3 21 GPS_EXTLD The following are se...

Page 79: ...S2_X 1 IOCSYS_IOMD1 SPI3 1 3 1 4 3 24 I2C0 The following are settings that pin P1j_ 00 01 is assigned I2C role IO_I2C0_BCK ENZI 1 IO_I2C0_BDT ENZI 1 IOCSYS_IOMD1 I2C0 1 3 1 4 3 25 I2C1 The following are settings that pin P1l_ 00 01 are assigned I2C role IO_PWM2 ENZI 1 IO_PWM3 ENZI 1 IOCSYS_IOMD1 PWMB 2 3 1 4 3 26 PWM The following are settings that pin P1k_ 00 01 and pin P1l_ 00 01 are assigned PW...

Page 80: ..._UART The following are settings that pin P1n_ 00 01 02 03 are assigned UART role IO_UART2_RXD ENZI 1 IO_UART2_CTS ENZI 1 IOCAPP_IOMD UART2 1 3 1 4 3 29 SPI4 APP_SPI The following are settings that pin P1o_ 00 01 02 03 are assigned SPI role IO_SPI4_MISO ENZI 1 IOCAPP_IOMD SPI4 1 3 1 4 3 30 EMMC The following are settings that pin P1p 00 01 02 03 and pin P1q_ 00 01 are assigned EMMC role IO_EMMC_CM...

Page 81: ...ed SDIO role IO_SIDO_CLK ENZI 1 IO_SIDO_CMD ENZI 1 IO_SIDO_DATA 0 3 ENZI 1 IO_SIDO_CD ENZI 1 IO_SIDO_WP ENZI 1 IO_SIDO_CLKI ENZI 1 IOCAPP_IOMD SDIOA 1 IOCAPP_IOMD SDIOB 1 IOCAPP_IOMD SDIOC 1 IOCAPP_IOMD SDIOD 1 Figure I O Configuration 13 shows connecting diagram of SDIO input clock SDIO IP uses either clock turned inside IOCELL or clock turned outside the LSI ...

Page 82: ... 3 0 1 2 3 0 GP_SDIO_CLK DIR IO_SDIO_CLKI ENZI 2 0 1 2 3 1 2 3 0 1 2 3 1 P1u_00 GP_SDIO_CLK OUT IOCAPP_IMOD SDIOD GP_SDIO_CLK IN GP_SDIO_CLKI DIR GP_SDIO_CLKI OUT 0 GP_SDIO_CLKI IN SDIO_CLK SPI5_SCK 0 SDIO_CLK SDIO_CLKI SPI5_SCK OPEN OPEN OPEN SDIO Figure I O Configuration 13 SDIO CLK Input Schematic ...

Page 83: ...APP SDIO_WP SDIO When IOCAPP_IOMD SDIOB 1 Connect from P1s_00 to SDIO_CD When IOCAPP_IOMD SDIOB 0 Connect from IOCFIX_APP SDIO_CD to SDIO_CD Figure I O Configuration 14 SDIO WP CD Input Control Register Schematic 3 1 4 3 32 I2S0 When you use a pin as I2S role you need to select I2S role by using IOCAPP_IOMD as well as decide in which mode I2S role should be played master or slave According to the ...

Page 84: ...pin P1w_ 00 01 02 03 are assigned the I2S master IO_I2S1_BCK ENZI 0 Input Disable IO_I2S1_LRCK ENZI 0 Input Disable IO_I2S1_DATA_IN ENZI 1 Input Enable IOCAPP_IOMD I2S1 1 IO_IOOEN_APP I2S1_BCK 0 Output Enable IO_IOOEN_APP I2S1_LRCK 0 Output Enable The following are settings that pin P1w_ 00 01 02 03 are assigned the I2S slave IO_IOOEN_APP I2S1_BCK 1 Output Disable IO_IOOEN_APP I2S1_LRCK 1 Output D...

Page 85: ...g are settings that pin P1z_00 is assigned USB_VBUSINT input role IO_USB_VBUSINT ENZI 1 Input Enable IOCAPP_IOMD USBVBUS 1 3 1 4 3 37 SPI5 The following are settings that pin P1p_ 00 01 02 03 are assigned SPI role IO_EMMC_DATA1 ENZI 1 Input Enable IOCAPP_IOMD EMMCA 2 The following are settings that pin P1r_ 00 01 02 03 are assigned SPI role In this setting pin P1r_ 04 05 can be used as GPIO role I...

Page 86: ...t Table General Purpose Input Output GPIO 19 Function List No Function Name Description 1 GPIO Control controls I O pins to switch between input and output 2 I O Pin Selection selects I O pins used for interrupts 3 External Interrupt Option selects an interrupt option for outputting to SYSCPU and DSP 4 Event Detection Control controls Event Detection that can be selected as an option described in ...

Page 87: ...unction I O Function Pull up down LOWEMI Pull up State Pull Dn State GPIO Control I O Configuration 2 IO Pin Pin Output Enable Pin Output Pull up Pull down Event Detect Wakeup factor to PMU Interrupt to CPU DSP Output Mode1 Alternate Function Output Alternate Function Input GPIO Status Pin Input Output Mode2 Output Mode3 Input Mode1 Input Mode2 Input Mode3 Pin Input Enable Input Enable Figure Gene...

Page 88: ... Level Pulse Pulse Pulse Pulse Pulse 2 3 4 0 PMU_WAKE_TRIG_CPUINTSELx PMU_WAKE_TRIG_ENx PMU_WAKE_TRIGx_RAW PMU_WAKE_TRIGx Wakeup factor to PMU 0 1 Pos edge Pulse Clr Set from I O CRG SCU RTC0 64 to 1 USB_VBUS PMIC_INT SEN_INT HVDD_DET HIF_UART_RXD HIF_SPI_CS_X HIF_SCL_LOW 20 Event Detect 4 4 GNSS SYSIOP_SUB HIF_DETECT_I2C _SLAVE INT_PMIC_I2CM PMU 14 20 EXDEVICE 11 0 USBVBUS USBVBUSN HVDD PMIC_INT ...

Page 89: ...W 16 1 OutputEnable control in GPIO mode 0 OutputEnable 1 OutputDisable Reserved RO 15 9 0 Reserved OUT RW 8 0 OutputData control in GPIO mode Reserved RO 7 1 0 Reserved IN RO 0 0 I O pin value 1 A register is prepared for each I O pin For correspondence of I O pins to registers refer to Table General Purpose Input Output GPIO 21 GP_ DIR Control of OutputEnable Set the register OutputEnable when y...

Page 90: ...1_SCK P18_01 GP_IS_DATA2 P1m_05 GP_SDIO_DIR0 P1t_01 GP_SPI1_IO0 P18_02 GP_IS_DATA3 P1m_06 GP_SDIO_DIR1_3 P1t_02 GP_SPI1_IO1 P18_03 GP_IS_DATA4 P1m_07 GP_SDIO_CLKI P1u_00 GP_SPI1_IO2 P19_00 GP_IS_DATA5 P1m_08 GP_I2S0_BCK P1v_00 GP_SPI1_IO3 P19_01 GP_IS_DATA6 P1m_09 GP_I2S0_LRCK P1v_01 GP_SPI2_CS_X P00_00 GP_IS_DATA7 P1m_10 GP_I2S0_DATA_IN P1v_02 GP_SPI2_SCK P00_01 GP_UART2_TXD P1n_00 GP_I2S0_DATA_O...

Page 91: ...er I O Function Pull up down LOWEMI Pull up State Pull Dn State GPIO Control I O Configuration 2 IO Pin Pin Output Enable Pin Output Pull up Pull down Event Detect Wakeup factor to PMU Interrupt to CPU DSP Output Mode1 Alternate Function Output Alternate Function Input GPIO Status Pin Input Output Mode2 Output Mode3 Input Mode1 Input Mode2 Input Mode3 Pin Input Enable Input Enable GP_ DIR 0 GP_ OU...

Page 92: ... shows a visualized function controlled by GPIO parameter that is set by GPIO input control register I O Function Pull up down LOWEMI Pull up State Pull Dn State GPIO Control I O Configuration 2 IO Pin Pin Output Enable Pin Output Pull up Pull down Event Detect Wakeup factor to PMU Interrupt to CPU DSP Output Mode1 Alternate Function Output Alternate Function Input GPIO Status Pin Input Output Mod...

Page 93: ...is section Internal signal detection External signal select External signal detection Instant High Instant Low Level High Level Low Pos edge Neg edge Chattering removal PMU_WAKE_TRIG_NOISECUTENx Pos Neg edge or 0 1 0 1 2 3 4 5 6 0 1 Clr Set PMU_WAKE_TRIG_INTDETx PMU_WAKE_TRIGx_CLR Level Level Pulse Pulse Pulse Pulse Pulse 2 3 4 0 PMU_WAKE_TRIG_CPUINTSELx PMU_WAKE_TRIG_ENx PMU_WAKE_TRIGx_RAW PMU_WA...

Page 94: ...ble General Purpose Input Output GPIO 22 IO Pin Selection SYS Group Address Register Name Bit Field Name Type Bit Initial Value Description 0x041007B0 IOCSYS_INTSEL0 Reserved RO 31 30 0 Reserved SEL3 RW 29 24 63 assigns an I O pin to an external signal SYSGPI3 Reserved RO 23 22 0 Reserved SEL2 RW 21 16 63 assigns an I O pin to an external signal SYSGPI2 Reserved RO 15 14 0 Reserved SEL1 RW 13 8 63...

Page 95: ...0 45 61 14 P02_00 30 P1k_01 46 62 15 P03_00 31 P1l_00 47 default 63 Table General Purpose Input Output GPIO 24 I O Pin Selection APP Group Address Register Name Bit Field Name Type Bit Initial Value Description 0x04101490 IOCAPP_INTSEL0 Reserved RO 31 30 0 Reserved SEL3 RW 29 24 63 assigns an I O pin to an external signal APPGPI3 Reserved RO 23 22 0 Reserved SEL2 RW 21 16 63 assigns an I O pin to ...

Page 96: ..._01 1 P1o_02 17 P1t_00 33 P1z_00 49 P1m_02 2 P1o_03 18 P1t_01 34 50 P1m_03 3 P1p_00 19 P1t_02 35 51 P1m_04 4 P1p_01 20 P1u_00 36 52 P1m_05 5 P1p_02 21 P1v_00 37 53 P1m_06 6 P1p_03 22 P1v_01 38 54 P1m_07 7 P1q_00 23 P1v_02 39 55 P1m_08 8 P1q_01 24 P1v_03 40 56 P1m_09 9 P1r_00 25 P1w_00 41 57 P1m_10 10 P1r_01 26 P1w_01 42 58 P1n_00 11 P1r_02 27 P1w_02 43 59 P1n_01 12 P1r_03 28 P1w_03 44 60 P1n_02 13...

Page 97: ...municated as an interrupt signal with no changes 3 When an event is detected the register is asserted and communicated as a latched interrupt signal 4 7 The output value is tied to 0 Internal signal detection External signal select External signal detection Instant High Instant Low Level High Level Low Pos edge Neg edge Chattering removal PMU_WAKE_TRIG_NOISECUTENx Pos Neg edge or 0 1 0 1 2 3 4 5 6...

Page 98: ...atus event detected is latched 4 7 The output value is tied to 0 Reserved RO 27 0 Reserved SYSGPI2 RW 26 24 0 Refer to SYSGPI3 Reserved RO 23 0 Reserved SYSGPI1 RW 22 20 0 Refer to SYSGPI3 Reserved RO 19 0 Reserved SYSGPI0 RW 18 16 0 Refer to SYSGPI3 Reserved RO 15 0 Reserved HVDD_DET RW 14 12 0 Refer to SYSGPI3 Reserved RO 11 0 Reserved HIF_UART_R XD RW 10 8 0 Refer to SYSGPI3 Reserved RO 7 0 Res...

Page 99: ...d RO 7 0 Reserved SYSGPI5 RW 6 4 0 Refer to SYSGPI3 Reserved RO 3 0 Reserved SYSGPI4 RW 2 0 0 Refer to SYSGPI3 0x04100470 PMU_WAKE_TRIG_ CPUINTSEL2 Reserved RO 31 15 0 Reserved USB_VBUS RW 14 12 0 Refer to SYSGPI3 Reserved RO 11 0 Reserved USB_VBUS_X RW 10 8 0 Refer to SYSGPI3 Reserved RO 7 0 Reserved PMIC_INT RW 6 4 0 Refer to SYSGPI3 Reserved RO 3 0 Reserved SEN_INT RW 2 0 0 Refer to SYSGPI3 ...

Page 100: ...al signal select External signal detection Instant High Instant Low Level High Level Low Pos edge Neg edge Chattering removal PMU_WAKE_TRIG_NOISECUTENx Pos Neg edge or 0 1 0 1 2 3 4 5 6 0 1 Clr Set PMU_WAKE_TRIG_INTDETx PMU_WAKE_TRIGx_CLR Level Level Pulse Pulse Pulse Pulse Pulse 2 3 4 0 PMU_WAKE_TRIG_CPUINTSELx PMU_WAKE_TRIG_ENx PMU_WAKE_TRIGx_RAW PMU_WAKE_TRIGx Wakeup factor to PMU 0 1 Pos edge ...

Page 101: ...upts of CXD5247 PMIC_INT P1e_00 SEN_INT detects interrupts SEN_IRQ_IN that are output from sensors Interrupts from external sensor devices connected to SCU are assumed refer to Table General Purpose Input Out put GPIO 2 5 APPGPI5 I O pin selected by IOCAPP_INTSEL1 SEL5 EXDEVICE 11 APPGPI4 I O pin selected by IOCAPP_INTSEL1 SEL4 EXDEVICE 10 APPGPI3 I O pin selected by IOCAPP_INTSEL0 SEL3 EXDEVICE 9...

Page 102: ...t one from them by using a register for each I O pin Selection of the way of detecting events PMU_WAKE_TRIG_INTDET 0 Instant High Detection 1 Instant Low Detection 2 Level High Detection 3 Level Low Detection 4 Rising Edge Detection 5 Falling Edge Detection 6 Both Edge Detection 7 Both Edge Detection This function removes information of event detection that is made when CXD5602 is reset and then t...

Page 103: ...igure General Purpose Input Output GPIO 22 Event Detection Timing Diagram Table General Purpose Input Output GPIO 28 shows registers for setting Event Detection of I O pins Table General Purpose Input Output GPIO 28 Event Detection Setting for I O Pins Address Register Name Bit Field Name Type Bit Initial Value Description 0x04100464 PMU_WAKE_TRIG_ NOISECUTEN0 USB_VBUS RW 31 0 Debounce 1 eliminate...

Page 104: ...oth Edges removes the response at the start up Reserved RO 27 0 Reserved SYSGPI2 RW 26 24 0 refer to SYSGPI3 Reserved RO 23 0 Reserved SYSGPI1 RW 22 20 0 refer to SYSGPI3 Reserved RO 19 0 Reserved SYSGPI0 RW 18 16 0 refer to SYSGPI3 Reserved RO 15 0 Reserved HVDD_DET RW 14 12 0 refer to SYSGPI3 Reserved RO 11 0 Reserved HIF_UART_RXD RW 10 8 0 refer to SYSGPI3 Reserved RO 7 0 Reserved HIF_SPI_CS_X ...

Page 105: ...rved RO 11 0 Reserved APPGPI0 RW 10 8 0 refer to SYSGPI3 Reserved RO 7 0 Reserved SYSGPI5 RW 6 4 0 refer to SYSGPI3 Reserved RO 3 0 Reserved SYSGPI4 RW 2 0 0 refer to SYSGPI3 0x0410047C PMU_WAKE_TRIG_ INTDET2 Reserved RO 31 15 0 Reserved USB_VBUS RW 14 12 0 refer to SYSGPI3 Reserved RO 11 0 Reserved USB_VBUS_X RW 10 8 0 refer to SYSGPI3 Reserved RO 7 0 Reserved PMIC_INT RW 6 4 0 refer to SYSGPI3 R...

Page 106: ... 0x04103440 PMU_WAKE_TRIG0 USB_VBUS RO 31 0 Status of Event Detection 1 event is detected 0 event is not detected USB_VBUS_X RO 30 0 PMIC_INT RO 29 0 SEN_INT RO 28 0 APPGPI5 RO 27 0 APPGPI4 RO 26 0 APPGPI3 RO 25 0 APPGPI2 RO 24 0 APPGPI1 RO 23 0 APPGPI0 RO 22 0 SYSGPI5 RO 21 0 SYSGPI4 RO 20 0 SYSGPI3 RO 19 0 SYSGPI2 RO 18 0 SYSGPI1 RO 17 0 SYSGPI0 RO 16 0 HVDD_DET RO 15 0 HIF_UART_RXD RO 14 0 HIF_...

Page 107: ...put Output GPIO 30 shows registers to clear the status of the Event Detections Table General Purpose Input Output GPIO 30 Registers to Clear the Status of the Event Detections Address Register Name Bit Field Name Type Bit Initial Value Description 0x04103430 PMU_WAKE_TRIG0_CLR USB_VBUS RW 31 0 Held statuses of Event Detection can be cleared by writing 1 USB_VBUS_X RW 30 0 PMIC_INT RW 29 0 SEN_INT ...

Page 108: ...External signal select External signal detection Instant High Instant Low Level High Level Low Pos edge Neg edge Chattering removal PMU_WAKE_TRIG_NOISECUTENx Pos Neg edge or 0 1 0 1 2 3 4 5 6 0 1 Clr Set PMU_WAKE_TRIG_INTDETx PMU_WAKE_TRIGx_CLR Level Level Pulse Pulse Pulse Pulse Pulse 2 3 4 0 PMU_WAKE_TRIG_CPUINTSELx PMU_WAKE_TRIG_ENx PMU_WAKE_TRIGx_RAW PMU_WAKE_TRIGx from I O 64 to 1 USB_VBUS PM...

Page 109: ...nterrupt again INT_EN0 EXDEVICE 0 1 Restriction on Clearing Events Clearing process to clear a held event is performed when 1 is set on any bit of PMU_WAKE_TRIG0_CLR You cannot start a new clearing while the former one is still in process That is if you set 1 on other bit of PMU_WAKE_TRIG0_CLR while the former clearing is still in process you must wait for the new clearing until the former one end...

Page 110: ...f RTC Clock 0 1 Instant Detection Don t care constantly without elimination 2 3 7 8 10 11 4 7 Edge Detection 0 No 2 3 7 8 10 11 1 Yes 4 5 7 8 12 13 1 The time intervals in the table are those which are assumed when the following conditions are met After an interrupt is detected SYSCPU or DSP instantly masks the interrupt and clears the event The clock frequency of one of SYSCPU or DSP that perform...

Page 111: ...1 intterupt detect Event Detectable Event Undetectable from event detect to event detect clear done PMU_WAKE_TRIG0_RAW PMU_WAKE_TRIG0_CLR INT_IRQ0 INT_EN0 5 mask disable A 2 3 Cycle B 7 8 Cycle Event Detectable Event detect Figure General Purpose Input Output GPIO 24 Time Interval for a Signal to be able to Detect an Event Again PMU_WAKE_TRIG_NOISECUTEN0 0 ...

Page 112: ...put Register Interrupt input Register Interrupt input Register Interrupt input Register Interrupt input Register Cortex M0 PID0 System and I O Processor 32 GNSS DSP 128 Application Processor WDT IRQ NMI Cortex M4 PID1 IRQ NMI DEBUG TIMER Cause1 21 Cause1 20 Cause1 22 Cause1 19 17 WDTRES WDTINT Cause1 23 Cause3 9 8 WDT WDTRES WDTINT Cause1 24 TIMER Cause1 19 17 DEBUG Cause3 9 8 Cause1 21 Cause1 20 ...

Page 113: ...e register depends on that of connected block 0xE0045004 INT_CAUSE1 RO 0xE0045008 INT_CAUSE2 RO 0xE004500C INT_CAUSE3 RO 0xE0045010 INT_EN0 RW 0x00000000 Interrupt enable When bit value is 1 interrupt is requested to processor enabled and when bit value is 0 interrupt is not requested disabled 0xE0045014 INT_EN1 RW 0x00000000 0xE0045018 INT_EN2 RW 0x00000000 0xE004501C INT_EN3 RW 0x00000000 0xE004...

Page 114: ...rupt request from PMU 0xE0045004 INT_CAUSE1 SDMAC RO 31 0 Interrupt request from SDMAC 0xE0045008 INT_CAUSE2 SPH RO 31 16 Interrupt request from semaphore regarding communication between CPUs FIFOFROM RO 15 Interrupt request from receive FIFO regarding communication between CPUs FIFOTO RO 14 Interrupt request from transmit FIFO regarding communication between CPUs DEBUG RO 13 12 Interrupt request ...

Page 115: ... from SPI4 IMGVSYNC RO 16 Interrupt request from Imaging vsync IMGUART RO 15 Interrupt request from UART2 IMGDMAC RO 14 Interrupt request from IDMAC IMGWSSP RO 13 Interrupt request from SPI5 IMGCIS RO 12 Interrupt request from CIS I F IMGROT RO 11 Interrupt request from Imaging rotation IMG2D RO 10 Interrupt request from 2D Graphics AUDCODEC RO 9 Interrupt request from AudioDSP AUDI2S1 RO 8 Interr...

Page 116: ...nagement Unit 26 The lower layer power domains cannot be turned ON when the upper layer power supplies are OFF Furthermore PWD_GNSS can be turned ON only when both PWD_GNSS_ITP and PWD_SYSIOP are ON VDD_CORE PWD_PMU PWD_SCU PWD_CORE PWD_GNSS_ITP PWD_SYSIOP PWD_SYSIOP_SUB PWD_GNSS PWD_APP PWD_APP_DSP PWD_APP_SUB PWD_APP_AUD PMU PWD_SCU Power switch PWD_CORE Power switch PWD_SYSIOP_SUB Power switch ...

Page 117: ...CXD5602 User Manual 117 1010 3 4 1 1 Individual Power Supply Control within the Power Domains The SRAM or analog circuits such as the ADC within the power domains enable individual power supply control ...

Page 118: ...Tile 0 128 KB SRAM Application Processor Tile 1 128 KB SRAM Application Processor Tile 2 128 KB SRAM Application Processor Tile 3 128 KB SRAM Application Processor Tile 4 128 KB SRAM Application Processor Tile 5 128 KB SRAM Application Processor Tile 6 128 KB SRAM Application Processor Tile 7 128 KB SRAM Application Processor Tile 8 128 KB SRAM Application Processor Tile 9 128 KB SRAM Application ...

Page 119: ...or Application Processor Tile 0 128KB Tile 1 128KB SRAM Peripheral Array for Application Processor Tile 11 128KB SRAM Peripheral Power switch SRAM Array Power switch SRAM Peripheral Power switch SRAM Array Power switch SRAM Peripheral Power switch Application Processor Tile 0 Application Processor Tile 1 Application Processor Tile 11 Application Processor SRAM total 1 5MB PWD_SYSIOP Figure PMU Pow...

Page 120: ...OFF and the CXD5247 is ON In this state the RTC of the CXD5247 is counting and time information can be obtained from the CXD5247 after the LSI is started 3 Reset In this state the LSI and CXD5247 are both ON and the LSI is being reset 4 Normal The LSI and CXD5247 are both ON and the System Control PWD_SYSIOP turns ON enabling power supply control of each Domain The state begins from Power OFF and ...

Page 121: ...in ON CXD5602 ON System and IOP Domain ON Application Domain ON GNSS Domain OFF Sensor Domain ON CXD5602 ON System and IOP Domain ON Application Domain OFF GNSS Domain ON Sensor Domain ON CXD5602 ON System and IOP Domain ON Application Domain ON GNSS Domain ON Sensor Domain ON State Normal Domain ON Transition to each state is possible Figure PMU Power Management Unit 29 Changes of Power Supply St...

Page 122: ...28 KByte OFF ON PWD_SYSIOP_SUB OFF ON PWD_SYSIOP OFF ON SRAM HOSTIFC 1KByte OFF ON SRAM HOSTIFC Sequencer RAM OFF ON Application Domain PWD_APP OFF OFF SRAM Application Processor Tile 0 128 KByte OFF OFF SRAM Application Processor Tile 1 128 KByte OFF OFF SRAM Application Processor Tile 2 128 KByte OFF OFF SRAM Application Processor Tile 3 128 KByte OFF OFF SRAM Application Processor Tile 4 128 KB...

Page 123: ...PWD_CTL _RAMMODE_SEL ANA_PW_CTL Power supply control is executed only when the register settings are correct and not performed when they are incorrect For example when a power supply of the upper layer PWD_APP is OFF and a power supply of the lower layer PWD_APP_DSP receives a setting request to turn it ON this is judged as an incorrect setting and power supply control is not performed Power Contr...

Page 124: ... OFF Turn ON from upper power supply PWD_SYSIOP first Turn OFF from lower power supply PWD_APP_DSP first INT supply power to PWD_CORE PWD_CORE PWD_APP_DSP PSW_CHECK Check result details Power supply setting Power control request Figure PMU Power Management Unit 30 Overall Block Diagram of the PMU 3 4 1 4 Clock and Reset Clock Figure PMU Power Management Unit 31 shows a system diagram of the PMU s ...

Page 125: ...K_SEL2 PMU Clock AHB IF Check Register Value Power Control Sequencer ck_ahb_gear Supply Power to RCOSC Initial Value ON Initial Value 0 Figure PMU Power Management Unit 31 PMU Clock System Reset The PMU is reset by full reset of the CXD5602 external reset RST_X or RCOSC POR or WDT reset by automatic release Reset cannot be applied to the PMU alone ...

Page 126: ...x0410002C Reserved RW Reserved 0x04100030 PMU_PW_CTL WO Power supply control request 0x00000000 0x04100040 PMU_INT_STAT RO Interrupt status 0x00000000 0x04100044 PMU_RAW_INT_STAT RO Pre masked interrupt status 0x00000000 0x04100048 PMU_INT_CLR WO Interrupt clear 0x00000000 0x0410004C PMU_INT_MASK RW Interrupt mask 0x00000F10 0x04100070 0x04100104 Reserved RW Reserved 0x04100200 PWD_STAT RO Power s...

Page 127: ...SS 0x00000000 0x04103C30 GNSS_RAMMODE_STAT RO Power supply status SRAM for GNSS 0x00000000 0x04104400 APPDSP_RAMMODE_SEL0 RW Power supply setting SRAM0 for Application Processor 0x00000000 0x04104404 APPDSP_RAMMODE_SEL1 RW Power supply setting SRAM1 for Application Processor 0x00000000 0x04104420 APPDSP_RAMMODE_STAT0 RO Power supply status SRAM0 for Application Processor 0x00000000 0x04104424 APPD...

Page 128: ...and Table PMU Power Management Unit 38 show the registers related to power supply control of the power domains For the control method refer to the control flow described in Section 3 4 4 1 Table PMU Power Management Unit 37 Power Supply Control Settings Power Domain Address Register Name Bit Field Name Type Bit Initial Value Description 0x04100000 PWD_CTL WEN RO 31 0 Reserved WO 30 0 Write Enable ...

Page 129: ... has been written to their corresponding Write Enables Table PMU Power Management Unit 38 Power Supply Status Power Domain Address Register Name Bit Field Name Type Bit Initial Value Description 0x04100200 PWD_STAT Reserved RO 31 15 0 Reserved PWD_APP_AUD RO 14 0 Power supply status 1 ON 0 OFF PWD_GNSS RO 13 0 PWD_GNSS_ITP RO 12 0 Reserved RO 11 0 Reserved PWD_APP_SUB RO 10 0 Power supply status 1...

Page 130: ...ite Enable RAM0_8KB_1 24 0 Write Enable RAM0_8KB_0 Reserved RO 23 14 0 Reserved RAM3_64KB RW 13 12 2 b11 Power supply control settings 2 b11 On mode 2 b01 Retention mode 2 b00 ShutDown mode 2 b10 Prohibited setting RAM2_64KB RW 11 10 2 b11 RAM1_64KB RW 9 8 2 b11 RAM0_32KB RW 7 6 2 b11 RAM0_16KB RW 5 4 2 b11 RAM0_8KB_1 RW 3 2 2 b11 RAM0_8KB_0 RW 1 0 2 b11 0x04100018 TOP_SCU_RAM MODE_SEL Reserved RO...

Page 131: ...ODE_SEL WEN WO 31 0 Write Enable RAM89_128KB 30 0 Write Enable RAM67_128KB 29 0 Write Enable RAM45_128KB 28 0 Write Enable RAM3_64KB 27 0 Write Enable RAM2_64KB 26 0 Write Enable RAM1_64KB 25 0 Write Enable RAM0_48KB 24 0 Write Enable RAM0_16KB Reserved RO 23 16 0 Reserved RAM89_128KB RW 15 14 2 b11 Power supply control settings 2 b11 On mode 2 b01 Retention mode 2 b00 ShutDown mode 2 b10 Prohibit...

Page 132: ...pply control settings 2 b11 On mode 2 b01 Retention mode 2 b00 ShutDown mode 2 b10 Prohibited setting RAMA RW 9 8 2 b00 RAM9 RW 7 6 2 b00 RAM8 RW 5 4 2 b00 RAM7 RW 3 2 2 b00 RAM6 RW 1 0 2 b00 Table PMU Power Management Unit 40 Power Supply Status SRAM Address Register Name Bit Field Name Type Bit Initial Value Description 0x0410020C SYSCPU_RAMM ODE_STAT Reserved RO 31 14 0 Reserved RAM3_64KB RO 13...

Page 133: ... 14 2 b11 Power supply status 2 b11 On mode 2 b01 Retention mode 2 b00 ShutDown mode 2 b10 Prohibited setting RAM67_128KB RO 13 12 2 b11 RAM45_128KB RO 11 10 2 b11 RAM3_64KB RO 9 8 2 b11 RAM2_64KB RO 7 6 2 b11 RAM1_64KB RO 5 4 2 b11 RAM0_48KB RO 3 2 2 b11 RAM0_16KB RO 1 0 2 b11 0x04104420 APPDSP_RAMM ODE_STAT0 Reserved RO 31 12 0 Reserved RAM5 RO 11 10 2 b00 Power supply status 2 b11 On mode 2 b01...

Page 134: ..._PW_CTL WEN RO 31 30 0 Reserved WO 29 0 Write Enable LPADC WO 28 0 Write Enable HPADC RO 27 26 0 Reserved WO 25 0 Write Enable RF_PLL WO 24 0 Write Enable RF_LO WO 23 0 Write Enable RF_ADC WO 22 0 Write Enable RF_IF WO 21 0 Write Enable RF_MIX WO 20 0 Write Enable RF_LNA RO 19 0 Reserved WO 18 0 Write Enable SYSPLL WO 17 0 Write Enable XOSC WO 16 0 Write Enable RCOSC Reserved RO 15 14 0 Reserved L...

Page 135: ...the initial value IXO_LV_I_VAL3 RW 23 16 0 Oscillator current adjustment IXO_LV_I_VAL1 RW 15 8 0 Oscillator current adjustment Reserved RW 7 0 0 Reserved Do not change the initial value Table PMU Power Management Unit 42 Power Supply Status Analog Circuit Address Register Name Bit Field Name Type Bit Initial Value Description 0x04100208 ANA_PW_STAT Reserved RO 31 14 0 Reserved LPADC RO 13 0 Power ...

Page 136: ...MU has two types of interrupts each of which allows the control of status read clear and mask The two interrupts PMU_INT_STAT 1 0 are ORed and sent to the CPU DSP as INT_CAUSE0 PMU For details refer to Section 3 3 2 The following describes the details of the two interrupts Table PMU Power Management Unit 44 shows a register list of the interrupts Interrupt DONE Completion of power supply control W...

Page 137: ..._CTRL and DONE NOGO_CTRL RW 1 0 Interrupt mask Processor notification setting of the interrupt factor 0 Notify 1 Do not notify DONE RW 0 0 3 4 3 7 Power Supply Setting Check During a power supply control request the PMU checks whether or not there is an incorrect setting in the power supply setting When there is an incorrect setting the corresponding bit within the PSW_CHECK becomes 1 and power su...

Page 138: ... least one of the SRAMs for GNSS DSP When turning OFF all SRAMs for GNSS DSP make sure to turn OFF PWD_GNSS too To turn ON the PWD_GNSS and SRAM for GNSSDP PWD_CTL 0x20002000 GNSSDSP_RAMMODE_SEL 0xFF00FFFF SRAM for GNSS DSP power supply setting To turn OFF the PWD_GNSS and SRAM for GNSSDP PWD_CTL 0x20000000 GNSSDSP_RAMMODE_SEL 0xFF000000 18 Power supply setting check RF and XOSC of the GNSS Domain...

Page 139: ... ANA_PW_CTL 0x30003000 HPADC and LPADC power supply setting TOP_SCU_RAMMODE_SEL 0x0000133F SRAM for SCU power supply setting To turn OFF the PWD_SCU SRAM for SCU HPADC and LPADC PWD_CTL 0x00010001 ANA_PW_CTL 0x30000000 TOP_SCU_RAMMODE_SEL 0x00001300 9 CPU Power supply setting check of the Application Domain When turning ON power supply layers lower than the PWD_APP also turn ON the PWD_APP When tu...

Page 140: ...on 3 4 4 1 6 1 Power supply control On Off Retention settings PWD_CTL 0x40004000 Example PWD_APP_AUD ON Refer to Table PMU Power Management Unit 47 and make the register settings of the desired power supply For the setting restrictions refer to the power supply control restrictions For an actual example of power supply control refer to Section 3 4 5 1 Table PMU Power Management Unit 47 Power Suppl...

Page 141: ...SCPU_RAMMODE_SEL 0x08000000 0x080000C0 0x08000040 SRAM SYSIOP Tile 1 64 KByte SYSCPU_RAMMODE_SEL 0x10000000 0x10000300 0x10000100 SRAM SYSIOP Tile 2 64 KByte SYSCPU_RAMMODE_SEL 0x20000000 0x20000C00 0x20000400 SRAM SYSIOP Tile 3 64 KByte SYSCPU_RAMMODE_SEL 0x40000000 0x40003000 0x40001000 SRAM GNSS DSP Tile 0 16 KByte GNSSDSP_RAMMODE_SEL 0x01000000 0x01000003 0x01000001 SRAM GNSS DSP Tile 0 48 KBy...

Page 142: ...Application Processor Tile 3 128 KByte APPDSP_RAMMODE_SEL0 0x08000000 0x080000C0 0x08000040 SRAM Application Processor Tile 4 128 KByte APPDSP_RAMMODE_SEL0 0x10000000 0x10000300 0x10000100 SRAM Application Processor Tile 5 128 KByte APPDSP_RAMMODE_SEL0 0x20000000 0x20000C00 0x20000400 SRAM Application Processor Tile 6 128 KByte APPDSP_RAMMODE_SEL1 0x01000000 0x01000003 0x01000001 SRAM Application ...

Page 143: ...PMU_INT_CLR CLR 1 0 2 b11 3 Interrupt mask cancel PMU_INT_MASK MSK 1 0 2 b00 4 Power supply control execution PMU_PW_CTL POWER_CTRL_ON 1 5 Interrupt confirmation Confirm PMU_INT_STAT STAT 1 0 2 b01 In the case of PMU_INT_STAT STAT 1 1 refer to Section 3 4 3 7 6 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 7 Clock and reset control Perform proper clock and reset control according to each power domain ...

Page 144: ...CXD5602 User Manual 144 1010 GNSS_RAMMODE_SEL 0x3F000FFF SRAM GNSS BB 0 5 ON ...

Page 145: ... the clock RCOSC_CTRL1 IRO_LV_SENSCLK_XEN 0 for HPADC RCOSC_CTRL1 IRO_LV_LOGICLK_XEN 0 for each function block When stopping the clock RCOSC_CTRL1 IRO_LV_SENSCLK_XEN 1 for HPADC RCOSC_CTRL1 IRO_LV_LOGICLK_XEN 1 for each function block ON OFF Control Flow The following describes the flow to turn OFF the power supply of the RCOSC As a precondition when there is a block using the RCOSC such as the PM...

Page 146: ...ies 26 MHz External clock mode system configuration that uses TCXO Supported frequencies 26 MHz Table PMU Power Management Unit 48 Parameter Setting for Each Mode Register Name Internal Oscillation Mode External Clock Mode ANA_EN_CTL ON_XO_OSC_EN_SET 0 1 ANA_EN_CTL OFF_XO_OSC_EN_CLR 0 1 ANA_EN_CTL ON_XO_OSCOUT_EN_SET 0 1 ANA_EN_CTL OFF_XO_OSCOUT_EN_CLR 0 1 ANA_EN_CTL ON_XO_EXT_EN_SET 1 0 ANA_EN_CT...

Page 147: ...0 20 52 5 2 0 90 70 4 XOSC power supply ON control ANA_PW_CTL 32 h00020002 5 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 6 Interrupt mask cancel PMU_INT_MASK MSK 1 0 2 b00 7 Power supply control execution PMU_PW_CTL POWER_CTRL_ON 1 8 Interrupt confirmation Confirm PMU_INT_STAT STAT 1 0 2 b01 9 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 10 Clock control Control the supply stop of the clock in accordan...

Page 148: ...make sure that the power supply of the SYSPLL is turned OFF during this operation 1 XOSC power supply OFF setting ANA_PW_CTL 32 h00020000 2 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 3 Interrupt mask cancel PMU_INT_MASK MSK 1 0 2 b00 4 XOSC power supply OFF control PMU_PW_CTL POWER_CTRL_ON 1 5 Interrupt confirmation Confirm PMU_INT_STAT STAT 1 0 2 b01 6 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 ...

Page 149: ... ISP_LV_SELFBDIV The frequency of the SYSPLL is determined by the frequency of the XOSC and register value The following describes the division ratio settings of the SYSPLL Table PMU Power Management Unit 50 SYSPLL Division Ratio Setting XOSC Frequency MHz SYS_PLL_CTRL2 ISP_L V_SELRCDIV 1 0 SYS_PLL_CTRL2 ISP_L V_SELFBDIV 2 0 SYSPLL Frequency MHz 16 368 0 0 163 68 0 1 196 42 19 2 1 2 144 00 0 0 192...

Page 150: ... describes the flow to turn OFF the power supply of the SYSPLL 1 SYSPLL power supply OFF setting ANA_PW_CTL 32 h00040000 2 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 3 Interrupt mask cancel PMU_INT_MASK MSK 1 0 2 b00 4 SYSPLL power supply OFF control PMU_PW_CTL POWER_CTRL_ON 1 5 Interrupt confirmation Confirm PMU_INT_STAT STAT 1 0 2 b01 6 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 3 4 4 1 4 HPADC OF...

Page 151: ...ails refer to Section xxx ON OFF Control Flow The following describes the flow to turn OFF the power supply of the HPADC 1 HPADC power supply OFF setting ANA_PW_CTL 32 h10000000 2 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 3 Interrupt mask cancel PMU_INT_MASK MSK 1 0 2 b00 4 HPADC power supply OFF control PMU_PW_CTL POWER_CTRL_ON 1 5 Interrupt confirmation Confirm PMU_INT_STAT STAT 1 0 2 b01 6 Inte...

Page 152: ...NT_STAT STAT 1 0 2 b01 6 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 7 LPADC reset release SWRESET_SCU XRST_SCU_LPADC 1 8 Clock control For details refer to Section xxx ON OFF Control Flow The following describes the flow for turning OFF the power supply of the LPADC 1 LPADC power supply OFF setting ANA_PW_CTL 32 h20000000 2 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 3 Interrupt mask cancel PMU_INT_M...

Page 153: ... PMU_PW_CTL POWER_CTRL_ON 1 5 Interrupt confirmation Confirm PMU_INT_STAT STAT 1 0 2 b01 6 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 7 Clock control For details refer to Section 3 12 ON OFF Control Flow The following describes the flow to turn OFF the power supply of the RF LNA MIX IF ADC LO PLL 1 RF power supply OFF setting ANA_PW_CTL 32 h03F00000 2 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 3 Int...

Page 154: ...FF ON PWD_SCU ON OFF SRAM Application Processor Tile 4 OFF ON Power supply control flow 1 Power supply control setting PWD_CTL 0x41014100 OR the following power supply control settings PWD_CTL 0x01000100 PWD_APP ON PWD_CTL 0x40004000 PWD_APP_AUD ON PWD_CTL 0x00010000 PWD_SCU ON APPDSP_RAMMODE_SEL0 0x3F000FFF Note Due to the power supply control restrictions turn ON all SRAMs of the PWD_APP layer O...

Page 155: ...r Tile 4 APPDSP_RAMMODE_SEL0 0x2F00CFF SRAM Application Processor Tile 0 3 5 OFF APPDSP_RAMMODE_SEL1 0x3F000000 SRAM Application Processor Tile 6 11 OFF 9 Interrupt clear PMU_INT_CLR CLR 1 0 2 b11 10 Interrupt mask setting PMU_INT_MASK MSK 1 0 2 b00 11 Power supply control execution PMU_PW_CTL POWER_CTRL_ON 1 12 Interrupt confirmation Confirm PMU_INT_STAT STAT 1 0 2 b01 13 Interrupt clear PMU_INT_...

Page 156: ...masked and the Application Processor enters WFI state 1 Mask all interrupts made to the Application Processor INT_EN 0 For details on the interrupt mask INT_EN refer to Section 3 3 2 2 Request Sleep PWD_APP_DSP OFF control to the System and I O Processor 3 Issue WFI command Control of System and I O Processor side reference The OFF request of the PWD_APP_DSP is received from the Application Proces...

Page 157: ...ON WFI reg Polling Application Processor Enable Off request Sleep setting Interrupt clear Sleep sequence Wakeup sequence WFI start Disable for Application processor Power on sequence Power off sequence Power control by proxy Off request On request Sleep setting wakeup setting WFI wakeup setting Interrupt Mask power off power on interrupt handling Detect power control by proxy PWD_APP_DSP ON System...

Page 158: ...e WDT Since clock control and reset control are performed using the API this Section describes the information for confirming the statuses of the clock and reset 3 5 2 Clock Scheme for CRG Figure Clock and Reset Clock Reset Generator 33 shows the overall clock scheme for the CRG while Figure Clock and Reset Clock Reset Generator 34 shows the details In Figure Clock and Reset Clock Reset Generator ...

Page 159: ...n Overall Clock Scheme Always On System and IOP Fabric Refer to SYSIOP BackUp SRAM 0 3 2 1 RCOSC XOSC ck_cpu_bus ck_rf_pll_1 0 3 2 1 0 1 1 2 1 3 1 4 1 5 XOSC macro SYSPLL macro RCOSC macro 0 3 2 1 ck_rtc_pre 1 250 Reserved Reserved 0 1 ck_sel_ro_rtc SEL 2 SEL 4 SEL 3 SEL 1 SEL 6 PMU I2C4 CK GATE 1 M CKDIV_CPU_DSP_BUS CK_M0 ck_cpu_bus_gear_1 CG 3 ck_ahb_gear 1 M CK GATE CK GATE 1 M ck_apb_gear Cryp...

Page 160: ...C block Table Clock and Reset Clock Reset Generator 51 RCOSC Block Status Registers Address Register Name Bit Field Name Type Bit Initial Value Description 0x04100590 RCOSC_ CTRL1 Reserved RW 31 15 0 Reserved IRO_LV_SENSCLK_ XEN RW 14 1 Indicated as ANA 1 in Figure Clock and Reset Clock Reset Generator 34 Clock Enable for HPADC 0 Enable 1 Disable IRO_LV_LOGICLK_ XEN RW 13 0 Indicated as ANA 0 in F...

Page 161: ...eserved RW 31 20 0 Reserved IXO_LV_LOCLK_E N RW 19 0 Indicated as ANA 5 in Figure Clock and Reset Clock Reset Generator 34 Clock Enable for GNSS 0 Clock supplied 1 Clock stopped IXO_LV_PLLCLK_E N RW 18 0 Indicated as ANA 4 in Figure Clock and Reset Clock Reset Generator 34 Clock Enable for SYSPLL block 0 Clock supplied 1 Clock stopped IXO_LV_SENCLK_ EN RW 17 0 Indicated as ANA 3 in Figure Clock an...

Page 162: ...r Descriptions Table Clock and Reset Clock Reset Generator 54 shows the control registers related to the SYSPLL block Table Clock and Reset Clock Reset Generator 54 SYSPLL Block Status Registers Address Register Name Bit Field Name Type Bit Initial Value Description 0x04100588 SYS_PLL _CTRL1 Reserved RW 31 4 0 Reserved ISP_LV_ENDSPCLK RW 3 0 Indicated as ANA 7 in Figure Clock and Reset Clock Reset...

Page 163: ... Table Clock and Reset Clock Reset Generator 55 Clock Switching Status Registers Address Register Name Bit Field Name Type Bit Initial Value Description 0x041004C4 CKSEL_ ROOT PMU_STAT_CLK_S EL4 RO 31 30 0 Indicated as SEL 5 in Figure Clock and Reset Clock Reset Generator 34 PMU s clock source switching status 2 b00 RCRTC frequency of dividing the RCOSC by 250 2 b01 Reserved 2 b10 RTC Clock 2 b11 ...

Page 164: ... 2 b01 divided by 2 Duty H L 1 1 2 b10 divided by 3 Duty H L 2 1 2 b11 divided by 4 Duty H L 1 1 or divided by 5 Duty H L 3 2 Reserved RW 9 3 0 Reserved CPU_PLL_DIV5 RW 2 0 Indicated as SEL 1 in Figure Clock and Reset Clock Reset Generator 34 Either SYSPLL4 or 5 frequency division switching status 0 divided by 4 1 divided by 5 Reserved RW 1 0 0 Reserved 0x041004C8 CKSEL_P MU Reserved RO 31 2 0 Res...

Page 165: ...PMU_CO RE_CKE N Reserved RO 31 4 0 Reserved BKMEM RW 3 1 Indicated as CG 3 in Figure Clock and Reset Clock Reset Generator 34 Clock Enable for BackUpSRAM 1 Clock supplied 0 Clock stopped HCLK_KAKI RW 2 0 Indicated as CG 2 in Figure Clock and Reset Clock Reset Generator 34 Clock Enable for Crypto Clefia RTC_PCLK RW 1 1 Indicated as CG 1 in Figure Clock and Reset Clock Reset Generator 34 Clock Enabl...

Page 166: ...ock and Reset Clock Reset Generator 57 shows the relation between each power domain and the reset control registers Table Clock and Reset Clock Reset Generator 57 Power Domain and the Reset Control Registers Power Domain Register PWD_PMU None Reset is automatically released at start up PWD_CORE PWD_SYSIOP PWD_SYSIOP_SUB PWD_RESET0 PWD_SYSIOP_SUB PWD_SCU PWD_RESET0 PWD_SCU PWD_APP PWD_RESET0 PWD_AP...

Page 167: ...te Enable PWD_APP 23 0 Reserved 22 0 Write Enable PWD_SYSIOP_SUB 21 17 0 Reserved 16 0 Write Enable PWD_SCU Reserved RO 15 14 0 Reserved PWD_GNSS RW 13 0 Reset of PWD_GNSS power domain 0 Reset is performed 1 Reset release PWD_GNSS_ITP RW 12 0 Reset of PWD_GNSS_ITP power domain Reserved RO 11 9 0 Reserved PWD_APP RW 8 0 Reset of PWD_APP power domain Reserved RO 7 0 Reserved PWD_SYSIOP_SUB RW 6 1 Re...

Page 168: ...Reset Clock Reset Generator 59 shows the control registers of reset by WDT Table Clock and Reset Clock Reset Generator 59 WDT Reset Control Registers Address Register Name Bit Field Name Type Bit Initial Value Description 0x04100640 WDT_SR ST_EN Reserved RO 31 1 0 Reserved EN RW 0 0 System reset by WDT valid invalid 0 Invalid 1 Valid 0x04100484 BOOT_C AUSE Reserved RO 31 1 0 Reserved CLR_WDT_REBOO...

Page 169: ...CXD5602 User Manual 169 1010 RAW_INITIAL_BO OT RO 0 1 Boot flag 1 Boot by POR or WDT When booted by POR RAW_WDT_REBOOT 0 RAW_INITIAL BOOT 1 When booted from WDT RAW_WDT_REBOOT 1 RAW_INITIAL BOOT 1 ...

Page 170: ...SYSIOP RTC0 is supplied with VDD_CORE of CXD5602 and after the reset release it continues counting time On the other hand RTC1 counts time only when PWD_SYSIOP is powered on When the PWD_SYSIOP power supply is turned off the Time Counter returns to 0 As for power on off setting of RTC0 and RTC1 refer to Chapter 3 4 PWD_CORE PWD_SYSIOP RTC1 RTC0 VDD_CORE Figure RTC 35 RTC0 1 Power Supply Framework ...

Page 171: ...KSEL_ROOT PMU_STAT_CLK_SEL4 1 Explanation 0 Clock resource is RCOSC The RCOSC is calibrated to 8 192 MHz for use Frequency is about 32 kHz initial value after the reset release of CXD5602 1 Clock resource is real time clock provided from RTC_CLK_IN terminal Frequency is 32 768 kHz RTC Clock which is connected to RTC1 and APB IF RTC0 1 register control block can be provided or stopped providing by ...

Page 172: ...ption 1 RTC Counter Update Synchronization updates internal RTC counter in variety of conditions 2 Alarm Output outputs Alarm Flag at the prescribed time 3 6 4 Function Block Diagrams Figure RTC 37 is a block diagram that shows functional specification of this block There are one Time Counter and three Alarm Timers Registers are set via APB IF block APB IF block is operated by PWD_SYSIOP power sup...

Page 173: ...Control Register 0 3 2 1 0 1 0 1 RTCx_Alarm2 RTCx_Alarm1 RTCx_Alarm0 RTCx_Misc to NVIC PMU RTCx_ExtAlm Figure RTC 37 RTC Block Diagram As for Time Counter there are two ways of updating and synchronizing time separately By using Interrupt you can check whether the Time Counter has been completely updated or not How to set Time Counter 1 You can set the designated Time Counter value 2 You can adjus...

Page 174: ...ntCtrl Edge Detect Edge Update Flag CntUpdateEn Time Counter update done 1 Register 2 Offset 3 RTC Sync Update Type WrIntCtrl 4 External Sync 1 4 2 3 Figure RTC 38 RTC Time Update Block Diagram 3 6 4 1 Address Map RTC0 and RTC1 have each Base Address and register for synchronization setting Addresses are as follows RTC0 0x04108000 Base Address 0x04100730 Time Synchronization setting RTC1 0x0410900...

Page 175: ... Alarm Flag 0x00000000 0x20 OffsetVal RW Correction value of Time Counter PreCounter 0x00000000 0x24 OffsetReq RW Correction request for Time Counter PreCounter 0x00000000 0x28 RtcSyncReq RW Synchronization request to other RTC synchronizing one RTC s time with another RTC s time 0x00000000 0x2C Reserved RO Reserved 0x00000000 Table RTC 64 Register List of Time Counter Value Read Control System Of...

Page 176: ...mOutEn0 RW Enable Signal Control and Status of O Err Alarm0 Read Value of DbgAlmOutEn0 Enable Signal Value for Alarm0 currently used by RTC The status of some bits is RO 0x00000000 0x78 AlmOutEn1 RW Enable Signal Control and Status of O Err Alarm1 Read Value of DbgAlmOutEn1 Enable Signal Value for Alarm1 currently used by RTC The status of some bits is RO 0x00000000 0x7C AlmOutEn2 RW Enable Signal...

Page 177: ...x00000000 0xB4 CntUpdateEn RW Enable Signal Control of interrupt notifying update completion of RTC Counter 0x00000000 0xB8 CntUpdateFlg RO Interrupt flag notifying update completion of RTC Counter 0x00000000 0xBC Reserved RO Reserved 0x00000000 0xC0 DiffSignBit RO Sign bit of difference value between one RTC Counter and other RTC Counter 0x00000000 0xC4 DiffPostCnt RO Read Value of difference val...

Page 178: ...et in the RTC0 can be read The following are registers that do not return to initial values AlmOutEn 0 1 2 Dbg AlmOutEn 0 1 ErrDbg DbgSetAlmPostCnt 0 1 2 Dbg DbgSetAlmPreCnt 0 1 2 Dbg AlmFlg Flg 0 1 2 AlmFlg ErrFlg 0 1 3 6 5 2 1 WrRegPostCnt 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Post RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Post RW bit 31 0 Post 31 0 PostCounter Write Value This is ...

Page 179: ... 9 8 7 6 5 4 3 2 1 0 Reserved Busy A RW When you write 1 on WrRegReq BusyA this register issues a write request After the write request is issued WrRegPostCnt values and WrRegPreCnt values are reflected on RTC Counter values Of RTC Counter 47 bits WrRegPostCnt values are reflected on higher 32 bits and WrRegPreCnt values are reflected on lower 15 bits This register is cleared to 0 after executing ...

Page 180: ...unter and PreCounter separately and the internal RTC is synchronized with the external RTC You can cancel Request for waiting for External Alarm Flag by writing 1 on WrIntClr register Busy Description of Functions 0 Writing 0 You cannot write 0 1 Writing 1 makes internal RTC come into the status of waiting for the External Alarm Flag When the internal RTC detects the External Alarm Flag during thi...

Page 181: ...ons 0 Writing 0 You cannot write 0 1 Writing 1 cancels a Request for waiting for External Alarm Flag When it is canceled this register is cleared to 0 automatically 3 6 5 2 6 OffsetVal 0x20 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Offset RW bit 7 0 Offset 7 0 Correction value of RTC Counter value This register adds Offset value to RTC ...

Page 182: ...ion request for RTC Counter value This register issues a correction request for RTC Counter value After issuing the request it adds OffsetVal value to RTC Counter BusyA Description of Functions 0 Writing 0 You cannot write 0 1 Writing 1 issues a correction request for RTC After correcting RTC Counter this register is cleared to 0 when the same request becomes possible to be issued again ...

Page 183: ...r makes one RTC import the other internal RTC counter value to its own value and makes it synchronize with the other RTC Example When this register issues a synchronization request to RTC0 RTC0 imports RTC1 s RTC Counter value and is synchronized with RTC1 Req Description of Functions 0 Writing 0 You cannot write 0 1 Writing 1 issues a synchronization request with the other RTC Counter After compl...

Page 184: ...eCnt BusyA Description of Functions 0 Writing 0 You cannot write 0 1 Writing 1 issues a Read Request After reflecting values on RdPostCnt and RdPreCnt this register is cleared to 0 automatically when the same request becomes possible to be issued again 3 6 5 2 10 RdPostCnt 0x34 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Post RO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Post RO bit 31 0 Post 31 0 ...

Page 185: ...26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rese rved Pre RO bit 14 0 Pre 14 0 PreCounter value at the time of Read Request By reading this register you can see the PreCounter value at the point of time when the read request was issued ...

Page 186: ...dReq to become 0 Restriction on the use of this register AS for Rt Post Pre Cnt read RtPostCnt before reading RtPreCnt If relation between CK_APB and CK_RTC RTC Clock 32 768kHz is frequency of CK_APB frequency of CK_RTC 10 do not read Rt Post Pre Cnt The value cannot be guaranteed 3 6 5 2 13 RtPreCnt 0x44 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ...

Page 187: ...RTC Counter PostCounter and PreCounter by using absolute value and generates Normal Alarm0 or Error Alarm0 Normal Alarm0 or Error Alarm0 is generated when the RTC Counter value meets the following conditions Normal Alarm is generated if value written on SetAlm Post Pre 0 1 matches RTC Counter value Error Alarm is generated if written value is smaller than RTC Counter value when SetAlmPre 0 1 is se...

Page 188: ...update the Alarm Operation time You can check whether it is in the process of reflecting by using Busy bit 16 Busy SetAlmPreCnt0 Write Busy status This register indicates how far SetAlm Post Pre Cnt0 register is reflected When Busy indicates 1 the register is reflecting Alarm Operation time means that SetAlm Post Pre Cnt0 must not be updated Once the reflection is completed Busy becomes 0 automati...

Page 189: ... 18 17 16 Reserved Busy RO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rese rved Pre RW bit 31 0 Pre 14 0 Comparison Value of PreCounter for AlmFlg Flg1 and AlmFlg ErrFlg1 This register sets Operation Time PreCounter of the Alarm1 It takes time to reflect a new Alarm Operation time During reflecting do not update the Alarm Operation time You can check whether it is in the process of reflecting by using ...

Page 190: ...time passes to the value set on SetAlm Post Pre Cnt2 starting from the time written on SetAlmPreCnt2 3 6 5 2 19 SetAlmPreCnt2 0x64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved Busy RO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rese rved Pre RW bit 31 0 Pre 14 0 Comparison Value of PostCounter for AlmFlg Flg2 This register sets Operation Time PreCounter of Alarm2 It takes time to reflect a n...

Page 191: ...curs an Alarm Interrupt is asserted set When a Clear Register is written the Alarm Interrupt can be deasserted reset instantly bit 0 Flg0 Clear of Normal Alarm Flag0 When you write 1 on AlmClr Flg0 Normal Alarm0 Interrupt is deasserted and Normal Alarm Flag0 is cleared Flg0 Description of Functions 0 Writing 0 invalid 1 Writing 1 deasserts Normal Alarm Flag0 When Normal Alarm Flag0 is deasserted t...

Page 192: ...alid 1 Writing 1 deasserts Interrupt of Error Alarm Flag1 When Error Alarm Flag1 is deasserted this register is cleared to 0 automatically 3 6 5 2 21 AlmOutEn0 0x74 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Err Dbg Reserved Err En RO RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dbg Reserved Busy Reserved En RO RO RW bit 0 En Enable Signal for Normal Alarm0 Interrupt This register does the settin...

Page 193: ...larm0 Interrupt that is currently used in RTC By using this register you can check whether the set value has been normally reflected on AlmOutEn0 En or not bit 16 ErrEn Enable Signal for Error Alarm0 Interrupt This register does the settings for notifying processor of Error Alarm Flag0 ErrEn Description of Functions 0 Writing 0 disables an interrupt request to processor Even if conditions are met ...

Page 194: ...uest is disabled However status register AlmFlg Flg1 transitions to 1 b1 if conditions are met bit 8 Busy Write Busy Status This register indicates how far AlmOutEn1register is reflected When Busy indicates 1 the register is reflecting Enable Signal means that AlmOutEn1 must not be updated Once the reflection is completed Busy becomes 0 automatically Busy Description of Functions 0 Reading 0 AlmOu...

Page 195: ...ll be asserted If 1 b0 is set on ErrEn an interrupt request is disabled However status register AlmFlg ErrFlg1 transitions to 1 b1 if conditions are met bit 31 ErrDbg Current Enable Signal Value This register is used for debugging By reading this register you can see Enable Signal value for the Error Alarm1 Interrupt that is currently used in RTC By using this register you can check whether the se...

Page 196: ... will be asserted If 1 b0 is set on En an interrupt request is disabled However status register AlmFlg Flg2 transitions to 1 b1 if conditions are met bit 8 Busy Write Busy Status This register indicates how far AlmOutEn2 register is reflected When Busy indicates 1 the register is reflecting Enable Signal means that AlmOutEn2 must not be updated Once the reflection is completed Busy becomes 0 autom...

Page 197: ...when set value of Alarm0 matches RTC Counter value Flg1 when set value of Alarm1 matches RTC Counter value Flg2 when time passes to the set value of Alarm2 based on the RTC Counter value at the time of being written on SetAlmPreCnt2 ErrFlg0 when set value of Alarm0 at the time of being written on SetAlmPreCnt0 is smaller than RTC Counter value ErrFlg1 when set value of Alarm1 at the time of being ...

Page 198: ...f Functions 0 Error Alarm1 Interrupt is deasserted 1 Error Alarm1 Interrupt is asserted 3 6 5 2 25 DbgSetAlmPostCnt0 0x90 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Dbg RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dbg RW bit 31 0 Dbg 31 0 Current SetAlmPostCnt0 value This register is used for debugging By reading this register you can see SetAlmPostCnt0 value that is currently used in RTC By usin...

Page 199: ...9 18 17 16 Dbg RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dbg RW bit 31 0 Dbg 31 0 Current SetAlmPostCnt1 value This register is used for debugging By reading this register you can see SetAlmPostCnt1 value that is currently used in RTC By using this register you can check whether the set value has been normally reflected on SetAlmPostCnt1 or not 3 6 5 2 28 DbgSetAlmPreCnt1 0x9C 31 30 29 28 27 26 25 ...

Page 200: ...plus RTC Counter value at the time when SetAlmPreCnt2 was written By using this register you can check whether the set value has been normally reflected on SetAlmPostCnt2 or not 3 6 5 2 30 DbgSetAlmPreCnt2 0xA4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rese rved Pre RW bit 14 0 Dbg 14 0 Current SetAlmPreCnt2 Value This register is used for debug...

Page 201: ...that RTC Counter has been updated When you write 1 on CntUpdateClr Flg the interrupt flag notifying that RTC Counter has been updated is deasserted and cleared to 0 Flg Description of Functions 0 Writing 0 invalid 1 Writing 1 deasserts interrupt flag notifying that RTC Counter has been updated 3 6 5 2 32 CntUpdateEn 0xB4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 ...

Page 202: ...he interrupt flag notifying that RTC Counter has been updated Interrupt value before being controlled Enabled or Disabled by CntUpdateEn If RTC Counter is updated under the following conditions CntUpdateFlg becomes 1 If you want to clear CntUpdateFlg to 0 write 1 on CntUpdateClr Update of RTC Counter value Synchronization of external RTC Synchronization between internal RTCs Correction of RTC Coun...

Page 203: ...ted Val Description of Functions 0 Positive 1 Negative Restriction on the use of this register Check the interrupt flag notifying that RTC Counter has been updated CntUpdateFlg 0xB8 before reading DiffSignBit DiffPostCnt and DiffPretCnt 3 6 5 2 35 DiffPostCnt 0xC4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Val RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Val RW bit 31 0 Val 31 0 Difference from o...

Page 204: ...ved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CLK NEG EDG E_E N Reserved SYNC_SEL Reserved EXT AL M_P OL Reserved EXTALM_S EL RW RW RW RW bit 1 0 EXTALM_SEL 1 0 External Alarm Output Select Signal This register selects one AlarmFlag from AlarmFlag0 AlarmFlag1 and AlarmFlag2 as an Alarm output outside RTC0_ExtAlm EXTALM_SEL Description of Functions 0 AlarmFlag0 AlmFlg Flg0 is used as an Extern...

Page 205: ...on 1 RTC1_ExtAlm is used as a trigger of Time Synchronization 2 When IOCSYS_IOMD0 PMIC_INT indicates 2 this alarm is used For details refer to Chapter 3 1 4 3 2 3 When IOCSYS_IOMD0 PMIC_INT indicates 3 this alarm is used For details refer to Chapter 3 1 4 3 3 bit 12 CLKNEGEDGE_EN Inverted Clock Setting By using this register External Output Alarm and Time Synchronization Trigger Signal are set whe...

Page 206: ...1_ExtAlm 2 AlarmFlag2 is used as an External Output Alarm RTC1_ExtAlm 3 0 is output as an External Output Alarm RTC0_ExtAlm When EXTALM_POL indicates 0 1 is output as an External Output Alarm RTC0_ExtAlm When EXTALM_POL indicates 1 bit 4 EXTALM_POL External Alarm Output Select Signal This register sets signal logic positive logic or negative logic of External Output Alarm EXTALM_POL Description of...

Page 207: ...External Output Alarm and Time Synchronization Trigger Signal are set whether to synchronize at the falling edge of the clock EXTALM_POL Description of Functions 0 External Output Alarm and Time Synchronization are performed at the rising edge of the clock External Output Alarm and Time Synchronization Trigger Signal synchronize to usual clock rising edge of the clock 1 External Output Alarm and T...

Page 208: ... polling to WrRegReq BusyA until it returns to 0 receiving interrupt request CntUpdateFlg which means that RTC Counter has been updated 3 6 5 3 2 Correction of RTC Counter Value This function is used to correct RTC Counter values You can set corrected RTC Counter values by providing current RTC Counter value with relative values The sequence is as follows 1 Write a correction value on OffsetVal re...

Page 209: ...register write the time Y 46 0 0x3 Δ that synchronizes with internal RTC Δ is a difference between the LSI and the PMIC For details refer to chapter Difference Calculation between CXD5602 and CXD5247 When Δ is 0x0 calculate the formula replacing the Δ with 0x40 When the synchronization is performed between internal RTCs calculate the formula replacing the Δ with 0x40 at all times The following are...

Page 210: ... refer to Alarm Output Setting and for Output Selection of External Output Alarm refer to RTC0_RTC_CTL 0x04100730 If you want to synchronize the value of CXD5602 with CXD5247 when the value of PostCounter 31 0 PreCounter 14 0 has reached X 46 0 the time to output External Output Alarm to CXD5247 will be set as follows For example when EXTALM_SEL is set as 2 the setting value of SetAlmPostCnt2 31 0...

Page 211: ... synchronization of time counter value is performed between RTC0 and RTC1 When a synchronization request is issued to one RTC it takes in the RTC Counter value of another RTC and gets synchronized with another RTC When you synchronize RTC0 with RTC Counter value of RTC1 write 1 on RtcSyncReq of RTC0 When you synchronize RTC1 with RTC Counter value of RTC0 write 1 on RtcSyncReq of RTC1 You can chec...

Page 212: ...e that you want to output an Alarm When you do not use Alarm anymore after outputting an Alarm 1 Write 0 on AlmOutEn0 En and AlmOutEn0 ErrEn registers Disable O Err Alarm0 to be output 2 Write 1 on AlmClr Flg0 and AlmClr ErrFlg0 registers Clear Normal and Error Alarm Flags to 0 3 7 I2C 3 7 1 Features and Overview This LSI integrates four I2C masters I2C List I2C0 Power domain PWD_SCU I2C1 Power do...

Page 213: ...IOP ck_ahb_gear ck_com_gear MHz 32 500 31 200 26 000 8 192 0 032768 I2C2 BCK kbps 400 400 400 356 1 424696 I2C4 BCK kbps 400 400 400 356 1 424696 SCU ck_scu_pre MHz 13 000 8 192 0 032768 I2C0 I2C1 BCK kbps 400 356 1 424696 SYSPLL 3 7 2 I2C0 I2C1 The I2C0 and I2C1 are the I2C masters and support Standard and Fast Mode In addition to direct control from the System and I O Processor they can be contr...

Page 214: ... RCOSC XOSC 0 3 2 1 1 2 1 3 1 4 CKSEL_SCU SEL_SCU_XTAL 0 3 2 1 0 1 RTC_CLK_IN 32 768kHz 1 250 ck_scu_pre CKSEL_SCU SEL_SCU_32K Reserved CKSEL_SCU SEL_SCU I2C0 PCLK I2CCLK PRESETn I2C1 PCLK I2CCLK PRESETn SWRESET_SCU XRST_SCU_I2C1 CK GATE SCU_CKEN SCU_I2C1 Control by sequencer Control by sequencer Figure I2C 39 I2C0 I2C1 Clock and Reset System The I2C0 and I2C1 are integrated within the SCU and clo...

Page 215: ...mmy read to wait for completion of preceding setting 2 Clock stop SCU_CKEN SCU_I2C0 1 b0 SCU_CKEN SCU_I2C1 1 b0 Reads the address 0x0418D400 of I2C0 dummy read to wait for completion of preceding setting Reads the address 0x0418D800 of I2C1 dummy read to wait for completion of preceding setting 3 Reset cancel SWRESET_SCU XRST_SCU_I2C0 1 b1 SWRESET_SCU XRST_SCU_I2C1 1 b1 4 Clock supply start SCU_CK...

Page 216: ...g the I2C2 register supply the clock to the AHB APB Bus Bridge SWRESET_BUS XRST_I2CM_SUB CK GATE SYSIOP_SUB_CKEN I2CM_SUB 1 M CKDIV_COM CK_COM 0 3 2 1 RCOSC XOSC RTC_CLK_IN 32 768kHz AHB APB BusBridge CK GATE 1 M SYSIOP_SUB_CKEN AHB_BRG_COMIF ck_cpu_bus CKDIV_CPU_DSP_BUS CK_M0 CKDIV_CPU_DSP_BUS CK_AHB ck_rf_pll_1 PWD_RESET0 PWD_SYSIOP_SUB ck_ahb_gear ck_com_gear SYSPLL 0 3 2 1 0 1 1 2 1 3 1 4 1 5 ...

Page 217: ... initialization SYSIOP_SUB_CKEN I2CM_SUB 1 b1 Reads the address 0x041AA000 of I2C2 dummy read to wait for completion of preceding setting 3 Clock stop SYSIOP_SUB_CKEN I2CM_SUB 1 b0 Reads the address 0x041AA000 of I2C2 dummy read to wait for completion of preceding setting 4 Reset release SWRESET_BUS XRST_I2CM_SUB 1 b1 5 Clock supply start SYSIOP_SUB_CKEN I2CM_SUB 1 b1 3 7 3 3 2 Clock Supply Stop T...

Page 218: ...C4 Before accessing the I2C4 registers make sure to set CKSEL_PMU SEL_RTC_PCLK 1 b0 and SYSIOP_CKEN APB 1 b1 SWRESET_BUS XRST_PMU_I2CM CK GATE ck_apb_gear 1 M CKDIV_CPU_DSP_BUS CK_AHB 0 3 2 1 RCOSC XOSC RTC_CLK_IN 32 768kHz ck_cpu_bus ck_rf_pll_1 SYSPLL 0 3 2 1 0 1 1 2 1 3 1 4 1 5 CKSEL_ROOT RFPLL1_STAT_CLK_SEL4 CKSEL_ROOT CPU_PLL_DIV5 I2C4 PCLK I2CCLK PRESETn 0 3 2 1 Reserved PMU_CORE_CKEN RTC_PC...

Page 219: ...my read to wait for completion of preceding setting 2 Clock stop PMU_CORE_CKEN RTC_PCLK 1 b0 PMU_CORE_CKEN PMU_RTC_PCLK 1 b0 Reads the address 0x04106000 of I2C4 dummy read to wait for completion of preceding setting 3 Reset release SWRESET_BUS XRST_PMU_I2CM 1 b1 4 Clock supply start PMU_CORE_CKEN RTC_PCLK 1 b1 PMU_CORE_CKEN PMU_RTC_PCLK 1 b1 3 7 4 3 2 Clock Supply Stop The following describes the...

Page 220: ...erforms DMA transfer between each SRAM IDMAC Power domain PWD_APP_SUB The IDMAC performs DMA transfer of the Display and Wi Fi data 3 8 2 Function Descriptions SDMAC The PrimeCell µDMA Controller PL230 from ARM Limited is equipped There are 32 channels of DMA channels For details refer to the PrimeCell µDMA Controller PL230 Technical Reference Manual This Controller adds a feature to notify the CP...

Page 221: ...0 TX Reserved UART1 RX Reserved SPI5 RX 6 LPADC0 UART0 RX Reserved SPI0 TX Reserved Reserved 7 LPADC1 Reserved Reserved SPI0 RX Reserved Reserved 8 LPADC2 Reserved Reserved Reserved Reserved Reserved 9 LPADC3 Reserved Reserved Reserved Reserved Reserved 10 HPADC0 Reserved Reserved Reserved Reserved Reserved 11 HPADC1 Reserved Reserved Reserved Reserved Reserved 12 SCU FIFO RX 1 Reserved Reserved R...

Page 222: ...s changed from pulse to level The interrupt factor register dma_done dma_err is added Figure DMAC 42 shows an overview of the independent interrupt signals of each DMA channel Additional logic SDMAC SDMAC PL230 dma_done pulse slave_error pulse set 32 32 clear set clear level Interrupt Clear to CPU Interrupt Interrupt Status Register Figure DMAC 42 SDMAC Overview of Added Functions ...

Page 223: ...r Name Type Description initial Value 0x04120000 0x0412004C PrimeCell µDMA Controller PL230 register 0x04120050 dma_done RW Notifies DMA transfer completion of each DMA channel 0x0 0x04120054 dma_err RW Notifies AHB error occurrence of each DMA channel 0x0 0x04120058 0x04120DFC Reserved RO Reserved 0x0 0x04120E00 0x04120FFC PrimeCell µDMA Controller PL230 register ...

Page 224: ...umber of AHB error occurrence Read as 0 AHB no error occurred 1 AHB error occurred Write as 0 No effect 1 Set dma_err LOW 3 8 3 3 Clock and Reset Figure DMAC 43 shows the clock and reset system diagram of the SDMAC Reset of the SDMAC is automatically released when the PWD_SYSIOP power domain is turned ON 0 3 2 1 RCOSC XOSC RTC_CLK_IN 32 768kHz SDMAC CK GATE ck_cpu_bus CKDIV_CPU_DSP_BUS CK_M0 ck_rf...

Page 225: ...rform the following control to stop supplying the HCLK clock of the SDMAC 1 Clock supply stop SYSIOP_CKEN AHB_DMAC0 1 b0 3 8 4 HDMAC Adds a feature to notify the CPU of independent interrupts of each DMA channel to the PrimeCell Single Master DMA Controller PL081 Figure DMAC 44 shows an overview of the added functions Additional logic Conventional logic HDMAC PL081 Chennel0 IntErrCh0 IntTCCh0 Chen...

Page 226: ...urned ON 0 3 2 1 RCOSC XOSC RTC_CLK_IN 32 768kHz HDMAC CK GATE ck_cpu_bus CKDIV_CPU_DSP_BUS CK_M0 ck_rf_pll_1 ck_ahb_gear SYSPLL 0 3 2 1 0 1 1 2 1 3 1 4 1 5 CKSEL_ROOT RFPLL1_STAT_CLK_SEL4 CKSEL_ROOT CPU_PLL_DIV5 CKDIV_CPU_DSP_BUS CK_AHB HCLK SYSIOP_CKEN AHB_DMAC1 Auto PWD_SYSIOP Power Domain ON HRESETn 1 M 1 M CKSEL_ROOT STAT_CLK_SEL4 Figure DMAC 45 HDMAC Clock and Reset System 3 8 4 3 Clock Supp...

Page 227: ...ingle Master DMA Controller PL081 register 3 8 5 2 Clock and Reset Figure DMAC 46 shows the clock and reset system diagram of the SYDMAC Reset of the SYDMAC is automatically released when the PWD_SYSIOP power domain is turned ON 0 3 2 1 RCOSC XOSC RTC_CLK_IN 32 768kHz SYDMAC CK GATE ck_cpu_bus CKDIV_CPU_DSP_BUS CK_M0 ck_rf_pll_1 ck_ahb_gear SYSPLL 0 3 2 1 0 1 1 2 1 3 1 4 1 5 CKSEL_ROOT RFPLL1_STAT...

Page 228: ... to stop supplying the HCLK clock of the SYDMAC 1 Clock supply stop SYSIOP_CKEN AHB_DMAC2 1 b0 3 8 6 SYSUBDMAC 3 8 6 1 Register List Table DMAC 88 shows the registers that control the SYSUBDMAC Table DMAC 80 SYSUBDMAC Control Register List Address Register Name Type Description initial Value 0x04123000 0x04123FFC PrimeCell Single Master DMA Controller PL081 register 3 8 6 2 Clock and Reset Figure ...

Page 229: ...t System 3 8 6 3 Clock Supply Start and Stop 3 8 6 3 1 Clock Supply Start Perform the following control to start supplying the HCLK clock of the SYSUBDMAC 1 Reset release Automatically released when the PWD_SYSIOP_SUB power domain is turned ON 2 Clock supply start SYSIOP_SUB_CKEN AHB_DMAC3 1 b1 3 8 6 3 2 Clock Supply Stop 1 Clock supply stop SYSIOP_SUB_CKEN AHB_DMAC3 1 b0 3 8 7 ADMAC 3 8 7 1 Regis...

Page 230: ...SEL STAT_SP_CLK_SEL4 Figure DMAC 48 ADMAC Clock and Reset System 3 8 7 3 Clock Supply Start and Stop 3 8 7 3 1 Clock Supply Start Perform the following control to start supplying the HCLK clock of the ADMAC 1 Reset release PWD_RESET0 PWD_APP 1 b1 RESET xrs_dsp_gen 1 b1 2 Supply the CK_APP Refer to APP Chapter 3 13 3 AHB bus clock supply and division ratio setting GEAR_AHB gear_m_ahb arbitrary deno...

Page 231: ...HB Slave Interface Channel0 Channel1 Channel2 Channel3 Channel4 Channel5 Channel6 Channel7 AHB Master 1 Internal Arbiter Bus Request AHB Master 2 Internal Arbiter Bus Request Bus Interface Bus Interface HADDRM1 31 0 HWRITEM1 HSIZEM1 2 0 HPROTM1 3 0 HLOCKM1 HTRANSM1 1 0 HBURSTM1 2 0 HWDATAM1 31 0 HRDATAM1 31 0 HRESPM1 1 0 HREADYINM1 HBUSREQM1 HGRANTM1 HADDRM2 31 0 HWRITEM2 HSIZEM2 2 0 HPROTM2 3 0 H...

Page 232: ...uest register 0 0x04123024 DMACSoftSReq RW Software single request register 0 0x04123028 DMACSoftLBReq RW Software last burst request register 0 0x0412302C DMACSoftLSReq RW Software last single request register 0 0x04123030 DMACConfiguration RW Configuration register 0x0400 0x04123034 DMACSync RW Synchronization register 0xFFFF 0x04123038 DMACSReqMask RW Single Request Mask register 0xFFFF 0x04123...

Page 233: ...4123000 DMACIntStatus RO 31 0 0 Same as PL080 0x04123004 DMACIntTCStatus RO 31 0 0 Same as PL080 0x04123008 DMACIntTCClr W 31 0 Same as PL080 0x0412300C DMACIntErrorStatus RO 31 0 0 Same as PL080 0x04123010 DMACIntErrClr W 31 0 Same as PL080 0x04123014 DMACRawIntTCStatus RO 31 0 0 Same as PL080 0x04123018 DMACRawIntErrorSta tus RO 31 0 0 Same as PL080 0x0412301C DMAEnbldChns RO 31 0 0 Same as PL08...

Page 234: ... Can read out whether or not there is a DefLLI function of the DMAC Takes the following values depending on the configuration of the DMAC 0 Disables the DefLLI function 1 Enables the DefLLI function TS RO 10 1 b1 Can read out whether the Channel Control register mapping of the DMAC is TransferSize expanded mapping or Default mapping Takes the following values depending on the configuration of the ...

Page 235: ...es the control information of each channel s transfer size burst size transfer data width etc during the DMA data transfer This register must be set before the corresponding DMA channel is enabled When Scatter Gather transfer is being performed it will be automatically updated to the value of the corresponding linked list I RW 31 1 b0 When DMACConfiguration TS 1 TransferSize expanded mapping The e...

Page 236: ...used for the source data transfer 0 Selects AHB master 1 for the source data transfer 1 Selects AHB master 2 for the source data transfer DWIDTH RW 26 25 0 When DMACConfiguration TS 1 TransferSize expanded mapping Indicates the transfer data size of the destination bus 0 byte transfer 1 halfword transfer 2 word transfer 3 Reserved SWIDTH RW 24 23 0 When DMACConfiguration TS 1 TransferSize expanded...

Page 237: ...actually transferred can be calculated by multiplying this burst size by the DWidth 0 1 Burst 1 4 Burst 2 8 Burst 3 16 Burst SSIZE RW 20 19 0 When DMACConfiguration TS 1 TransferSize expanded mapping Indicates the burst size of the source data transfer Make sure to set this value to the burst size of the source peripheral or to the memory boundary size if the memory is the source The burst size se...

Page 238: ...r various settings of the DMA channels This register does not change by update of the LLI item TRIGGER PERPHER AL RW 31 28 0 When DMACConfiguration TR 1 when waiting for external trigger This is the selection bit for external trigger Peripheral When the external trigger function is disabled this bit is invalid When DMACConfiguration TR 0 when operating without external trigger Becomes Reserved Whe...

Page 239: ...ess of the Source side so that it always conforms to the burst length set by SBSize This is used to raise the efficiency of memory access However since the FIFO size is 16 32 64 bytes 4 8 16 burst is the largest number of bursts in word size Be cautious with the SBSize setting of the Channel Control register Reserved RO 23 19 0 Reserved HALT RW 18 0 Same as PL080 ACTIVE RW 17 0 Same as PL080 LOCK ...

Page 240: ...fore starting data transfer and following the update of SrcAddr DestAddr LLI and Control the transfer starts DEFLE RW 1 0 Selects enable disable of the DefLLI function 0 Disabled 1 Enabled DEFLM RW 0 0 Sets the AHB bus master channel that becomes active when the DefLLI is loaded 0 Selects AHB master 1 1 Selects AHB master 2 0x04123500 DMACITCR RW 31 0 0 Same as PL080 0x04123504 DMACITOP1 RW 31 0 0...

Page 241: ... s SrcAddr DstAddr and Swidth Dwidt 1 If Swidth Word SrcAddr 1 0 2 b00 2 If Swidth HalfWord SrcAddr 0 1 b0 3 If Dwidth Word DstAddr 1 0 2 b00 4 If Dwidth HalfWord DstAddr 0 1 b0 About Transfersize When the Dwidth is larger than the Swidth in each DMAC channel depending on the TransferSize broken numbers may occur against the data width and the transfer cannot be completed and the data will be lost...

Page 242: ...CKSEL STAT_SP_CLK_SEL4 Figure DMAC 50 IDMAC Clock and Reset System 3 8 8 4 Clock Supply Start and Stop 3 8 8 4 1 Clock Supply Start Perform the following control to start supplying the HCLK clock of the IDMAC 1 Reset release PWD_RESET0 PWD_APP 1 b1 RESET xrs_img 1 b1 2 Supply the CK_APP Refer to APP Chapter 3 13 3 AHB bus clock supply and division ratio setting GEAR_AHB gear_m_ahb arbitrary denomi...

Page 243: ...each sensor interface refer to the Chapters of each function 2 Sequencer Functions for capturing sensor data The Sequencer performs the following sequence of processes Using the designated time intervals as a trigger it intermittently captures the sensor data from the sensor I F Performs arithmetic processing MATH_PROC to the sensor data and stores the results in the FIFO within the SCU When stori...

Page 244: ...or data The following arithmetic processing can be executed in a programmable fashion Unsigned data signed data conversion Gain multiplication by each vector element Offset addition by each vector element Decimation Multiplication processing with clipping 2nd order IIR filter Normalization Processing Excess Detection Event 5 PWM function that is capable of external output The SCU has eight channel...

Page 245: ...SCU Block Diagram CXD5602 ASYNC MUX SCU_REG SCU_LOGIC PWD_SCU SEQUENCER MATH_PROC Arbiter MUX MUX SPI I2C0 I2C1 ADCIF Arbiter PWM SCU_FIFO SCU_ANALOG LPADC HPADC SEL HOSTIFC ASYNC Figure SCU Sensor Control Unit 51 Block Function Overview ...

Page 246: ...DC 4K SDMAC 4K HDMAC 4K SYDMAC 4K SYSUBDMAC 4K BKUPSRAM 64K 0x0040_0000 0x0040_FFFF 0x0041_0000 Reserved 11 9M 0x00FF_FFFF 0x0100_0000 SPIFLASHIF 256M Reserved 1792M SYS_CPU_Local 48M 0x0012_3FFF 0x0010_AFFF 0x0010_9FFF 0x0010_A000 0x0010_8FFF 0x0010_9000 0x0010_0000 0x0010_2FFF 0x0010_3000 0x0010_5FFF 0x0010_6000 0x0010_6FFF 0x0010_7000 0x0010_7FFF 0x0010_8000 0x0012_2FFF 0x0012_3000 0x0012_1FFF ...

Page 247: ...e FIFO 4 KByte is the port for data writing and readout Refer to Table SCU Sensor Control Unit 103 for details The FIFO REG 8 KByte handles controls around the FIFO Refer to Section 3 9 12 10 for details The SCU_REG 4 KByte is the control register Refer to Section 3 9 12 3 for details The DRAM 2 KByte is used as the SCU_RAM Refer to Section 3 9 12 11 for details The IRAM 8 KByte is used as the SEQ...

Page 248: ...ry Mapping as seen from the SCU window of the HOSTIFC Figure SCU Sensor Control Unit 55 Memory Mapping as seen from the HOSTIFC The Reserved area within this Figure is writing invalid no error response and 0 read during readout no error response The Reserved area within this Figure is writing invalid no error response and 0 read during readout no error response ...

Page 249: ...MHz 8MHz For HPADC 1 CK_SCU_U32KL 32kHz 32kHz For LPADC 1 CK_SCU_U32KH 32kHz 32kHz For HPADC 1 CK_SCU_32K 32kHz 32kHz For PWM CK_SCU_BRG_HCLK 13MHz 13MHz For AHB BUS 1 For details on the clocks for the HPADC and LPADC refer to the Chapter on ADC 3 21 3 9 4 2 Logic System High Speed Clocks CK_SCU_SCU CK_SCU_SCU_SC CK_SCU_SPI for SPI CK_SCU_I2C0 for I2C0 CK_SCU_I2C1 for I2C1 CK_SCU_SEQ for SEQ CK_SC...

Page 250: ... 768 kHz RCOSC divided by 250 Use the API to select these clock sources 3 9 4 4 HPADC Clock and LPADC Clock For details on the HPADC clock and LPADC clock refer to the Chapter on ADC 3 21 clock control 3 9 4 5 Clock Control Summary The following table summarizes the selection of input clocks For details on the LPADC and HPADC clocks refer to the Chapter on ADC 3 21 Table SCU Sensor Control Unit 83...

Page 251: ... 0 3 2 1 DIV CKSEL_SCU SCU_XTAL CKSEL_SCU SEL_SCU CK_SCU_SCU_SC CG configure unavailable SCU CK_SCU_32K CG CG CK_SCU_SCU_SPI CK_SCU_SCU_SEQ CG CG CK_SCU_SCU_I2C0 CK_SCU_SCU_I2C1 2 2 2 2 2 SCU_CKEN 8 SCU_CKEN 5 SCU_CKEN 4 SCU_CKEN 0 SCU_CKEN 3 SCU_CKEN 2 SCU_CKEN 1 CK_SCU_BRG_HCLK 1 control signal from the HOSTIFC sequencer 2 control signal from the SCU sequencer Figure SCU Sensor Control Unit 56 C...

Page 252: ...cer of the HOSTIFC or the internal sequencer of the SCU In the case of controlling from multiple CPUs internal sequencers OR control is used Table SCU Sensor Control Unit 84 Control of each Clock SCU Clock Name Control from the Upper CPU Control from Internal Sequencer of SCU Control from Internal Sequencer of HOSTIFC CK_SCU_SCU possible possible possible CK_SCU_SCU_SC possible CK_SCU_SCU_SPI poss...

Page 253: ...encers SCU Clock Name During Internal Sequencer Sleep During Internal Sequencer Active CK_SCU_SCU OFF ON CK_SCU_SCU_SC Not controlled CK_SCU_SCU_SPI OFF ON only during SPI transfer OFF all other times CK_SCU_SCU_I2C0 OFF ON only during I2C0 transfer OFF all other times CK_SCU_SCU_I2C1 OFF ON only during I2C1 transfer OFF all other times CK_SCU_SCU_SEQ OFF ON CK_SCU_32K Not controlled 3 9 4 7 Clock...

Page 254: ...F clock OFF clock OFF clock OFF ADC is used Internal Sequencer is not used clock ON clock ON clock OFF clock OFF clock OFF clock OFF C C C C clock OFF PWM is used Internal Sequencer is not used clock ON clock OFF clock OFF clock OFF clock OFF clock OFF C C C C clock ON When Internal Sequencer is used clock OFF clock ON clock OFF clock OFF clock OFF clock ON C C C C clock ON C When using the corres...

Page 255: ...errupts which connect to the SYSCPU and DSP For details refer to the Chapter on Interrupt 3 3 The following shows the relation with the interrupt number Table SCU Sensor Control Unit 89 Interrupt Number SCU Interrupt Name Description INT0 SPI interrupt INT1 I2C0 interrupt INT2 I2C1 interrupt INT3 Event Interrupt 3 9 6 2 Interrupt Details The interrupts that occur within the SCU are connected to th...

Page 256: ... can be read out The Edge interrupt factor can be cleared In addition depending on the interrupt factor Level Edge selection is possible Figure SCU Sensor Control Unit 57 shows the connections of the INT_SEL SCU_REG SCU_INT_SEL Configuration Data ex EN CLR etc SPI I2C0 I2C1 SCU_ADCIF SCU_FIFO SCU_SEQ_CTRL SCU_PWM 0 7 4 PWD_SCU M0 M4 CPU Figure SCU Sensor Control Unit 57 Interrupt Connections ...

Page 257: ...Math Function n within the MATH_PROC Edge D0_Rn_C_ALM OST_FULL 2 n 1 2 The data amount stored in the FIFO partition D0_Rn has reached the Watermark Selecta ble D1_Rn_C_ALM OST_FULL 2 n 1 2 The data amount stored in the FIFO partition D1_Rn has reached the Watermark Selecta ble Nn_R1_C_ALM OST_FULL 8 n 0 7 The data amount stored in the FIFO partition Nn_R1 has reached the Watermark Selecta ble Dn_R...

Page 258: ...d Level LPADC_UND ER_RUNn 4 n 0 3 The FIFO for the n th channel of the LPADC within the ADCIF was empty but readout Edge HPADCn_UN DER_RUN 2 n 1 2 The FIFO for the n th channel of the HPADC within the ADCIF was empty but readout Edge D0_Rn_C_UN DER_RUN 2 n 1 2 The FIFO partition D0_Rn was empty but readout Level D1_Rn_C_UN DER_RUN 2 n 1 2 The FIFO partition D1_Rn was empty but readout Level Nn_R1_...

Page 259: ...e or more data HPADCn_NOT_EMP TY 2 n 0 1 The FIFO for the n th channel of the HPADC has one or more data MATH_PROC_WRIT E_DATA_READY 1 Indicates whether or not writing is possible to the MATH_PROC MATH_PROC_READ _DATA_READY 1 Indicates whether or not readout is possible from the MATH_PROC FIFO0_ALL_ON_STT 1 Indicates that the power supply status of the FIFO SRAM 8 KByte is All On FIFO1_ALL_ON_STT ...

Page 260: ... can be handled Preprocessing For details see Section 3 9 7 1 Unsigned data signed data conversion Gain multiplication by vector element Offset addition by vector element Decimation Processing For details see Section 3 9 7 2 Decimation Multiplication processing with clipping Math Function Processing For details refer to Section 3 9 7 3 2nd order IIR filters Normalization processing Excess detectio...

Page 261: ...ned 16bit Afterwards the Math Function can be assigned The Math Function processing can be inserted in up to three paths among the total of 16 paths in the MATH_PROC four paths per Decimation Partition Data Path x two lines 1 path per Normal Sensor Partition Data Path x eight lines In the Decimation Partition Data Path example in Figure SCU Sensor Control Unit 58 the Math Function is inserted only...

Page 262: ...equencer and SEQ1 sequencer The decimation path has four output paths per each input and 1 2 n decimation can be selected for three of them depending on the settings A two stage CIC filter process is applied for the decimation processing For the three target paths of decimation the results of decimation the input signal in its original form or the setting for 0 fixed output can be selected Also af...

Page 263: ...Order IIR Filter The Math Function is a function block comprised of 2nd order IIR Filters normalization processing and excess detection Of the 16 paths for writing to the FIFO within the MATH_PROC up to three can be independently inserted in arbitrary paths Within the Math Function there are the two following data paths 1 Path that outputs to the FIFO 2 Path that is input to the excess detection a...

Page 264: ...on The path on the top is output to the FIFO and the path on the bottom is used for excess detection Also at blocks 1 through 8 in Figure SCU Sensor Control Unit 62 two 2nd order IIR filters can be inserted at arbitrary points by setting the registers Figure SCU Sensor Control Unit 63 shows the combination of data paths when 2nd order IIR filters are inserted ...

Page 265: ...1000 Norm 2nd order IIR 2nd order IIR 2nd order IIR 2nd order IIR Norm Excess Detector 4 b1001 Norm 2nd order IIR 2nd order IIR Excess Detector 4 b1010 Norm 2nd order IIR 2nd order IIR Excess Detector 4 b1100 2nd order IIR Norm 2nd order IIR Excess Detector else Norm Figure SCU Sensor Control Unit 63 2 2nd Order IIR Filter Combinations The 2nd order IIR Filters allows settings of five multiplicati...

Page 266: ... when the three axes have the same value However in normalization processing the values are calculated as approximates to a rectangular octagon when converting from two axes 1st order The absolute value of the input is output as is Output x 2nd order Output 123 128 x Max x y 51 128 x Min x y 3rd order L1 120 128 x Max x y 49 128 x Min x y Output Max L1 z 44 128 x Min L1 z Figure SCU Sensor Control...

Page 267: ...ermination By using registers you can delay the interrupt occurrence which is output in response to the determination The occurrence of the two interrupts Rise interrupt which indicates the transition from Low to High and Fall interrupt which indicates the transition from High to Low can be selected independently Figure SCU Sensor Control Unit 66 shows an example of the input value s change with t...

Page 268: ...urrence conditions using Rise interrupt as an example Precondition UCOUNT0 Number of status continuity of the top threshold of the status continuity determination 0 LCOUNT0 Number of status continuity of the bottom threshold of the status continuity determination 0 UCOUNT1 Number of status continuity of the top threshold of the status continuity determination 1 DELAY_SAMPLE_R Delay of Rise interru...

Page 269: ...AY_SMAPLE_R 7 and the detection result is Lower for two consecutive times a Rise interrupt occurs after seven sample times regardless of the detection result that follows E g When UCOUNT0 2 UCOUNT1 4 DELAY_SAMPLE_R 2 and the detection result is Upper for two consecutive times Status Continuity Determination 0 is Upper and this state is held four times after status changes to Upper the detection re...

Page 270: ...s Writing is stopped regardless of the Rise Fall interrupts 3 9 8 FIFO 3 9 8 1 Overview The FIFO operation is such that the values written to the writing ports of the two SRAMs 8 KByte 32 Kbyte each can be readout from the readout ports in the same order The SRAMs are divided into regions called Partitions where each one can be used as FIFO Up to 27 partitions can be used 3 9 8 2 FIFO Writing Data...

Page 271: ...e a one to one relation and the readout ports that are not used must be set to disable When performing power supply control of the SRAM the partition region must not be set across the 8 Kbytes and 32 Kbytes of the two SRAMs The number of each partition s writing ports readout ports depends on the type of the partition For clarification Table SCU Sensor Control Unit 102 shows the mnemonics for each...

Page 272: ...0 R0_W_CH R0_R_CH Not Available Not Available Not Available The one to two character suffix of the mnemonic describes the access privileges for the given writing port readout port as follows S For partitions that can be written to from the SCU C For partitions that can be written to readout from the CPU H For partitions that can be readout from the Host CH For partitions that can be written to rea...

Page 273: ...ture it does not have physical writing ports or physical readout ports 3 9 8 4 Decimation Partition The Decimation partition stores the data that was decimation processed by the MATH_PROC There are two sets of Decimation partitions each of which is comprised of four sub partitions Within each sub partition of the Decimation partition data can be stored as either Calculation Operable Sample Type or...

Page 274: ...can be set as the Random Access partition The Random Access partition has a non FIFO structure and data can be randomly written and readout to from the CPU or Host Reading Writing access is possible be selecting an arbitrary address from the 40 Kbytes of the SRAM However caution is required so that the data of other partitions is not corrupted by exceeding the region secured for the Random Access ...

Page 275: ...rtition has time stamp information Time stamps are count values of 47 bits that are incremented at 32 768 kHz intervals The upper 32 bits indicate integer part of second while the lower 15 bits are values of second after the decimal point 3 9 8 8 1 Time Stamp Value Handling at the Writing Side The partition to which data is written from the SCU internal sequencer is directly connected to the time ...

Page 276: ...t must have a one to one relation and the readout ports that are not used must be disabled When performing power supply control of the SRAM do not set the partition region across the 8 Kbyte and 32 KByte SRAMs When performing a Clear to the FIFO writing port also make sure to perform a Clear to the corresponding readout port When changing FIFO_ENABLE from Disable to Enable make sure to perform a C...

Page 277: ...e output to be duplicated to one other Write FIFO Data Processing Function When the data is sent to the MATH_PROC a maximum data size of 6 Bytes can be Byte Swapped or Left Bit Shifted in units of 2 Btyes before input to the MATH_PROC Note Since the data processing within the MATH_PROC is performed by the hardware other than the sequencer the internal sequencer is not involved Other Functions SCU ...

Page 278: ...or Control Unit 69 Sequencer Overall Image Figure SCU Sensor Control Unit 70 shows an example of the process The SEQ ID0 operates periodically according to the timer and the data from the I2C is captured The SEQ ID1 starts up by a certain trigger and captures the data of the LPADC FIFO SEQ ID0 SEQ ID1 HW Resource Sequencer Status startup config generate the bus transactions fetch the external data...

Page 279: ...EQ8 SCU_RAM SEQ9 SCU_RAM MATH_PROC SCU_RAM From SEQ0 9 V0_R_H V0_W_C D0_R0_H D0_R1_C D0_R2_C D0_R3_CH D1_R0_H D1_R1_C D1_R2_C D1_R3_CH N0_R0_H N0_R1_C N1_R0_H N1_R1_C N2_R0_H N2_R1_C N3_R0_H N3_R1_C N4_R0_H N4_R1_C N5_R0_H N5_R1_C N6_R0_H N6_R1_C N7_R0_H N7_R1_C V1_R_H V1_W_C V2_R_H V2_W_C V3_R_H V3_W_C V4_R_H V4_W_C V5_R_H V5_W_C V6_R_H V6_W_C V7_R_H V7_W_C V8_R_H V8_W_C V9_R_H V9_W_C CPU R0_R_CH...

Page 280: ...eceiving an external interrupt as the trigger One operation using an external interrupt as the trigger One operation using the register writing operation as the trigger which is from the CPU The startup intervals by the timer can be selected using the frequency division value of the Pre Divider that determines the startup maximum frequency The operating frequency of each sequencer can be selected ...

Page 281: ...e according to the setting value written on the SCU_RAM The SPI and I2C I2C0 I2C1 access sequencers can be issued by combining the below sequence commands TX_RX command In the case of SPI the selected data is output from the MOSI terminal and up to 8 Bytes of data are simultaneously captured from the MISO terminal In the case of IC2 the selected data is either output to the I2C bus or up to 8 Byte...

Page 282: ...H_PROC or directly from the sensor to the FIFO the data type must be one of the following Calculation Operable Sample Types or Calculation Inoperable Sample Types Other data types cannot be handled Also when the data is written via the MATH_PROC processing the data type of the sensor readout data the data handed to the MATH_PROC must be the Calculation Operable Sample Type Calculation Operable Sam...

Page 283: ...14 15 Firstly Read Data Lastly Read Data XH XL X MSB LSB YH YL Y MSB LSB ZH ZL Z LSB MATH_PROC XH XL X MSB LSB YH YL Y MSB LSB ZH ZL Z LSB FIFO Calculation Operable Sample Type Calculation Operable Sample Type SPI I2C Read Out Buffer Figure SCU Sensor Control Unit 75 Sensor Data Flow when Capturing External Data When the data captured by the SPI I2C LPADC or HPADC is sent through the MATH_PROC tak...

Page 284: ...a Normalization Example When the data is not passed through the MATH_PROC the offset and writing length can be selected for a maximum of 16 Bytes of data that was captured by the SPI I2C LPADC or HPADC The data ultimately written to the FIFO when not passed through the MATH_PROC is written in the readout order from the sensor When passed through the MATH_PROC you can select from 16 bits or 8 bits ...

Page 285: ...age 3 9 9 4 Connectable Sequencers 3 9 9 4 1 I2C The I2C0 and I2C1 can be connected to any sequencer from SEQ0 to SEQ9 See Section 3 9 9 8 for the data flow The I2C execution command must be set beforehand in the parameter SEQ_INSTRUCTION_n n is the instruction number n 0 127 within the SCU_RAM At each sequencer set this instruction number in the parameter SEQ_PROPERTY_n INST_OFST n is the sequenc...

Page 286: ...rom the ADC the resources of the sequencers are not used However the sequencers using the same FIFO numbers cannot be used because the FIFO connected to the sequencers are occupied when the readout data is written However One shot Operation using the sequencer number assigned for ADC readout is possible The LPADC can connect to the following FIFOs D0_W0_S D1_W0_S from N0_W_S to N7_W_S The LPADC ca...

Page 287: ...n When One shot Operation is completed an iSoP0 1 2 interrupt is notified in accordance with the writing region of the SCU_RAM 3 9 9 6 Sequencer Settings The following table shows each resource with its registers and SCU_RAM parameters For the power supplies of the overall SCU and control of clocks make the appropriate settings separately Table SCU Sensor Control Unit 96 Parameters of Sequencer Re...

Page 288: ...ction 3 9 12 11 7 FIFO SCU_RAM FIFO_WRITE_EVENT_CTRL Section 3 9 12 11 11 FIFO_SRAM_POWER_CTRL Section 3 9 12 11 12 ADC SCU_RAM ADC_PROPERTY Section 3 9 12 11 9 HPADC0_ENABLE Section 3 9 12 11 9 HPADC1_ENABLE Section3 9 12 11 9 LPADC_ENABLE Section 3 9 12 11 9 ADC_MATH_PROC_OFST_GAIN Section 3 9 12 11 10 Table SCU Sensor Control Unit 97 Parameters of ADC Resources Sub resource Item Parameter Descr...

Page 289: ...3 9 12 10 117 V6_W_C_CTRL Section 3 9 12 10 123 and 3 9 12 10 124 V7_W_C_CTRL Section 3 9 12 10 130 and 3 9 12 10 131 V8_W_C_CTRL Section 3 9 12 10 137 and 3 9 12 10 138 V9_W_C_CTRL Section 3 9 12 10 144 and 3 9 12 10 145 V0_W_C_TIMESTAMP_SET Section 3 9 12 10 86 and 3 9 12 10 87 V1_W_C_TIMESTAMP_SET Section 3 9 12 10 93 and 3 9 12 10 94 V2_W_C_TIMESTAMP_SET Section 3 9 12 10 100 and 3 9 12 10 101...

Page 290: ...4_R1_C_ALMOST_FULL N5_R1_C_ALMOST_FULL N6_R1_C_ALMOST_FULL N7_R1_C_ALMOST_FULL D0_R3_CH_ALMOST_FULL D1_R3_CH_ALMOST_FULL D0_R1_C_OVER_RUN Section 3 9 12 3 131 D0_R2_C_OVER_RUN D1_R1_C_OVER_RUN D1_R2_C_OVER_RUN N0_R1_C_OVER_RUN N1_R1_C_OVER_RUN N2_R1_C_OVER_RUN N3_R1_C_OVER_RUN N4_R1_C_OVER_RUN N5_R1_C_OVER_RUN N6_R1_C_OVER_RUN N7_R1_C_OVER_RUN D0_R3_CH_OVER_RUN D1_R3_CH_OVER_RUN D0_R1_C_UNDER_RUN ...

Page 291: ...igher sampling frequencies must be assigned to sequencers with higher priority This is because sequencers with higher sampling frequencies require higher precision for time stamps Since an execution flag check is performed for each sequencer number after a task is executed sequencers with lower priority may be executed earlier depending on the execution order of the task Also when a sequence with ...

Page 292: ...der the following conditions These are all controlled from the settings of the CPU SEQ0 or SEQ1 decimation filter is used When any of the following conditions are true 1 Any of the OFST_GAIN_EN in the OFST_GAIN_EN 0x5070 of the MATHID within the SCU_REG is set to 1 2 Any from among MATHF_EN0 MAYHF_EN1 and MATHF_EN2 in the MATHFUNC_SEL 0x508c of the MATHID within the SCU_REG is set 3 Any from among...

Page 293: ...er and the SCU hardware parameters can only be re written when their corresponding functions are not operating Refer to Section 3 9 12 for information on which registers can be written or not during operation of functions For the parameters within the SCU_RAM refer to Section 3 9 12 11 For the CPU to recognize whether the operation of a sequencer has completely finished or whether the operation ha...

Page 294: ... status is suspended Figure SCU Sensor Control Unit 80 Sequencer Suspended 3 9 9 12 1 Completion Judgement The following events notify the CPU of the completion of operations The ADC has been completed One of the SEQ0 to SEQ9 has been completed The CPU requests the completion of operations to each sequencer Multiple complete requests are not issued simultaneously therefore each judgement of sequen...

Page 295: ...to the FIFO The following describes an example of changing setting of MATH_PROC by using this suspension judgement SEQ MATH_PROC Processing Process ing START_CTRL interrupt HPADC0_ACCESS _INHIBIT_REQ Process ing CPU 1 2 3 4 5 CPU can change the configuration of MATH_PROC in this period Processing Processing HPADC1_ACCESS _INHIBIT_REQ SYNCHRO_CPU2iSoP 1 interrupt 6 Figure SCU Sensor Control Unit 81...

Page 296: ...lected The interrupt requests are controlled from the SEQ_ACCESS_INHIBIT_REQ register refer to Section 3 9 12 3 4 within the SCU_REG However regarding the LPADC_ACCESS_INHIBIT_REQ the conventional INHIBIT request function related operations do not function during INHIBIT requests of the LPADC has been removed from the register When you need to use the LPADC not being under the CPU s control set LP...

Page 297: ... from the SCU The setting of the MATH_PROC cannot be re written until the MATH_PROC is executed with the given settings at least once SEQ MATH_PROC Processing Process ing START_CTRL interrupt HPADC0_ACCESS _INHIBIT_REQ Process ing CPU 1 2 3 4 5 Processing Processing HPADC1_ACCESS _INHIBIT_REQ SYNCHRO_CPU2iSoP 1 interrupt Processing Processing SYNCHRO_iSoP2CPU 6 Figure SCU Sensor Control Unit 82 Er...

Page 298: ...r SLEEP unless you set the HPADC0_ACCESS_INHIBIT_REQ register back to 0 SLEEP Inhibition SLEEP can be inhibited by setting the HPADC0_ACCESS_INHIBIT_REQ register within the SCU_REG to 1 3 9 9 14 Manual Mode The SCU assumes the reduction of CPU load using the sequencers but you can also choose not to use sequencers In such case the CPU will set all accessible control registers as appropriate to rea...

Page 299: ...SCU Sensor Control Unit 101 DMA Handshake Signals and Connection Destination DMAC ch IDs DMA Request Factor Connection Destination DMAC ch ID DMA Request Factor Connection Destination DMAC ch ID SPI M Tx ch0 FIFO Rx D0_R1_C ch12 SPI M Rx ch1 FIFO Rx D0_R2_C ch13 I2C0 M Tx ch2 FIFO Rx D0_R3_CH ch14 I2C0 M Rx ch3 FIFO Rx D1_R1_C ch15 I2C1 M Tx ch4 FIFO Rx D1_R2_C ch16 I2C1 M Rx ch5 FIFO Rx D1_R3_CH ...

Page 300: ...32768 the cycle and output H width are freely selectable within this range Function for synchronization with ADC The PWM can be output using the data fix signal of any ADC channel as a reference ADC data can be captured after a specified duration from the rising edge of the PWM output Synchronization function between PWM channels The PWM output can be synchronized between arbitrary PWM channels in...

Page 301: ...field 15 8 sets the capture start position from 3 to 255 PWM_PASExx register PWM_CNTENn field 7 4 sets the number of captures from 1 to 15 PWM_PASEn register PWM_CNTENn field 3 0 sets the frequency division of the prescaler PWM_FUCN2 register PWM_SEL_DISm field selects the PWM channels used for combining PWM_FUNCSEL0 register PWM_SEL_INVm field selects whether or not to invert the PWM polarity PWM...

Page 302: ...alculation Formula PWM cycle UPWM_CYCLE SCU_CLK PWM_CNTENn When prescaler is set to 1 1 PWM_CNTENn 0 UPWM_CYCLE PWMn_CYCLE 1 Restriction PWMn_CYCLE 0 When prescaler is set to 1 2 or higher PWM_CNTENn 1 UPWM_CYCLE PWMn_CYCLE Restriction PWMn_CYCLE 1 3 9 11 2 2 PWM Output Duty High time cycle Calculation Formula DUTY 1 UPWM_THRESH UPWM_CYCLE When prescaler is set to 1 1 PWM_CNTENn 0 UPWM_CYCLE PWMn_...

Page 303: ...om the ADC LPADC HPADC as a reference The following is an overview AD_EN Internal Triangular signal PWM output A D Sampling Timing PWM start phase is controllable PWM period is controllable Start Phase is adjusted when the 1st AD_EN rising after updating register setting Figure SCU Sensor Control Unit 84 PWM Output Mode using ADC Timing as a Reference When setting the PWM channel n n 0 7 set the f...

Page 304: ..._A0 LV_ADC_EN Note The data strobe signal connected to the PWM cannot be controlled by the HPADC0_D2 DECIFIFO_EN HPADC1_D2 DECI FIFO_EN LPADC_D2 FIFO_EN The ADC channels used as the reference can be selected as follows Table SCU Sensor Control Unit 103 Reference ADC Channel Selection PWM_SELLn 2 0 AD Selection 0 Does not synchronize with ADC free run mode 1 Synchronizes with HPADC0 2 Synchronizes ...

Page 305: ...0_EN 0x0000000x Selection of ADC synchronization source 0x1 EN PWM0_UPDATE 0x00000001 3 PWM suspend settings PWM0_EN 0x00000000 PWM0_UPDATE 0x00000001 4 ADC Sampling Start same as 2 ADC_EN ON 5 PWM Start Settings from 2nd time on PWM_PASE0 0x0000ffff PWM0_PARAM 0x00070007 PWM0_EN 0x0000000x Selection of ADC synchronization source 0x1 EN PWM0_UPDATE 0x00000001 PWM_PASE0 0x00000001 3 9 11 4 Function...

Page 306: ...ce PWM_SELLn field 5 3 fixed to 0 Enable control of this synchronization function is controlled by the PWMn_EN field of the PWMn_EN register and synchronization operation starts by using the Writing to the PWMn_UPDATE register as a trigger The following is an example of the basic settings 1 Setting of the PWM to which data capture timing of the ADC is synchronized HPADC0_D1 DECI_RATIO2 HPADC1_D1 D...

Page 307: ...els It is also possible to operate multiple PWMs in a chain sequence When setting the PWM channel n n 0 7 set the following registers in addition to the basic operation settings PWMn_EN register PWM_SELLn field 5 3 sets channel m of the PWM you want to synchronize PWM_PASEn register PWM_DELAYn field selects the number of clocks for phase adjustment After making the settings perform the additional ...

Page 308: ...0 2 PWM2 PWM2 PWM1 PWM1 PWM1 PWM1 PWM1 PWM1 3 PWM3 PWM3 PWM3 PWM2 PWM2 PWM2 PWM2 PWM2 4 PWM4 PWM4 PWM4 PWM4 PWM3 PWM3 PWM3 PWM3 5 PWM5 PWM5 PWM5 PWM5 PWM5 PWM4 PWM4 PWM4 6 PWM6 PWM6 PWM6 PWM6 PWM6 PWM6 PWM5 PWM5 7 PWM7 PWM7 PWM7 PWM7 PWM7 PWM7 PWM7 PWM6 3 9 11 5 1 PWM Output Phase Calculation Formula When prescaler is set to 1 1 Phase difference number of SCU_CLOCK PWM_DELAYn 1 When prescaler is s...

Page 309: ...e internal PWM signal the waveform output from the external PWM terminal can be combined AND or OR can be used for the combining Setting example Terminal PWM0ch PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 Terminal PWM1ch PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 When setting the output terminal PWMm m 0 3 set the following registers in addition to the basic operation settings PWM_FUCN2 register PWM_SEL_...

Page 310: ...ut Regarding the PWM_SEL_INVm the PWM channels corresponding to each bit are inverted by 1 When performing OR combining by the PWM_SELm field setting disable the channels that are not used by PWM_SEL_DISm and then also make an invert setting for PWM_SEL_INVm input 0 at the OR combining stage Note that at the reset initial state these registers are All 0 and the output terminal PWMm m 0 3 is in a s...

Page 311: ...ata Ram Array 3 9 12 3 SCU_REG Register List Note Some offset addresses are listed irregularly Be careful when you set address by calculating with the SW The Reserved regions are secured in the 0x50AC to 0x50AF and 0x50C0 to 0x50CF offset addresses shown in the following list Table SCU Sensor Control Unit 108 SCU Register List Offset Address Transaction Port Name Type Size bit Description Reset Va...

Page 312: ...000000 0x5038 START_INTERVAL7_4 RW 32 0x00000000 0x503C START_INTERVAL9_8 RW 32 0x00000000 0x5040 START_PHASE1_0 RW 32 0x00000000 0x5044 START_PHASE3_2 RW 32 0x00000000 0x5048 START_PHASE5_4 RW 32 0x00000000 0x504C START_PHASE7_6 RW 32 0x00000000 0x5050 START_PHASE9_8 RW 32 0x00000000 0x5054 SINGLE_EXE RW 32 0x00000000 0x5058 START_CTRL_STT0 RO 32 0x00000000 0x505C START_CTRL_STT1 RO 32 0x00000000...

Page 313: ... 0x00000000 0x50A8 MATHFUNC_PARAM_C0_0_ 0_LSB RW 32 0x00000000 0x50AC to 0x50AF Reserved Reserved 0x50B0 MATHFUNC_PARAM_C1_0_ 0_MSB RW 32 0x00000000 0x50B4 MATHFUNC_PARAM_C1_0_ 0_LSB RW 32 0x00000000 0x50B8 MATHFUNC_PARAM_C2_0_ 0_MSB RW 32 0x00000000 0x50BC MATHFUNC_PARAM_C2_0_ 0_LSB RW 32 0x00000000 0x50C0 to 0x50CF Reserved Reserved 0x50D0 MATHFUNC_PARAM_C3_0_ 0_MSB RW 32 0x00000000 0x50D4 MATHF...

Page 314: ...SB RW 32 0x00000000 0x5100 MATHFUNC_PARAM_C3_0_ 1_LSB RW 32 0x00000000 0x5104 MATHFUNC_PARAM_C4_0_ 1_MSB RW 32 0x00000000 0x5108 MATHFUNC_PARAM_C4_0_ 1_LSB RW 32 0x00000000 0x510C MATHFUNC_PARAM_1_0 RW 32 0x00000000 0x5110 MATHFUNC_PARAM_C0_1_ 0_MSB RW 32 0x00000000 0x5114 MATHFUNC_PARAM_C0_1_ 0_LSB RW 32 0x00000000 0x5118 MATHFUNC_PARAM_C1_1_ 0_MSB RW 32 0x00000000 0x511C MATHFUNC_PARAM_C1_1_ 0_L...

Page 315: ...SB RW 32 0x00000000 0x5150 MATHFUNC_PARAM_C2_1_ 1_LSB RW 32 0x00000000 0x5154 MATHFUNC_PARAM_C3_1_ 1_MSB RW 32 0x00000000 0x5158 MATHFUNC_PARAM_C3_1_ 1_LSB RW 32 0x00000000 0x515C MATHFUNC_PARAM_C4_1_ 1_MSB RW 32 0x00000000 0x5160 MATHFUNC_PARAM_C4_1_ 1_LSB RW 32 0x00000000 0x5164 MATHFUNC_PARAM_2_0 RW 32 0x00000000 0x5168 MATHFUNC_PARAM_C0_2_ 0_MSB RW 32 0x00000000 0x516C MATHFUNC_PARAM_C0_2_ 0_L...

Page 316: ... 32 0x00000000 0x51A4 MATHFUNC_PARAM_C2_2_ 1_MSB RW 32 0x00000000 0x51A8 MATHFUNC_PARAM_C2_2_ 1_LSB RW 32 0x00000000 0x51AC MATHFUNC_PARAM_C3_2_ 1_MSB RW 32 0x00000000 0x51B0 MATHFUNC_PARAM_C3_2_ 1_LSB RW 32 0x00000000 0x51B4 MATHFUNC_PARAM_C4_2_ 1_MSB RW 32 0x00000000 0x51B8 MATHFUNC_PARAM_C4_2_ 1_LSB RW 32 0x00000000 0x51BC EVENT_PARAM0_THRESH RW 32 0x00000000 0x51C0 EVENT_PARAM0_COUNT0 RW 32 0x...

Page 317: ... 32 0x00000000 0x5208 EVENT_TIMESTAMP1_R_M SB RO 32 0x00000000 0x520C EVENT_TIMESTAMP1_R_LS B RO 32 0x00000000 0x5210 EVENT_TIMESTAMP2_R_M SB RO 32 0x00000000 0x5214 EVENT_TIMESTAMP2_R_LS B RO 32 0x00000000 0x5218 EVENT_TIMESTAMP0_F_M SB RO 32 0x00000000 0x521C EVENT_TIMESTAMP0_F_LS B RO 32 0x00000000 0x5220 EVENT_TIMESTAMP1_F_M SB RO 32 0x00000000 0x5224 EVENT_TIMESTAMP1_F_LS B RO 32 0x00000000 0...

Page 318: ...5460 INT_ENABLE_ERR_2 RW 32 0x00000000 0x5464 INT_DISABLE_ERR_2 RW 32 0x00000000 0x5468 INT_CLEAR_ERR_2 WO 32 0x00000000 0x546C INT_RAW_STT_ERR_2 RO 32 0x00000000 0x5470 INT_MASKED_STT_ERR_2 RO 32 0x00000000 0x5500 RAM_TEST RW 32 0x00000000 0x5510 SCU_POWER RO 32 Clock status controlled by the SCU internal sequencer 0 CK_SCU 1 CK_SCU_SPI 2 CK_SCU_I2C0 3 CK_SCU_I2C1 0x00000000 0x5520 INT_ENABLE_MAI...

Page 319: ...000 0x564C PWM5_PARAM RW 32 0x00000000 0x5650 PWM5_EN RW 32 0x00000000 0x5654 PWM5_UPDATE RW 32 0x00000000 0x5658 PWM6_PARAM RW 32 0x00000000 0x565C PWM6_EN RW 32 0x00000000 0x5660 PWM6_UPDATE RW 32 0x00000000 0x5664 PWM7_PARAM RW 32 0x00000000 0x5668 PWM7_EN RW 32 0x00000000 0x566C PWM7_UPDATE RW 32 0x00000000 0x5670 PWM_PASE4 RW 32 0x00000000 0x5674 PWM_PASE5 RW 32 0x00000000 0x5678 PWM_PASE6 RW...

Page 320: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FSM Reserved SDA SCL Bits Name Type Reset Value Description 31 13 Reserved RO 0x00000 Reserved 12 8 FSM RO 0x00 The internal status of the IP for I2C0 can be monitored 7 2 Reserved RO 0x00 Reserved 1 SDA RO 0x0 Input status of the signal in the SDA of the IP for I2C0 can be monitored 0 SCL RO 0x0 Input status of the signal in the SCL of...

Page 321: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FSM Reserved SDA SCL Bits Name Type Reset Value Description 31 13 Reserved RO 0x00000 Reserved 12 8 FSM RO 0x00 The internal status of the IP for I2C1 can be monitored 7 2 Reserved RO 0x00 Reserved 1 SDA RO 0x0 Input status of the signal in the SDA of the IP for I2C1 can be monitored 0 SCL RO 0x0 Input status of the signal in the SCL of the IP for I2C1...

Page 322: ...ssion of each sequence Table SCU Sensor Control Unit 111 Local Address 0x5020 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENABLE_READY ENABLE_ALL_SEQ Bits Name Type Reset Value Description 31 2 Reserved RO 0x00000000 Reserved 1 ENABLE_READY RO 0x0 Indicates that the sequence operation is ready Wri...

Page 323: ...S_INHIBIT_ACK LPADC_ACCESS_INHIBIT_ACK I2C1_ACCESS_INHIBIT_ACK I2C0_ACCESS_INHIBIT_ACK SPI_ACCESS_INHIBIT_ACK Reserved HPADC1_ACCESS_INHIBIT_REQ HPADC0_ACCESS_INHIBIT_REQ LPADC_ACCESS_INHIBIT_REQ I2C1_ACCESS_INHIBIT_REQ I2C0_ACCESS_INHIBIT_REQ SPI_ACCESS_INHIBIT_REQ Bits Name Type Reset Value Description 31 20 Reserved RO 0x000 Reserved 19 LPADC_ACCESS_I NHIBIT_ACK3 RO 0x0 18 LPADC_ACCESS_I NHIBIT...

Page 324: ...it becomes 1 7 6 Reserved RO 0x0 Reserved 5 HPADC1_ACCESS_ INHIBIT_REQ RW 0x0 When the sequencer is requested to be suspended Suspend interrupt is requested and canceled to the internal sequencer 1 is set when the sequencer is requested to be suspended 0 is set in the interrupt context Refer to Section 3 9 9 12 3 4 HPADC0_ACCESS_ INHIBIT_REQ RW 0x0 When the sequencer is requested to be completed o...

Page 325: ... RW 0x0 When the CPU directly accesses I2C0 1 is set on this bit SEQ_CTRL holds the access to I2C0 while the bit is 1 Note that if this bit is set 1 for longer time than the sequencer s access cycle using I2C0 from SEQ_CTRL the bit of EXE_ERR_STT will become 1 0 SPI_ACCESS_INHI BIT_REQ RW 0x0 When the CPU directly accesses SPI 1 is set on this bit SEQ_CTRL holds the access to SPI while the bit is ...

Page 326: ...RE_DIVIDER RW 0xFF Maximum frequency setting for starting data capturing common to all sequencers 32 768 kHz PRE_DIVIDER 1 is the maximum frequency for data capturing common to all sequencers For example if you have a sensor which must sample at maximum 1 kHz the frequency is 32 768 31 1 1024 and the value of PRE_DIVIDER is 31 For the sensor s maximum sampling ability refer to the Chapter of ADC 3...

Page 327: ...ed when ENABLE_ALL is prohibited the operation will not start 8 START_ENABLE8 RW 0x0 This designates permission prohibition of the Sequencer 8 s operation Even if the operation is permitted when ENABLE_ALL is prohibited the operation will not start 7 START_ENABLE7 RW 0x0 This designates permission prohibition of the Sequencer 7 s operation Even if the operation is permitted when ENABLE_ALL is proh...

Page 328: ...ration will not start 2 START_ENABLE2 RW 0x0 This designates permission prohibition of the Sequencer 2 s operation Even if the operation is permitted when ENABLE_ALL is prohibited the operation will not start 1 START_ENABLE1 RW 0x0 This designates permission prohibition of the Sequencer 1 s operation Even if the operation is permitted when ENABLE_ALL is prohibited the operation will not start 0 ST...

Page 329: ...o START_MODE9 15 14 START_MODE7 RW 0x0 This designates the Sequencer 7 s starting mode For the control specifications refer to START_MODE9 13 12 START_MODE6 RW 0x0 This designates the Sequencer 6 s starting mode For the control specifications refer to START_MODE9 11 10 START_MODE5 RW 0x0 This designates the Sequencer 5 s starting mode For the control specifications refer to START_MODE9 9 8 START_M...

Page 330: ...ency division value The value range that can be set to SEQ_INTERVAL3 is from 0 to 9 When using a One shot Sequencer corresponding to the register 0xA must be set 23 20 Reserved RO 0x0 Reserved 19 16 START_IN TERVAL2 RW 0x0 This designates Sequencer 2 s timer operating frequency division value When SEQ_MODE is 0 or 1 this set value is referred As for the calculating formula of the operating frequen...

Page 331: ...rved START_INTERVAL6 Reserved START_INTERVAL5 Reserved START_INTERVAL4 Bits Name Type Reset Value Description 31 28 Reserved RO 0x0 Reserved 27 24 START_IN TERVAL7 RW 0x0 This designates Sequencer 7 s timer operating frequency division value When SEQ_MODE7 is 0 or 1 this set value is referred As for the calculating formula of the operating frequency the range of values that can be set and set valu...

Page 332: ...ues that can be set and set values when using the One shot Sequencer refer to START_INTERVAL3 3 9 12 3 10 0x503C START_INTERVAL9_8 Details Table SCU Sensor Control Unit 118 Local Address 0x503C Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved START_INTERVAL9 Reserved START_INTERVAL8 Bits Name Type Rese...

Page 333: ... Sequencer 8 s timer operating frequency division value When SEQ_MODE8 is 0 or 1 this set value is referred As for the calculating formula of the operating frequency the range of values that can be set and set values when using the One shot Sequencer refer to START_INTERVAL3 ...

Page 334: ...ved RO 0x00 Reserved 24 16 START_PHASE1 RW 0x000 This designates Sequencer 1 s timer startup phase When SEQ_MODE1 is 0 or 1 this set value is referred When the value of the internal counter SEQ_INTERVAL1 corresponds to SEQ_PHASE1 a request to start sequencer operation occurs 15 9 Reserved RO 0x00 Reserved 8 0 START_PHASE0 RW 0x000 This designates Sequencer 0 s timer startup phase When SEQ_MODE0 is...

Page 335: ...ed RO 0x00 Reserved 24 16 START_PH ASE3 RW 0x000 This designates Sequencer 3 s timer startup phase When SEQ_MODE3 is 0 or 1 this set value is referred When the value of the internal counter SEQ_INTERVAL3 corresponds to SEQ_PHASE3 a request to start sequencer operation occurs 15 9 Reserved RO 0x00 Reserved 8 0 START_PH ASE2 RW 0x000 This designates Sequencer 2 s timer startup phase When SEQ_MODE2 i...

Page 336: ...ed RO 0x00 Reserved 24 16 START_PH ASE5 RW 0x000 This designates Sequencer 5 s timer startup phase When SEQ_MODE5 is 0 or 1 this set value is referred When the value of the internal counter SEQ_INTERVAL5 corresponds to SEQ_PHASE5 a request to start sequencer operation occurs 15 9 Reserved RO 0x00 Reserved 8 0 START_PH ASE4 RW 0x000 This designates Sequencer 4 s timer startup phase When SEQ_MODE4 i...

Page 337: ...ed RO 0x00 Reserved 24 16 START_PH ASE7 RW 0x000 This designates Sequencer 7 s timer startup phase When SEQ_MODE7 is 0 or 1 this set value is referred When the value of the internal counter SEQ_INTERVAL7 corresponds to SEQ_PHASE7 a request to start sequencer operation occurs 15 9 Reserved RO 0x00 Reserved 8 0 START_PH ASE6 RW 0x000 This designates Sequencer 6 s timer startup phase When SEQ_MODE1 i...

Page 338: ...ed RO 0x00 Reserved 24 16 START_P HASE9 RW 0x000 This designates Sequencer 9 s timer startup phase When SEQ_MODE9 is 0 or 1 this set value is referred When the value of the internal counter SEQ_INTERVAL9 corresponds to SEQ_PHASE9 a request to start sequencer operation occurs 15 9 Reserved RO 0x00 Reserved 8 0 START_P HASE8 RW 0x000 This designates Sequencer 8 s timer startup phase When SEQ_MODE8 i...

Page 339: ...O 0x0 By writing 1 Sequencer 8 s execution request is issued only once When the corresponding START_ENABLE bit is 0 this register is not active When SEQ_MODE8 is 2 or 3 this set value is referred 7 REQ7 WO 0x0 By writing 1 Sequencer 7 s execution request is issued only once When the corresponding START_ENABLE bit is 0 this register is not active When SEQ_MODE7 is 2 or 3 this set value is referred ...

Page 340: ... the corresponding START_ENABLE bit is 0 this register is not active When SEQ_MODE1 is 2 or 3 this set value is referred 0 REQ0 WO 0x0 By writing 1 Sequencer 0 s execution request is issued only once When the corresponding START_ENABLE bit is 0 this register is not active When SEQ_MODE0 is 2 or 3 this set value is referred 3 9 12 3 17 0x5058 START_CTRL_STT0 Details Table SCU Sensor Control Unit 12...

Page 341: ...ates the request status of the sequencers 1 request issued or request in processing bit 16 Sequencer 0 bit 17 Sequencer 1 bit 18 Sequencer 2 bit 19 Sequencer 3 bit 20 Sequencer 4 bit 21 Sequencer 5 bit 22 Sequencer 6 bit 23 Sequencer 7 bit 24 Sequencer 8 bit 25 Sequencer 9 15 Reserved RO 0x0 Reserved 14 0 TIME_STAMP_LS B RO 0x0000 The execution request value at the time of being read out can be re...

Page 342: ...ed MONSEL Reserved EXT_INT_REQ_DBG_EN DONE_REQ_DBG_EN Bits Name Type Reset Value Description 31 EXT_INT_REQ WO 0x0 This forces an external interrupt to occur from the CPU 30 26 Reserved RO 0x00 Reserved 25 16 DONE_REQ WO 0x000 This forces an execution completed to occur from the CPU 15 12 Reserved RO 0x0 Reserved 11 8 MONSEL RW 0x0 Selecting monitor output signals 7 2 Reserved RO 0x00 Reserved 1 E...

Page 343: ...equencer 8 If 0 is designated the value of OFST_GAIN8 is ignored 13 OFST_GAIN_ EN13 RW 0x0 Designate 1 to perform offset addition processing and gain multiplication processing for MATH_PROC of Sequencer 7 If 0 is designated the value of OFST_GAIN7 is ignored 12 OFST_GAIN_ EN12 RW 0x0 Designate 1 to perform offset addition processing and gain multiplication processing for MATH_PROC of Sequencer 6 I...

Page 344: ...ved RO 0x0 Reserved 4 OFST_GAIN_ EN4 RW 0x0 Designate 1 to perform offset addition processing and gain multiplication processing for MATH_PROC of Sequencer 1 If 0 is designated the value of OFST_GAIN1 is ignored 3 1 Reserved RO 0x0 Reserved 0 OFST_GAIN_ EN0 RW 0x0 Designate 1 to perform offset addition processing and gain multiplication processing for MATH_PROC of Sequencer 0 If 0 is designated th...

Page 345: ...st be regarded as offset binary and converted into two s complement format The offset binary format s offset is maximum value of input value binary 1 2 When 0 is designated code conversion is not performed 14 UNSIGNED_TO _SIGNED14 RW 0x0 This controls processing of Sequencer 8 As for specifications refer to UNSIGNED_TO_SIGNED15 13 UNSIGNED_TO _SIGNED13 RW 0x0 This controls processing of Sequencer ...

Page 346: ...r to UNSIGNED_TO_SIGNED15 7 5 Reserved RO 0x0 Reserved 4 UNSIGNED_TO _SIGNED4 RW 0x0 This controls processing of Sequencer 1 As for specifications refer to UNSIGNED_TO_SIGNED15 3 1 Reserved RO 0x0 Reserved 0 UNSIGNED_TO _SIGNED0 RW 0x0 This controls processing of Sequencer 0 As for specifications refer to UNSIGNED_TO_SIGNED15 ...

Page 347: ..._N2_CLR WO 0x0 DEC1 synchronous reset to FF in the differentiating circuit for N2 6 DEC1_N1_CLR WO 0x0 DEC1 synchronous reset to FF in the differentiating circuit for N1 5 DEC1_N0_CLR WO 0x0 DEC1 synchronous reset to FF in the differentiating circuit for N0 4 DEC1_COMMON_CLR WO 0x0 DEC1 synchronous reset 3 DEC0_N2_CLR WO 0x0 DEC0 synchronous reset to FF in the differentiating circuit for N2 2 DEC0...

Page 348: ...ed WO 0x00000000 Reserved 2 MATHFUNC2_CLR WO 0x0 MATHFUNC2 synchronous reset 1 MATHFUNC1_CLR WO 0x0 MATHFUNC1 synchronous reset 0 MATHFUNC0_CLR WO 0x0 MATHFUNC0 synchronous reset 3 9 12 3 24 0x5080 EVENT_STT Details Table SCU Sensor Control Unit 132 Local Address 0x5080 Register Type WO write only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 349: ...0x0 Reserved 29 28 LEVEL_ADJ_3 RW 0x0 Level adjust value setting with clipping for D0_W3_S 0 once 1 twice 2 four times 3 eight times 27 24 N3 RW 0x0 Decimation ratio for D0_W3_S 0 to 9 Frequency is divided by 1 2 n using n as a designated value 10 to 15 Decimation is not performed and data are not output 23 FORCE_THROU GH2 RW 0x0 When 1 is set input data is forced to output directly regardless of ...

Page 350: ..._W1_S As for specifications refer to LEVEL_ADJ_3 11 8 N1 RW 0x0 Decimation ratio for D0_W1_S As for specifications refer to N3 7 6 Reserved RO 0x0 Reserved 5 4 LEVEL_ADJ_0 RW 0x0 Level adjust value setting with clipping for D0_W0_S As for specifications refer to LEVEL_ADJ_3 3 0 Reserved RO 0x0 Reserved ...

Page 351: ...0 Reserved RO 0x0 Reserved 29 28 LEVEL_ADJ_7 RW 0x0 Level adjust value setting with clipping for D1_W3_S 0 once 1 twice 2 four times 3 eight times 27 24 N7 RW 0x0 Decimation ratio for D1_W3_S 0 to 9 Frequency is divided by 1 2 n using n as a designated value 10 to 15 Decimation is not performed and data are not output 23 FORCE_THROUG H6 RW 0x0 When 1 is set input data is forced to output directly ...

Page 352: ...lipping for D1_W1_S As for specifications refer to LEVEL_ADJ_7 11 8 N5 RW 0x0 Decimation ratio for D1_W1_S As for specifications refer to N7 7 6 Reserved RO 0x0 Reserved 5 4 LEVEL_ADJ_4 RW 0x0 Level adjust value setting with clipping for D1_W0_S As for specifications refer to LEVEL_ADJ_7 3 0 Reserved RO 0x0 Reserved ...

Page 353: ...ATHF_EN2 WID2 Reserved MATHF_EN1 WID1 Reserved MATHF_EN0 WID0 Bits Name Type Reset Value Description 31 21 Reserved RO 0x000 Reserved 20 MATHF_EN2 RW 0x0 Operation permission of Math Function 2 19 16 WID2 RW 0x0 FIFO Partition ID setting value allocated to Math Function 2 0 to 15 15 13 Reserved RO 0x0 Reserved 12 MATHF_EN1 RW 0x0 Operation permission of Math Function 1 11 8 WID1 RW 0x0 FIFO Partit...

Page 354: ... side IIR0 insertion IIR on the right side IIR1 The positions where IIRs are inserted are as follows 4 b0001 1 2 4 b0011 1 3 4 b0101 1 5 4 b1001 1 7 4 b0010 3 4 4 b0110 3 5 4 b1010 3 7 4 b0100 5 6 4 b1100 5 7 4 b1001 7 8 Table SCU Sensor Control Unit 136 Local Address 0x5090 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6...

Page 355: ...served POS_1 Bits Name Type Reset Value Description 31 4 Reserved RO 0x0000000 Reserved 3 0 POS_1 RW 0x0 This designates the position where the IIR of Math Function 1 is inserted 3 9 12 3 30 0x5098 MATHFUNC_POS2 Details As for the positions where the IIRs are inserted refer to Section 3 9 12 3 28 0x5090 MATHFUNC_POS0 Table SCU Sensor Control Unit 138 Local Address 0x5098 Register Type RW read writ...

Page 356: ...e RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved S2 Reserved S1 Bits Name Type Reset Value Description 31 11 Reserved RO 0x000000 Reserved 10 8 S2 RW 0x0 The IIR parameter for Math Function 0 3 bit shift at IIR0 outlet port Changing the setting value is prohibited during operation 7 3 Reserved RO 0x00 Reserved 2 0...

Page 357: ...REG C0 Coefficient value format s2 31 Changing the setting value is prohibited during operation 3 9 12 3 33 0x50A8 MATHFUNC_PARAM_C0_0_0_LSB Details The IIR Parameter for Math Function 0 Table SCU Sensor Control Unit 141 Local Address 0x50A8 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C0 Reserved Bits Name...

Page 358: ...REG C1 Coefficient value format s2 31 Changing the setting value is prohibited during operation 3 9 12 3 35 0x50B4 MATHFUNC_PARAM_C1_0_0_LSB Details The IIR Parameter for Math Function 0 Table SCU Sensor Control Unit 143 Local Address 0x50B4 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1 Reserved Bits Name...

Page 359: ...REG C2 Coefficient value format s2 31 Changing the setting value is prohibited during operation 3 9 12 3 37 0x50BC MATHFUNC_PARAM_C2_0_0_LSB Details The IIR Parameter for Math Function 0 Table SCU Sensor Control Unit 145 Local Address 0x50BC Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C2 Reserved Bits Name...

Page 360: ...REG C3 Coefficient value format s2 31 Changing the setting value is prohibited during operation 3 9 12 3 39 0x50D4 MATHFUNC_PARAM_C3_0_0_LSB Details The IIR Parameter for Math Function 0 Table SCU Sensor Control Unit 147 Local Address 0x50D4 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3 Reserved Bits Name...

Page 361: ...REG C4 Coefficient value format s2 31 Changing the setting value is prohibited during operation 3 9 12 3 41 0x50DC MATHFUNC_PARAM_C4_0_0_LSB Details The IIR Parameter for Math Function 0 Table SCU Sensor Control Unit 149 Local Address 0x50DC Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C4 Reserved Bits Name...

Page 362: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved S2 Reserved S1 Bits Name Type Reset Value Description 31 11 Reserved RO 0x000000 Reserved 10 8 S2 RW 0x0 The IIR parameter for Math Function 0 3 bit shift at IIR1 outlet port Changing the setting value is prohibited during operation 7 3 Reserved RO 0x00 Reserved 2 0 S1 RW 0x0 The IIR parameter for Math Function 0 3 bit shift at IIR1 outlet po...

Page 363: ...REG C0 Coefficient value format s2 31 Changing the setting value is prohibited during operation 3 9 12 3 44 0x50E8 MATHFUNC_PARAM_C0_0_1_LSB Details The IIR Parameter for Math Function 0 Table SCU Sensor Control Unit 152 Local Address 0x50E8 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C0 Reserved Bits Name...

Page 364: ...REG C1 Coefficient value format s2 31 Changing the setting value is prohibited during operation 3 9 12 3 46 0x50F0 MATHFUNC_PARAM_C1_0_1_LSB Details The IIR Parameter for Math Function 0 Table SCU Sensor Control Unit 154 Local Address 0x50F0 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1 Reserved Bits Name...

Page 365: ...REG C2 Coefficient value format s2 31 Changing the setting value is prohibited during operation 3 9 12 3 48 0x50F8 MATHFUNC_PARAM_C2_0_1_LSB Details The IIR Parameter for Math Function 0 Table SCU Sensor Control Unit 156 Local Address 0x50F8 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C2 Reserved Bits Name...

Page 366: ...REG C3 Coefficient value format s2 31 Changing the setting value is prohibited during operation 3 9 12 3 50 0x5100 MATHFUNC_PARAM_C3_0_1_LSB Details The IIR Parameter for Math Function 0 Table SCU Sensor Control Unit 158 Local Address 0x5100 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3 Reserved Bits Name...

Page 367: ...REG C4 Coefficient value format s2 31 Changing the setting value is prohibited during operation 3 9 12 3 52 0x5108 MATHFUNC_PARAM_C4_0_1_LSB Details The IIR Parameter for Math Function 0 Table SCU Sensor Control Unit 160 Local Address 0x5108 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C4 Reserved Bits Name...

Page 368: ...ils Table SCU Sensor Control Unit 161 Local Address 0x510C Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved S2 Reserved S1 Bits Name Type Reset Value Description 31 11 Reserved RO 0x000000 Reserved 10 8 S2 RW 0x0 7 3 Reserved RO 0x00 Reserved 2 0 S1 RW 0x0 ...

Page 369: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C0 Bits Name Type Reset Value Description 31 0 C0 RW 0x00000000 3 9 12 3 55 0x5114 MATHFUNC_PARAM_C0_1_0_LSB Details The IIR Parameter for Math Function 1 Refer to 0x50A8 MATHFUNC_PARAM_C0_0_0_LSB Details Table SCU Sensor Control Unit 163 Local Address 0x5114 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 370: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1 Bits Name Type Reset Value Description 31 0 C1 RW 0x00000000 3 9 12 3 57 0x511C MATHFUNC_PARAM_C1_1_0_LSB Details The IIR Parameter for Math Function 1 Refer to 0x50B4 MATHFUNC_PARAM_C1_0_0_LSB Details Table SCU Sensor Control Unit 165 Local Address 0x511C Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 371: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C2 Bits Name Type Reset Value Description 31 0 C2 RW 0x00000000 3 9 12 3 59 0x5124 MATHFUNC_PARAM_C2_1_0_LSB Details The IIR Parameter for Math Function 1 Refer to 0x50BC MATHFUNC_PARAM_C2_0_0_LSB Details Table SCU Sensor Control Unit 167 Local Address 0x5124 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 372: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3 Bits Name Type Reset Value Description 31 0 C3 RW 0x00000000 3 9 12 3 61 0x512C MATHFUNC_PARAM_C3_1_0_LSB Details The IIR Parameter for Math Function 1 Refer to 0x50D4 MATHFUNC_PARAM_C3_0_0_LSB Details Table SCU Sensor Control Unit 169 Local Address 0x512C Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 373: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C4 Bits Name Type Reset Value Description 31 0 C4 RW 0x00000000 3 9 12 3 63 0x5134 MATHFUNC_PARAM_C4_1_0_LSB Details The IIR Parameter for Math Function 1 Refer to 0x50DC MATHFUNC_PARAM_C4_0_0_LSB Details_ 0x50DC _MATHFUNC_PARAM_C4_0_0_LSB_ Table SCU Sensor Control Unit 171 Local Address 0x5134 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 2...

Page 374: ...ils Table SCU Sensor Control Unit 172 Local Address 0x5138 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved S2 Reserved S1 Bits Name Type Reset Value Description 31 11 Reserved RO 0x000000 Reserved 10 8 S2 RW 0x0 7 3 Reserved RO 0x00 Reserved 2 0 S1 RW 0x0 ...

Page 375: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C0 Bits Name Type Reset Value Description 31 0 C0 RW 0x00000000 3 9 12 3 66 0x5140 MATHFUNC_PARAM_C0_1_1_LSB Details The IIR Parameter for Math Function 1 Refer to 0x50E8 MATHFUNC_PARAM_C0_0_1_LSB Details Table SCU Sensor Control Unit 174 Local Address 0x5140 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 376: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1 Bits Name Type Reset Value Description 31 0 C1 RW 0x00000000 3 9 12 3 68 0x5148 MATHFUNC_PARAM_C1_1_1_LSB Details The IIR Parameter for Math Function 1 Refer to 0x50F0 MATHFUNC_PARAM_C1_0_1_LSB Details Table SCU Sensor Control Unit 176 Local Address 0x5148 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 377: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C2 Bits Name Type Reset Value Description 31 0 C2 RW 0x00000000 3 9 12 3 70 0x5150 MATHFUNC_PARAM_C2_1_1_LSB Details The IIR Parameter for Math Function 1 Refer to 0x50F8 MATHFUNC_PARAM_C2_0_1_LSB Details Table SCU Sensor Control Unit 178 Local Address 0x5150 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 378: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3 Bits Name Type Reset Value Description 31 0 C3 RW 0x00000000 3 9 12 3 72 0x5158 MATHFUNC_PARAM_C3_1_1_LSB Details The IIR Parameter for Math Function 1 Refer to 0x5100 MATHFUNC_PARAM_C3_0_1_LSB Details Table SCU Sensor Control Unit 180 Local Address 0x5158 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

Page 379: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C4 Bits Name Type Reset Value Description 31 0 C4 RW 0x00000000 3 9 12 3 74 0x5160 MATHFUNC_PARAM_C4_1_1_LSB Details The IIR Parameter for Math Function 1 Refer to 0x5100 MATHFUNC_PARAM_C3_0_1_LSB Details Table SCU Sensor Control Unit 182 Local Address 0x5160 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 380: ...ils Table SCU Sensor Control Unit 183 Local Address 0x5164 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved S2 Reserved S1 Bits Name Type Reset Value Description 31 11 Reserved RO 0x000000 Reserved 10 8 S2 RW 0x0 7 3 Reserved RO 0x00 Reserved 2 0 S1 RW 0x0 ...

Page 381: ...6 5 4 3 2 1 0 C0 Bits Name Type Reset Value Description 31 0 C0 RW 0x00000000 3 9 12 3 77 0x516C MATHFUNC_PARAM_C0_2_0_LSB Details The IIR Parameter for Math Function 2 Refer to 0x50A8 MATHFUNC_PARAM_C0_0_0_LSB Details_ 0x50A8 _MATHFUNC_PARAM_C0_0_0_LSB_ Table SCU Sensor Control Unit 185 Local Address 0x516C Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

Page 382: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1 Bits Name Type Reset Value Description 31 0 C1 RW 0x00000000 3 9 12 3 79 0x5174 MATHFUNC_PARAM_C1_2_0_LSB Details The IIR Parameter for Math Function 2 Refer to 0x50B4 MATHFUNC_PARAM_C1_0_0_LSB Details Table SCU Sensor Control Unit 187 Local Address 0x5174 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

Page 383: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C2 Bits Name Type Reset Value Description 31 0 C2 RW 0x00000000 3 9 12 3 81 0x517C MATHFUNC_PARAM_C2_2_0_LSB Details The IIR Parameter for Math Function 2 Refer to 0x50BC MATHFUNC_PARAM_C2_0_0_LSB Details Table SCU Sensor Control Unit 189 Local Address 0x517C Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 384: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3 Bits Name Type Reset Value Description 31 0 C3 RW 0x00000000 3 9 12 3 83 0x5184 MATHFUNC_PARAM_C3_2_0_LSB Details The IIR Parameter for Math Function 2 Refer to 0x50D4 MATHFUNC_PARAM_C3_0_0_LSB Details Table SCU Sensor Control Unit 191 Local Address 0x5184 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 385: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C4 Bits Name Type Reset Value Description 31 0 C4 RW 0x00000000 3 9 12 3 85 0x518C MATHFUNC_PARAM_C4_2_0_LSB Details The IIR Parameter for Math Function 2 Refer to 0x50DC MATHFUNC_PARAM_C4_0_0_LSB Details Table SCU Sensor Control Unit 193 Local Address 0x518C Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 386: ...Control Unit 194 Local Address 0x5190 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved S2 Reserved S1 Bits Name Type Reset Value Description 31 11 Reserved RO 0x000000 Reserved 10 8 S2 RW 0x0 7 3 Reserved RO 0x00 Reserved 2 0 S1 RW 0x0 ...

Page 387: ...6 5 4 3 2 1 0 C0 Bits Name Type Reset Value Description 31 0 C0 RW 0x00000000 3 9 12 3 88 0x5198 MATHFUNC_PARAM_C0_2_1_LSB Details The IIR Parameter for Math Function 2 Refer to 0x50E8 MATHFUNC_PARAM_C0_0_1_LSB Details_ 0x50E8 _MATHFUNC_PARAM_C0_0_1_LSB_ Table SCU Sensor Control Unit 196 Local Address 0x5198 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

Page 388: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1 Bits Name Type Reset Value Description 31 0 C1 RW 0x00000000 3 9 12 3 90 0x51A0 MATHFUNC_PARAM_C1_2_1_LSB Details The IIR Parameter for Math Function 2 Refer to 0x50F0 MATHFUNC_PARAM_C1_0_1_LSB Details_ 0x50F0 _MATHFUNC_PARAM_C1_0_1_LSB_ Table SCU Sensor Control Unit 198 Local Address 0x51A0 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 ...

Page 389: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C2 Bits Name Type Reset Value Description 31 0 C2 RW 0x00000000 3 9 12 3 92 0x51A8 MATHFUNC_PARAM_C2_2_1_LSB Details The IIR Parameter for Math Function 2 Refer to 0x50F8 MATHFUNC_PARAM_C2_0_1_LSB Details Table SCU Sensor Control Unit 200 Local Address 0x51A8 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

Page 390: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 C3 Bits Name Type Reset Value Description 31 0 C3 RW 0x00000000 3 9 12 3 94 0x51B0 MATHFUNC_PARAM_C3_2_1_LSB Details The IIR Parameter for Math Function 2 Refer to 0x5100 MATHFUNC_PARAM_C3_0_1_LSB Details_ 0x5100 _MATHFUNC_PARAM_C3_0_1_LSB_ Table SCU Sensor Control Unit 202 Local Address 0x51B0 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 ...

Page 391: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C4 Bits Name Type Reset Value Description 31 0 C4 RW 0x00000000 3 9 12 3 96 0x51B8 MATHFUNC_PARAM_C4_2_1_LSB Details The IIR Parameter for Math Function 2 Refer to 0x5108 MATHFUNC_PARAM_C4_0_1_LSB Details Table SCU Sensor Control Unit 204 Local Address 0x51B8 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

Page 392: ...PARAMX_COUNT2 DELAY_SAMPLE_F Interrupt Number of status continuity unsigned 16bit Number of status continuity unsigned 16bit Number of status continuity unsigned 16bit Number of status continuity unsigned 16bit Rise interrupt enable Fall interrupt enable Rise interrupt delay time unsigned 16bit Fall interrupt delay time unsigned 16bit Figure SCU Sensor Control Unit 88 Excess Detection Overview Exc...

Page 393: ...0 UCOUNT RW 0x0000 Designates how many times the input value exceeds the bottom threshold before the event ignition 3 9 12 3 99 0x51C4 EVENT_PARAM0_COUNT1 Details Excess detection for Math Function 0 Table SCU Sensor Control Unit 207 Local Address 0x51C4 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCOUNT U...

Page 394: ...tion 31 9 Reserved RO 0x000000 Reserved 8 FALL_INT_EN RW 0x0 Interrupt occurrence permission in the case that the status has changed from determined serially that the input values are bigger than the top threshold to determined serially that the input values are smaller than the bottom threshold 7 1 Reserved RO 0x00 Reserved 0 RISE_INT_EN RW 0x0 Interrupt occurrence permission in the case that the...

Page 395: ...09 Local Address 0x51CC Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LTHRESH UTHRESH Bits Name Type Reset Value Description 31 16 LTHRESH RW 0x0000 Reference value for excess detection bottom 15 0 UTHRESH RW 0x0000 Reference value for excess detection top ...

Page 396: ...0 UCOUNT RW 0x0000 Designates how many times the input value exceeds the bottom threshold before the event ignition 3 9 12 3 103 0x51D4 EVENT_PARAM1_COUNT1 Details Excess detection for Math Function 1 Table SCU Sensor Control Unit 211 Local Address 0x51D4 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCOUNT ...

Page 397: ...tion 31 9 Reserved RO 0x000000 Reserved 8 FALL_INT_EN RW 0x0 Interrupt occurrence permission in the case that the status has changed from determined serially that the input values are bigger than the top threshold to determined serially that the input values are smaller than the bottom threshold 7 1 Reserved RO 0x00 Reserved 0 RISE_INT_EN RW 0x0 Interrupt occurrence permission in the case that the...

Page 398: ...e SCU Sensor Control Unit 213 Local Address 0x51DC Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LTHRESH UTHRESH Bits Name Type Reset Value Description 31 16 LTHRESH RW 0x0000 Bottom threshold 15 0 UTHRESH RW 0x0000 Top threshold ...

Page 399: ...0 UCOUNT RW 0x0000 Designates how many times the input value exceeds the bottom threshold before the event ignition 3 9 12 3 107 0x51E4 EVENT_PARAM2_COUNT1 Details Excess detection for Math Function 2 Table SCU Sensor Control Unit 215 Local Address 0x51E4 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCOUNT ...

Page 400: ...tion 31 9 Reserved RO 0x000000 Reserved 8 FALL_INT_EN RW 0x0 Interrupt occurrence permission in the case that the status has changed from determined serially that the input values are bigger than the top threshold to determined serially that the input values are smaller than the bottom threshold 7 1 Reserved RO 0x00 Reserved 0 RISE_INT_EN RW 0x0 Interrupt occurrence permission in the case that the...

Page 401: ...f the event ignition is fulfilled this register designates how many samples must be taken before the event ignition 3 9 12 3 110 0x51F0 EVENT_PARAM1_DELAY_SAMPLE Details Table SCU Sensor Control Unit 218 Local Address 0x51F0 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DELAY_SAMPLE_F DELAY_SAMPLE_R Bits Nam...

Page 402: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DELAY_SAMPLE_F DELAY_SAMPLE_R Bits Name Type Reset Value Description 31 16 DELAY_SAMPLE_F RW 0x0000 After the conditions of the event ignition is fulfilled this register designates how many samples must be taken before the event ignition 15 0 DELAY_SAMPLE_R RW 0x0000 After the conditions of the event ignition is fulfilled this register designates how many sample...

Page 403: ... 0 TIMESTAMP RO 0x00000000 Time stamp value integer part of second at the EVENT0 occurrence 3 9 12 3 113 0x5204 EVENT_TIMESTAMP0_R_LSB Details Table SCU Sensor Control Unit 221 Local Address 0x5204 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIMESTAMP Bits Name Type Reset Value Description 31 15 Re...

Page 404: ... 0 TIMESTAMP RO 0x00000000 Time stamp value integer part of second at the EVENT1 occurrence 3 9 12 3 115 0x520C EVENT_TIMESTAMP1_R_LSB Details Table SCU Sensor Control Unit 223 Local Address 0x520C Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIMESTAMP Bits Name Type Reset Value Description 31 15 Re...

Page 405: ... 0 TIMESTAMP RO 0x00000000 Time stamp value integer part of second at the EVENT2 occurrence 3 9 12 3 117 0x5214 EVENT_TIMESTAMP2_R_LSB Details Table SCU Sensor Control Unit 225 Local Address 0x5214 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIMESTAMP Bits Name Type Reset Value Description 31 15 Re...

Page 406: ... 0 TIMESTAMP RO 0x00000000 Time stamp value integer part of second at the EVENT0 occurrence 3 9 12 3 119 0x521C EVENT_TIMESTAMP0_F_LSB Details Table SCU Sensor Control Unit 227 Local Address 0x521C Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIMESTAMP Bits Name Type Reset Value Description 31 15 Re...

Page 407: ... 0 TIMESTAMP RO 0x00000000 Time stamp value integer part of second at the EVENT1 occurrence 3 9 12 3 121 0x5224 EVENT_TIMESTAMP1_F_LSB Details Table SCU Sensor Control Unit 229 Local Address 0x5224 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIMESTAMP Bits Name Type Reset Value Description 31 15 Re...

Page 408: ... 0 TIMESTAMP RO 0x00000000 Time stamp value integer part of second at the EVENT2 occurrence 3 9 12 3 123 0x522C EVENT_TIMESTAMP2_F_LSB Details Table SCU Sensor Control Unit 231 Local Address 0x522C Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIMESTAMP Bits Name Type Reset Value Description 31 15 Re...

Page 409: ... 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EVENT2_F EVENT1_F EVENT0_F EVENT2_R EVENT1_R EVENT0_R Bits Name Type Reset Value Description 31 6 Reserved RO 0x0000000 Reserved 5 EVENT2_F RW 0x0 4 EVENT1_F RW 0x0 3 EVENT0_F RW 0x0 2 EVENT2_R RW 0x0 1 EVENT1_R RW 0x0 0 EVENT0_R RW 0x0 The status of MATH_EVENT It is referred when writing data to the FIFO It can be cleared by wri...

Page 410: ...1_R2_C_ALMOST_FULL D1_R1_C_ALMOST_FULL D0_R2_C_ALMOST_FULL D0_R1_C_ALMOST_FULL MATH_EVENT2_R MATH_EVENT1_R MATH_EVENT0_R HPADC1_ALMOST_FULL HPADC0_ALMOST_FULL LPADC_ALMOST_FULL I2C1 I2C0 SPI Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 MATH_EVENT2_F RW 0x0 29 MATH_EVENT1_F RW 0x0 28 MATH_EVENT0_F RW 0x0 27 ISOP3 RW 0x0 26 ISOP2 RW 0x0 25 ISOP1 RW 0x0 24 ISOP0 RW 0x0 23 Res...

Page 411: ...H_EVENT2_R RW 0x0 7 MATH_EVENT1_R RW 0x0 6 MATH_EVENT0_R RW 0x0 5 HPADC1_ALMOST_FULL RW 0x0 4 HPADC0_ALMOST_FULL RW 0x0 3 LPADC_ALMOST_FULL RW 0x0 2 I2C1 RW 0x0 1 I2C0 RW 0x0 0 SPI RW 0x0 Interrupt permission for the SPI or Math Function Event 0 The interrupt is permitted by writing 1 Writing 0 cannot prohibit the interrupt ...

Page 412: ...D1_R2_C_ALMOST_FULL D1_R1_C_ALMOST_FULL D0_R2_C_ALMOST_FULL D0_R1_C_ALMOST_FULL MATH_EVENT2_R MATH_EVENT1_R MATH_EVENT0_R HPADC1_ALMOST_FULL HPADC0_ALMOST_FULL LPADC_ALMOST_FULL I2C1 I2C0 SPI Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 MATH_EVENT2_F RW 0x0 29 MATH_EVENT1_F RW 0x0 28 MATH_EVENT0_F RW 0x0 27 ISOP3 RW 0x0 26 ISOP2 RW 0x0 25 ISOP1 RW 0x0 24 ISOP0 RW 0x0 23 Re...

Page 413: ...RW 0x0 8 MATH_EVENT2_R RW 0x0 7 MATH_EVENT1_R RW 0x0 6 MATH_EVENT0_R RW 0x0 5 HPADC1_ALMOST_FULL RW 0x0 4 HPADC0_ALMOST_FULL RW 0x0 3 LPADC_ALMOST_FULL RW 0x0 2 I2C1 RW 0x0 1 I2C0 RW 0x0 0 SPI RW 0x0 Interrupt prohibition for the SPI The interrupt is prohibited by writing 1 Writing 0 cannot permit the interrupt ...

Page 414: ..._FULL D1_R1_C_ALMOST_FULL D0_R2_C_ALMOST_FULL D0_R1_C_ALMOST_FULL MATH_EVENT2_R MATH_EVENT1_R MATH_EVENT0_R HPADC1_ALMOST_FULL HPADC0_ALMOST_FULL LPADC_ALMOST_FULL Reserved Bits Name Type Reset Value Description 31 Reserved WO 0x0 Reserved 30 MATH_EVENT2_F WO 0x0 29 MATH_EVENT1_F WO 0x0 28 MATH_EVENT0_F WO 0x0 27 ISOP3 WO 0x0 26 ISOP2 WO 0x0 25 ISOP1 WO 0x0 24 ISOP0 WO 0x0 23 Reserved WO 0x0 Reser...

Page 415: ...0_R2_C_ALMOST_FULL WO 0x0 9 D0_R1_C_ALMOST_FULL WO 0x0 8 MATH_EVENT2_R WO 0x0 7 MATH_EVENT1_R WO 0x0 6 MATH_EVENT0_R WO 0x0 5 HPADC1_ALMOST_FULL WO 0x0 4 HPADC0_ALMOST_FULL WO 0x0 3 LPADC_ALMOST_FULL WO 0x0 2 0 Reserved WO 0x0 Reserved ...

Page 416: ...T_FULL D1_R1_C_ALMOST_FULL D0_R2_C_ALMOST_FULL D0_R1_C_ALMOST_FULL Reserved HPADC1_ALMOST_FULL HPADC0_ALMOST_FULL LPADC_ALMOST_FULL Reserved Bits Name Type Reset Value Description 31 28 Reserved RO 0x0 Reserved 27 ISOP3 RW 0x0 26 ISOP2 RW 0x0 25 ISOP1 RW 0x0 24 ISOP0 RW 0x0 23 Reserved RO 0x0 Reserved 22 D1_R3_CH_ALMOST_FULL RW 0x0 21 D0_R3_CH_ALMOST_FULL RW 0x0 20 N7_R1_C_ALMOST_FULL RW 0x0 19 N6...

Page 417: ...Reserved 5 HPADC1_ALMOST_FULL RW 0x0 4 HPADC0_ALMOST_FULL RW 0x0 3 LPADC_ALMOST_FULL RW 0x0 Set 1 when you want to use interrupt LPADC_ALMOST_FULL as a level interrupt Set 0 when you use the interrupt as an edge detection 2 0 Reserved RO 0x0 Reserved ...

Page 418: ...ULL D1_R1_C_ALMOST_FULL D0_R2_C_ALMOST_FULL D0_R1_C_ALMOST_FULL MATH_EVENT2_R MATH_EVENT1_R MATH_EVENT0_R HPADC1_ALMOST_FULL HPADC0_ALMOST_FULL LPADC_ALMOST_FULL I2C1 I2C0 SPI Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 MATH_EVENT2_F RO 0x0 29 MATH_EVENT1_F RO 0x0 28 MATH_EVENT0_F RO 0x0 27 ISOP3 RO 0x0 26 ISOP2 RO 0x0 25 ISOP1 RO 0x0 24 ISOP0 RO 0x0 23 Reserved RO 0x0 Re...

Page 419: ..._FULL RO 0x0 8 MATH_EVENT2_R RO 0x0 7 MATH_EVENT1_R RO 0x0 6 MATH_EVENT0_R RO 0x0 5 HPADC1_ALMOST_FULL RO 0x0 4 HPADC0_ALMOST_FULL RO 0x0 3 LPADC_ALMOST_FULL RO 0x0 2 I2C1 RO 0x0 1 I2C0 RO 0x0 0 SPI RO 0x0 The interrupt status of the SPI or Math Function Event 0 before masking ...

Page 420: ...MOST_FULL D1_R1_C_ALMOST_FULL D0_R2_C_ALMOST_FULL D0_R1_C_ALMOST_FULL MATH_EVENT2_R MATH_EVENT1_R MATH_EVENT0_R HPADC1_ALMOST_FULL HPADC0_ALMOST_FULL LPADC_ALMOST_FULL I2C1 I2C0 SPI Bits Name Type Reset Value Description 31 ALL_ORED_ERR RO 0x0 30 MATH_EVENT2_F RO 0x0 29 MATH_EVENT1_F RO 0x0 28 MATH_EVENT0_F RO 0x0 27 ISOP3 RO 0x0 26 ISOP2 RO 0x0 25 ISOP1 RO 0x0 24 ISOP0 RO 0x0 23 Reserved RO 0x0 R...

Page 421: ..._FULL RO 0x0 8 MATH_EVENT2_R RO 0x0 7 MATH_EVENT1_R RO 0x0 6 MATH_EVENT0_R RO 0x0 5 HPADC1_ALMOST_FULL RO 0x0 4 HPADC0_ALMOST_FULL RO 0x0 3 LPADC_ALMOST_FULL RO 0x0 2 I2C1 RO 0x0 1 I2C0 RO 0x0 0 SPI RO 0x0 The interrupt status of the SPI or Math Function Event 0 after masking ...

Page 422: ...VER_RUN Reserved ADCIF_READ_ERR HPADC1_OVER_RUN HPADC0_OVER_RUN LPADC_OVER_RUN LPADC_OVER_RUN3 LPADC_OVER_RUN2 LPADC_OVER_RUN1 Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 PWM7_INVALID_VALUE RW 0x0 29 PWM6_INVALID_VALUE RW 0x0 28 PWM5_INVALID_VALUE RW 0x0 27 PWM4_INVALID_VALUE RW 0x0 26 PWM3_INVALID_VALUE RW 0x0 25 PWM2_INVALID_VALUE RW 0x0 24 PWM1_INVALID_VALUE RW 0x0 Int...

Page 423: ...0 10 D0_R2_C_OVER_RUN RW 0x0 9 D0_R1_C_OVER_RUN RW 0x0 8 7 Reserved RO 0x0 Reserved 6 ADCIF_READ_ERR RW 0x0 5 HPADC1_OVER_RUN RW 0x0 4 HPADC0_OVER_RUN RW 0x0 3 LPADC_OVER_RUN RW 0x0 2 LPADC_OVER_RUN3 RW 0x0 1 LPADC_OVER_RUN2 RW 0x0 0 LPADC_OVER_RUN1 RW 0x0 ...

Page 424: ...OVER_RUN Reserved ADCIF_READ_ERR HPADC1_OVER_RUN HPADC0_OVER_RUN LPADC_OVER_RUN LPADC_OVER_RUN3 LPADC_OVER_RUN2 LPADC_OVER_RUN1 Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 PWM7_INVALID_VALUE RW 0x0 29 PWM6_INVALID_VALUE RW 0x0 28 PWM5_INVALID_VALUE RW 0x0 27 PWM4_INVALID_VALUE RW 0x0 26 PWM3_INVALID_VALUE RW 0x0 25 PWM2_INVALID_VALUE RW 0x0 24 PWM1_INVALID_VALUE RW 0x0 In...

Page 425: ...OVER_RUN RW 0x0 8 7 Reserved RO 0x0 Reserved 6 ADCIF_READ_ERR RW 0x0 5 HPADC1_OVER_RUN RW 0x0 4 HPADC0_OVER_RUN RW 0x0 3 LPADC_OVER_RUN RW 0x0 2 LPADC_OVER_RUN3 RW 0x0 1 LPADC_OVER_RUN2 RW 0x0 0 LPADC_OVER_RUN1 RW 0x0 Interrupt permission of overrun error write occurrence at FIFO Full for LPADC ...

Page 426: ...ER_RUN LPADC_OVER_RUN3 LPADC_OVER_RUN2 LPADC_OVER_RUN1 Bits Name Type Reset Value Description 31 Reserved WO 0x0 Reserved 30 PWM7_INVALID_VALUE WO 0x0 29 PWM6_INVALID_VALUE WO 0x0 28 PWM5_INVALID_VALUE WO 0x0 27 PWM4_INVALID_VALUE WO 0x0 26 PWM3_INVALID_VALUE WO 0x0 25 PWM2_INVALID_VALUE WO 0x0 24 PWM1_INVALID_VALUE WO 0x0 Interrupt clear of detecting outlier setting CYCLE THRESH to PWM1 23 PWM0_I...

Page 427: ..._R1_C_OVER_RUN D0_R2_C_OVER_RUN D0_R1_C_OVER_RUN Reserved ADCIF_READ_ERR HPADC1_OVER_RUN HPADC0_OVER_RUN LPADC_OVER_RUN LPADC_OVER_RUN3 LPADC_OVER_RUN2 LPADC_OVER_RUN1 Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 PWM7_INVALID_VALUE RO 0x0 29 PWM6_INVALID_VALUE RO 0x0 28 PWM5_INVALID_VALUE RO 0x0 27 PWM4_INVALID_VALUE RO 0x0 26 PWM3_INVALID_VALUE RO 0x0 25 PWM2_INVALID_VALU...

Page 428: ...0 9 D0_R1_C_OVER_RUN RO 0x0 8 7 Reserved RO 0x0 Reserved 6 ADCIF_READ_ERR RO 0x0 5 HPADC1_OVER_RUN RO 0x0 4 HPADC0_OVER_RUN RO 0x0 3 LPADC_OVER_RUN RO 0x0 2 LPADC_OVER_RUN3 RO 0x0 1 LPADC_OVER_RUN2 RO 0x0 0 LPADC_OVER_RUN1 RO 0x0 ...

Page 429: ...D1_R1_C_OVER_RUN D0_R2_C_OVER_RUN D0_R1_C_OVER_RUN Reserved ADCIF_READ_ERR HPADC1_OVER_RUN HPADC0_OVER_RUN LPADC_OVER_RUN LPADC_OVER_RUN3 LPADC_OVER_RUN2 LPADC_OVER_RUN1 Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 PWM7_INVALID_VALUE RO 0x0 29 PWM6_INVALID_VALUE RO 0x0 28 PWM5_INVALID_VALUE RO 0x0 27 PWM4_INVALID_VALUE RO 0x0 26 PWM3_INVALID_VALUE RO 0x0 25 PWM2_INVALID_VA...

Page 430: ...0 9 D0_R1_C_OVER_RUN RO 0x0 8 7 Reserved RO 0x0 Reserved 6 ADCIF_READ_ERR RO 0x0 5 HPADC1_OVER_RUN RO 0x0 4 HPADC0_OVER_RUN RO 0x0 3 LPADC_OVER_RUN RO 0x0 2 LPADC_OVER_RUN3 RO 0x0 1 LPADC_OVER_RUN2 RO 0x0 0 LPADC_OVER_RUN1 RO 0x0 ...

Page 431: ...1_UNDER_RUN HPADC0_UNDER_RUN LPADC_UNDER_RUN LPADC_UNDER_RUN3 LPADC_UNDER_RUN2 LPADC_UNDER_RUN1 Bits Name Type Reset Value Description 31 23 Reserved RO 0x000 Reserved 22 D1_R3_CH_UNDER_RUN RW 0x0 21 D0_R3_CH_UNDER_RUN RW 0x0 20 N7_R1_C_UNDER_RUN RW 0x0 19 N6_R1_C_UNDER_RUN RW 0x0 18 N5_R1_C_UNDER_RUN RW 0x0 17 N4_R1_C_UNDER_RUN RW 0x0 16 N3_R1_C_UNDER_RUN RW 0x0 15 N2_R1_C_UNDER_RUN RW 0x0 14 N1_...

Page 432: ...C1_UNDER_RUN HPADC0_UNDER_RUN LPADC_UNDER_RUN LPADC_UNDER_RUN3 LPADC_UNDER_RUN2 LPADC_UNDER_RUN1 Bits Name Type Reset Value Description 31 23 Reserved RO 0x000 Reserved 22 D1_R3_CH_UNDER_RUN RW 0x0 21 D0_R3_CH_UNDER_RUN RW 0x0 20 N7_R1_C_UNDER_RUN RW 0x0 19 N6_R1_C_UNDER_RUN RW 0x0 18 N5_R1_C_UNDER_RUN RW 0x0 17 N4_R1_C_UNDER_RUN RW 0x0 16 N3_R1_C_UNDER_RUN RW 0x0 15 N2_R1_C_UNDER_RUN RW 0x0 14 N1...

Page 433: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HPADC1_UNDER_RUN HPADC0_UNDER_RUN LPADC_UNDER_RUN LPADC_UNDER_RUN3 LPADC_UNDER_RUN2 LPADC_UNDER_RUN1 Bits Name Type Reset Value Description 31 6 Reserved WO 0x0000000 Reserved 5 HPADC1_UNDER_RUN WO 0x0 4 HPADC0_UNDER_RUN WO 0x0 3 LPADC_UNDER_RUN WO 0x0 2 LPADC_UNDER_RUN3 WO 0x0 1 LPADC_UNDER_RUN2 WO 0x0 0 LPADC_UNDER_RUN1 WO ...

Page 434: ...1_UNDER_RUN HPADC0_UNDER_RUN LPADC_UNDER_RUN LPADC_UNDER_RUN3 LPADC_UNDER_RUN2 LPADC_UNDER_RUN1 Bits Name Type Reset Value Description 31 23 Reserved RO 0x000 Reserved 22 D1_R3_CH_UNDER_RUN RO 0x0 21 D0_R3_CH_UNDER_RUN RO 0x0 20 N7_R1_C_UNDER_RUN RO 0x0 19 N6_R1_C_UNDER_RUN RO 0x0 18 N5_R1_C_UNDER_RUN RO 0x0 17 N4_R1_C_UNDER_RUN RO 0x0 16 N3_R1_C_UNDER_RUN RO 0x0 15 N2_R1_C_UNDER_RUN RO 0x0 14 N1_...

Page 435: ...ADC1_UNDER_RUN HPADC0_UNDER_RUN LPADC_UNDER_RUN LPADC_UNDER_RUN3 LPADC_UNDER_RUN2 LPADC_UNDER_RUN1 Bits Name Type Reset Value Description 31 23 Reserved RO 0x000 Reserved 22 D1_R3_CH_UNDER_RUNRO 0x0 21 D0_R3_CH_UNDER_RUNRO 0x0 20 N7_R1_C_UNDER_RUN RO 0x0 19 N6_R1_C_UNDER_RUN RO 0x0 18 N5_R1_C_UNDER_RUN RO 0x0 17 N4_R1_C_UNDER_RUN RO 0x0 16 N3_R1_C_UNDER_RUN RO 0x0 15 N2_R1_C_UNDER_RUN RO 0x0 14 N1...

Page 436: ...EFORE_FINISH3 REQ_BEFORE_FINISH2 REQ_BEFORE_FINISH1 REQ_BEFORE_FINISH0 Bits Name Type Reset Value Description 31 26 Reserved RO 0x00 Reserved 25 EXE_ERR9 RW 0x0 24 EXE_ERR8 RW 0x0 23 EXE_ERR7 RW 0x0 22 EXE_ERR6 RW 0x0 21 EXE_ERR5 RW 0x0 20 EXE_ERR4 RW 0x0 19 EXE_ERR3 RW 0x0 18 EXE_ERR2 RW 0x0 17 EXE_ERR1 RW 0x0 16 EXE_ERR0 RW 0x0 Permission of interrupt for not completing the sequencer s process s...

Page 437: ...CXD5602 User Manual 437 1010 1 REQ_BEFORE_FINISH1 RW 0x0 0 REQ_BEFORE_FINISH0 RW 0x0 Permission of interrupt for requesting the next operation before completion Sequencer 0 ...

Page 438: ...EFORE_FINISH3 REQ_BEFORE_FINISH2 REQ_BEFORE_FINISH1 REQ_BEFORE_FINISH0 Bits Name Type Reset Value Description 31 26 Reserved RO 0x00 Reserved 25 EXE_ERR9 RW 0x0 24 EXE_ERR8 RW 0x0 23 EXE_ERR7 RW 0x0 22 EXE_ERR6 RW 0x0 21 EXE_ERR5 RW 0x0 20 EXE_ERR4 RW 0x0 19 EXE_ERR3 RW 0x0 18 EXE_ERR2 RW 0x0 17 EXE_ERR1 RW 0x0 16 EXE_ERR0 RW 0x0 Permission of interrupt for not completing the sequencer s process s...

Page 439: ...CXD5602 User Manual 439 1010 1 REQ_BEFORE_FINISH1 RW 0x0 0 REQ_BEFORE_FINISH0 RW 0x0 Permission of interrupt for requesting the next operation before completion Sequencer 0 ...

Page 440: ..._BEFORE_FINISH3 REQ_BEFORE_FINISH2 REQ_BEFORE_FINISH1 REQ_BEFORE_FINISH0 Bits Name Type Reset Value Description 31 26 Reserved WO 0x00 Reserved 25 EXE_ERR9 WO 0x0 24 EXE_ERR8 WO 0x0 23 EXE_ERR7 WO 0x0 22 EXE_ERR6 WO 0x0 21 EXE_ERR5 WO 0x0 20 EXE_ERR4 WO 0x0 19 EXE_ERR3 WO 0x0 18 EXE_ERR2 WO 0x0 17 EXE_ERR1 WO 0x0 16 EXE_ERR0 WO 0x0 Clear of interrupt for not completing the sequencer s process succ...

Page 441: ...CXD5602 User Manual 441 1010 1 REQ_BEFORE_FINISH1 WO 0x0 0 REQ_BEFORE_FINISH0 WO 0x0 Clear of interrupt for requesting the next operation before completion Sequencer 0 ...

Page 442: ...FINISH3 REQ_BEFORE_FINISH2 REQ_BEFORE_FINISH1 REQ_BEFORE_FINISH0 Bits Name Type Reset Value Description 31 26 Reserved RO 0x00 Reserved 25 EXE_ERR9 RO 0x0 24 EXE_ERR8 RO 0x0 23 EXE_ERR7 RO 0x0 22 EXE_ERR6 RO 0x0 21 EXE_ERR5 RO 0x0 20 EXE_ERR4 RO 0x0 19 EXE_ERR3 RO 0x0 18 EXE_ERR2 RO 0x0 17 EXE_ERR1 RO 0x0 16 EXE_ERR0 RO 0x0 Status of interrupt for not completing the sequencer s process successfull...

Page 443: ...CXD5602 User Manual 443 1010 1 REQ_BEFORE_FINISH1 RO 0x0 0 REQ_BEFORE_FINISH0 RO 0x0 Interrupt status for requesting the next operation before completion Sequencer 0 before masking ...

Page 444: ...E_FINISH3 REQ_BEFORE_FINISH2 REQ_BEFORE_FINISH1 REQ_BEFORE_FINISH0 Bits Name Type Reset Value Description 31 26 Reserved RO 0x00 Reserved 25 EXE_ERR9 RO 0x0 24 EXE_ERR8 RO 0x0 23 EXE_ERR7 RO 0x0 22 EXE_ERR6 RO 0x0 21 EXE_ERR5 RO 0x0 20 EXE_ERR4 RO 0x0 19 EXE_ERR3 RO 0x0 18 EXE_ERR2 RO 0x0 17 EXE_ERR1 RO 0x0 16 EXE_ERR0 RO 0x0 Status of interrupt for not completing the sequencer s process successfu...

Page 445: ...CXD5602 User Manual 445 1010 1 REQ_BEFORE_FINISH1 RO 0x0 0 REQ_BEFORE_FINISH0 RO 0x0 Interrupt status for requesting the next operation before completion Sequencer 0 after masking ...

Page 446: ...ll RAMs in the SCU 4 2 RM RW 0x0 read timing margin common to all RAMs in the SCU 1 EN_STANDBY RW 0x0 standby enable common to all RAMs in the SCU 0 EN_IG RW 0x0 InputGate enable common to all RAMs in the SCU 3 9 12 3 147 0x5510 SCU_POWER Details Clock Control under Internal Sequencer s control 0 CK_SCU 1 CK_SCU_SPI 2 CK_SCU_I2C0 3 CK_SCU_I2C1 Table SCU Sensor Control Unit 255 Local Address 0x5510...

Page 447: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LPADC_ALMOST_FULL3 LPADC_ALMOST_FULL2 LPADC_ALMOST_FULL1 Bits Name Type Reset Value Description 31 3 Reserved RO 0x00000000 Reserved 2 LPADC_ALMOST_FULL3 RW 0x0 1 LPADC_ALMOST_FULL2 RW 0x0 0 LPADC_ALMOST_FULL1 RW 0x0 Interrupt permission for the SPI or Math Function Event 0 The interrupt is permitted by writing 1 Writing 0 cannot prohib...

Page 448: ... 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LPADC_ALMOST_FULL3 LPADC_ALMOST_FULL2 LPADC_ALMOST_FULL1 Bits Name Type Reset Value Description 31 3 Reserved RO 0x00000000 Reserved 2 LPADC_ALMOST_FULL3 RW 0x0 1 LPADC_ALMOST_FULL2 RW 0x0 0 LPADC_ALMOST_FULL1 RW 0x0 Interrupt prohibition for the SPI The interrupt is prohibited by writing 1 Writing 0 cannot permit the inter...

Page 449: ... 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LPADC_ALMOST_FULL3 LPADC_ALMOST_FULL2 LPADC_ALMOST_FULL1 Bits Name Type Reset Value Description 31 3 Reserved WO 0x00000000 Reserved 2 LPADC_ALMOST_FULL3 WO 0x0 1 LPADC_ALMOST_FULL2 WO 0x0 0 LPADC_ALMOST_FULL1 WO 0x0 Interrupt clear of Math Function Event 0 When the SPI is selected the interrupt is cleared by the register of the ...

Page 450: ...W read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LPADC_ALMOST_FULL3 LPADC_ALMOST_FULL2 LPADC_ALMOST_FULL1 Bits Name Type Reset Value Description 31 3 Reserved RO 0x00000000 Reserved 2 LPADC_ALMOST_FULL3 RW 0x0 1 LPADC_ALMOST_FULL2 RW 0x0 0 LPADC_ALMOST_FULL1 RW 0x0 ...

Page 451: ...0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LPADC_ALMOST_FULL3 LPADC_ALMOST_FULL2 LPADC_ALMOST_FULL1 Bits Name Type Reset Value Description 31 3 Reserved RO 0x00000000 Reserved 2 LPADC_ALMOST_FULL3 RO 0x0 1 LPADC_ALMOST_FULL2 RO 0x0 0 LPADC_ALMOST_FULL1 RO 0x0 Interrupt status of the SPI or Math Function Event 0 before masking ...

Page 452: ...000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LPADC_ALMOST_FULL3 LPADC_ALMOST_FULL2 LPADC_ALMOST_FULL1 Bits Name Type Reset Value Description 31 3 Reserved RO 0x00000000 Reserved 2 LPADC_ALMOST_FULL3 RO 0x0 1 LPADC_ALMOST_FULL2 RO 0x0 0 LPADC_ALMOST_FULL1 RO 0x0 Interrupt status of the SPI or Math Function Event 0 after masking ...

Page 453: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM0_THRESH PWM0_CYCLE Bits Name Type Reset Value Description 31 16 PWM0_THRESH RW 0x0000 Sets the duty of PWM0 output 15 0 PWM0_CYCLE RW 0x0000 Sets the cycle of PWM0 output For formulas of the cycle and the DUTY refer to the below As for the formula of the PWM cycle refer to Section 3 9 11 2 1 and as for the formula of the DUTY period of HIGH cycle of the PWM outp...

Page 454: ... RO 0x000000 Reserved 7 1 PWM_SELL0 RW 0x00 3 1 Selects a target AD which the PWM0 is synchronized with 0x0 is not synchronized with ADs 0x1 is synchronized with HPADC0 0x2 is synchronized with HPADC1 0x3 is synchronized with LPADC in operation 0x4 is synchronized with LPADC0 0x5 is synchronized with LPADC1 0x6 is synchronized with LPADC2 0x7 is synchronized with LPADC3 6 4 Selects a target PWM wh...

Page 455: ...s register 3 9 12 3 157 0x560C PWM1_PARAM Details Table SCU Sensor Control Unit 265 Local Address 0x560C Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM1_THRESH PWM1_CYCLE Bits Name Type Reset Value Description 31 16 PWM1_THRESH RW 0x0000 Sets the duty of PWM1 output 15 0 PWM1_CYCLE RW 0x0000 Sets the outp...

Page 456: ...7 1 PWM_SELL1 RW 0x00 3 1 Selects a target AD which the PWM1 is synchronized with 0x0 is not synchronized with ADs 0x1 is synchronized with HPADC0 0x2 is synchronized with HPADC1 0x3 is synchronized with LPADC in operation 0x4 is synchronized with LPADC0 0x5 is synchronized with LPADC1 0x6 is synchronized with LPADC2 0x7 is synchronized with LPADC3 6 4 Selects a target PWM which the PWM1 is synchr...

Page 457: ... this register 3 9 12 3 160 0x5618 PWM2_PARAM Details Table SCU Sensor Control Unit 268 Local Address 0x5618 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM2_THRESH PWM2_CYCLE Bits Name Type Reset Value Description 31 16 PWM2_THRESH RW 0x0000 Sets the duty of PWM2 output 15 0 PWM2_CYCLE RW 0x0000 Sets the ...

Page 458: ...e PWM2 is synchronized with 0x0 is not synchronized with ADs 0x1 is synchronized with HPADC0 0x2 is synchronized with HPADC1 0x3 is synchronized with LPADC in operation 0x4 is synchronized with LPADC0 0x5 is synchronized with LPADC1 0x6 is synchronized with LPADC2 0x7 is synchronized with LPADC3 6 4 Selects a target PWM which the PWM2 is synchronized with 0 PWM2_EN RW 0x0 Controls the permission s...

Page 459: ...s register 3 9 12 3 163 0x5624 PWM3_PARAM Details Table SCU Sensor Control Unit 271 Local Address 0x5624 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM3_THRESH PWM3_CYCLE Bits Name Type Reset Value Description 31 16 PWM3_THRESH RW 0x0000 Sets the duty of PWM3 output 15 0 PWM3_CYCLE RW 0x0000 Sets the outp...

Page 460: ...e PWM3 is synchronized with 0x0 is not synchronized with ADs 0x1 is synchronized with HPADC0 0x2 is synchronized with HPADC1 0x3 is synchronized with LPADC in operation 0x4 is synchronized with LPADC0 0x5 is synchronized with LPADC1 0x6 is synchronized with LPADC2 0x7 is synchronized with LPADC3 6 4 Selects a target PWM which the PWM3 is synchronized with 0 PWM3_EN RW 0x0 Controls the permission s...

Page 461: ...Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PWM3_UPDATE Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 PWM3_UPDATE WO 0x0 Reflects a set value in PWM3 s operation by writing 1 on this register ...

Page 462: ..._CNTEN0 PWM_DELAY0 Bits Name Type Reset Value Description 31 16 PWM_CNTEN0 RW 0x0000 19 16 Sets the PWM prescale 0x0 1 1 0x1 1 2 0x2 1 4 0x3 1 8 0x4 1 16 0x5 1 32 0x6 1 64 0x7 1 128 0x8 1 256 23 20 The number of AD capturing based on the PWM from 1 to 15 available 31 24 Positioning for capturing AD based on the PWM step is SCU_CK unit from 3 to 255 available 15 0 PWM_DELAY0 RW 0x0000 Adjusts phase...

Page 463: ... Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM_CNTEN1 PWM_DELAY1 Bits Name Type Reset Value Description 31 16 PWM_CNTEN1 RW 0x0000 PWM1 setting for the control specification refer to PWM_CNTEN0 15 0 PWM_DELAY1 RW 0x0000 Adjusts phases for the timing of AD data capturing to SCU unit 0 65535 clock ...

Page 464: ... Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM_CNTEN2 PWM_DELAY2 Bits Name Type Reset Value Description 31 16 PWM_CNTEN2 RW 0x0000 PWM2 setting for the control specification refer to PWM_CNTEN0 15 0 PWM_DELAY2 RW 0x0000 Adjusts phases for the timing of AD data capturing to SCU unit 0 65535 clock ...

Page 465: ... Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM_CNTEN3 PWM_DELAY3 Bits Name Type Reset Value Description 31 16 PWM_CNTEN3 RW 0x0000 PWM3 setting for the control specification refer to PWM_CNTEN0 15 0 PWM_DELAY3 RW 0x0000 Adjusts phases for the timing of AD data capturing to SCU unit 0 65535 clock ...

Page 466: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM4_THRESH PWM4_CYCLE Bits Name Type Reset Value Description 31 16 PWM4_THRESH RW 0x0000 Sets the duty of PWM4 output 15 0 PWM4_CYCLE RW 0x0000 Sets the output cycle of PWM4 For formulas of the cycle and the DUTY refer to the below As for the formula of the PWM cycle refer to Section 3 9 11 2 1 and as for the formula of the DUTY period of HIGH cycle of the PWM outpu...

Page 467: ... RW 0x00 3 1 Selects a target AD which the PWM4 is synchronized with 0x0 is not synchronized with ADs 0x1 is synchronized with HPADC0 0x2 is synchronized with HPADC1 0x3 is synchronized with LPADC in operation 0x4 is synchronized with LPADC0 0x5 is synchronized with LPADC1 0x6 is synchronized with LPADC2 0x7 is synchronized with LPADC3 6 4 Selects a target PWM which the PWM4 is synchronized with 0...

Page 468: ...Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PWM4_UPDATE Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 PWM4_UPDATE WO 0x0 Reflects a set value in PWM4 s operation by writing 1 on this register ...

Page 469: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM5_THRESH PWM5_CYCLE Bits Name Type Reset Value Description 31 16 PWM5_THRESH RW 0x0000 Sets the duty of PWM5 output 15 0 PWM5_CYCLE RW 0x0000 Sets the output cycle of PWM5 For formulas of the cycle and the DUTY refer to the below As for the formula of the PWM cycle refer to Section 3 9 11 2 1 and as for the formula of the DUTY period of HIGH cycle of the PWM outp...

Page 470: ...e PWM5 is synchronized with 000 is not synchronized with ADs 001 is synchronized with HPADC0 002 is synchronized with HPADC1 003 is synchronized with LPADC in operation 004 is synchronized with LPADC0 005 is synchronized with LPADC1 006 is synchronized with LPADC2 007 is synchronized with LPADC3 6 4 Selects a target PWM which the PWM5 is synchronized with 0 PWM5_EN RW 0x0 Controls the permission s...

Page 471: ...Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PWM5_UPDATE Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 PWM5_UPDATE WO 0x0 Reflects a set value in PWM5 s operation by writing 1 on this register ...

Page 472: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM6_THRESH PWM6_CYCLE Bits Name Type Reset Value Description 31 16 PWM6_THRESH RW 0x0000 Sets the duty of PWM6 output 15 0 PWM6_CYCLE RW 0x0000 Sets the output cycle of PWM6 For formulas of the cycle and the DUTY refer to the below As for the formula of the PWM cycle refer to Section 3 9 11 2 1 and as for the formula of the DUTY period of HIGH cycle of the PWM outp...

Page 473: ...e PWM6 is synchronized with 000 is not synchronized with ADs 001 is synchronized with HPADC0 002 is synchronized with HPADC1 003 is synchronized with LPADC in operation 004 is synchronized with LPADC0 005 is synchronized with LPADC1 006 is synchronized with LPADC2 007 is synchronized with LPADC3 6 4 Selects a target PWM which the PWM6 is synchronized with 0 PWM6_EN RW 0x0 Controls the permission s...

Page 474: ...Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PWM6_UPDATE Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 PWM6_UPDATE WO 0x0 Reflects a set value in PWM6 s operation by writing 1 on this register ...

Page 475: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM7_THRESH PWM7_CYCLE Bits Name Type Reset Value Description 31 16 PWM7_THRESH RW 0x0000 Sets the duty of PWM7 output 15 0 PWM7_CYCLE RW 0x0000 Sets the output cycle of PWM7 For formulas of the cycle and the DUTY refer to the below As for the formula of the PWM cycle refer to Section 3 9 11 2 1 and as for the formula of the DUTY period of HIGH cycle of the PWM outp...

Page 476: ...e PWM7 is synchronized with 000 is not synchronized with ADs 001 is synchronized with HPADC0 002 is synchronized with HPADC1 003 is synchronized with LPADC in operation 004 is synchronized with LPADC0 005 is synchronized with LPADC1 006 is synchronized with LPADC2 007 is synchronized with LPADC3 6 4 Selects a target PWM which the PWM7 is synchronized with 0 PWM7_EN RW 0x0 Controls the permission s...

Page 477: ...Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PWM7_UPDATE Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 PWM7_UPDATE WO 0x0 Reflects a set value in PWM7 s operation by writing 1 on this register ...

Page 478: ... Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM_CNTEN4 PWM_DELAY4 Bits Name Type Reset Value Description 31 16 PWM_CNTEN4 RW 0x0000 PWM4 setting for the control specification refer to PWM_CNTEN0 15 0 PWM_DELAY4 RW 0x0000 Adjusts phases for the timing of AD data capturing to SCU unit 0 65535 clock ...

Page 479: ... Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM_CNTEN5 PWM_DELAY5 Bits Name Type Reset Value Description 31 16 PWM_CNTEN5 RW 0x0000 PWM5 setting for the control specification refer to PWM_CNTEN0 15 0 PWM_DELAY5 RW 0x0000 Adjusts phases for the timing of AD data capturing to SCU unit 0 65535 clock ...

Page 480: ... Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM_CNTEN6 PWM_DELAY6 Bits Name Type Reset Value Description 31 16 PWM_CNTEN6 RW 0x0000 PWM6 setting for the control specification refer to PWM_CNTEN0 15 0 PWM_DELAY6 RW 0x0000 Adjusts phases for the timing of AD data capturing to SCU unit 0 65535 clock ...

Page 481: ... Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM_CNTEN7 PWM_DELAY7 Bits Name Type Reset Value Description 31 16 PWM_CNTEN7 RW 0x0000 PWM7 setting for the control specification refer to PWM_CNTEN0 15 0 PWM_DELAY7 RW 0x0000 Adjusts phases for the timing of AD data capturing to SCU unit 0 65535 clock ...

Page 482: ...pe Reset Value Description 31 16 TIMER1 RO 0x0000 Counter value of PWM1 15 0 TIMER0 RO 0x0000 Counter value of PWM0 3 9 12 3 187 0x5684 PWM_TIMER23 Details When the PWM is not used PWM generator can be used as a timer In this case counter values within the timer can be read Table SCU Sensor Control Unit 295 Local Address 0x5684 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25...

Page 483: ...pe Reset Value Description 31 16 TIMER5 RO 0x0000 Counter value of PWM5 15 0 TIMER4 RO 0x0000 Counter value of PWM4 3 9 12 3 189 0x568C PWM_TIMER67 Details When the PWM is not used PWM generator can be used as a timer In this case counter values within the timer can be read Table SCU Sensor Control Unit 297 Local Address 0x568C Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25...

Page 484: ...Description 31 24 PWM_SEL_INV3 RW 0x00 23 16 PWM_SEL_INV2 RW 0x00 15 8 PWM_SEL_INV1 RW 0x00 7 0 PWM_SEL_INV0 RW 0x00 3 9 12 3 191 0x5694 PWM_FUNC1 Details When synthesizing the PWM you can designate the polarity of the source PWM for PWM4 7 Table SCU Sensor Control Unit 299 Local Address 0x5694 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 485: ...SEL_DIS1 RW 0x00 7 0 PWM_SEL_DIS0 RW 0x00 3 9 12 3 193 0x569C PWM_FUNC3 Details When synthesizing the PWM you can designate whether to use the PWM or not for PWM4 7 Table SCU Sensor Control Unit 301 Local Address 0x569C Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM_SEL_DIS7 PWM_SEL_DIS6 PWM_SEL_DIS5 PWM_...

Page 486: ... 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM_SEL7PWM_SEL6PWM_SEL5PWM_SEL4PWM_SEL3PWM_SEL2PWM_SEL1PWM_SEL0 Bits Name Type Reset Value Description 31 28 PWM_SEL7 RW 0x0 Invalid setting 27 24 PWM_SEL6 RW 0x0 Invalid setting 23 20 PWM_SEL5 RW 0x0 Invalid setting 19 16 PWM_SEL4 RW 0x0 Invalid setting 15 12 PWM_SEL3 RW 0x0 For PWM3 unit 11 8 PWM_SEL2 RW 0x0 For PWM2 unit 7 4 PWM_SE...

Page 487: ...ntrol Unit 303 Local Address 0x56A4 Register Type RW read write Reset Value 0x0000FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved POWER_EN Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 POWER_EN RW 0xFFFF Prohibited setting ...

Page 488: ...set Value 0xxxxxxxxx Bits Name Type Reset Value Description 31 0 SEQ_IRAM RW 0xxxxxxxxx Instruction RAM array for internal sequencer 3 9 12 3 197 0x4000 0x4FFC SEQ_DRAM Details Data Ram array for internal sequencer Table SCU Sensor Control Unit 305 Local Address 0x4000 Memory Type RW read write Reset Value 0xxxxxxxxx Bits Name Type Reset Value Description 31 0 SEQ_DRAM RW 0xxxxxxxxx Data Ram array...

Page 489: ...can be seen from the sequencers in the SCU For calculating the address to access from the sequencer in the CPU add this address to each offset in the table Offset 0x0000e000 3 9 12 6 SCU_MATH_PROC_REG Register List Table SCU Sensor Control Unit 306 Offset Address Transaction Port Name Type Size bits Description Reset Value 0x0 MATH_PROC_EXE RO 32 0x00000000 0x4 WRITE_DATA_SET0 RW 32 0x00000000 0x8...

Page 490: ...should be executed or not 1 Performs MATH_PROC processing 0 4 8 to 15 bit only valid The following describes the conditions that the value of MATH_PROC_EXE becomes 1 0 4 bit When if any of the following 1 2 and 3 are true 1 When OFST_GAIN_EN 0x5070 of MATHID which you use is 1 2 When MATHFUNC_SEL 0x508c of MATHID which you use is set 3 When the set value for DECIMATION_PARAM0 1 0x5084 0x5088 of MA...

Page 491: ...C_ELE_NUM Reserved FIFO_W_ID Bits Name Type Reset Value Description 31 16 DATA_X RW 0x0000 Vector element X of the target data for processing request 15 10 Reserved RO 0x00 Reserved 9 8 VEC_ELE_NUM RW 0x0 The number of Vector element X of the target data for processing request 0 is equivalent to 1 element You can select one integer from 1 2 and 3 7 4 Reserved RO 0x0 Reserved 3 0 FIFO_W_ID RW 0x0 Y...

Page 492: ...8 7 6 5 4 3 2 1 0 DATA_Z DATA_Y Bits Name Type Reset Value Description 31 16 DATA_Z RW 0x0000 15 0 DATA_Y RW 0x0000 3 9 12 6 4 0xC WRITE_DATA_SET2 Details Table SCU Sensor Control Unit 310 Local Address 0xC Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GAIN_X OFST_X Bits Name Type Reset Value Description 31 ...

Page 493: ...8 7 6 5 4 3 2 1 0 GAIN_Y OFST_Y Bits Name Type Reset Value Description 31 16 GAIN_Y RW 0x0000 15 0 OFST_Y RW 0x0000 3 9 12 6 6 0x14 WRITE_DATA_SET4 Details Table SCU Sensor Control Unit 312 Local Address 0x14 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GAIN_Z OFST_Z Bits Name Type Reset Value Description 3...

Page 494: ...rite Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DATA_UPDATE Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 DATA_UPDATE RW 0x0 This can be set if some changes need to be made between WRITE_DATA_SET0 and WRITE_DATA_SET5 or if MATH is executed ...

Page 495: ... 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA_X Reserved VEC_ELE_NUM Reserved FIFO_W_ID Bits Name Type Reset Value Description 31 16 DATA_X RO 0x0000 15 10 Reserved RO 0x00 Reserved 9 8 VEC_ELE_NUM RO 0x0 7 4 Reserved RO 0x0 Reserved 3 0 FIFO_W_ID RO 0x0 MATH ID from 0 to 15 which is requested to process is output The order in which the MATH ID is output is not the same as the order of t...

Page 496: ...1 0 DATA_Z DATA_Y Bits Name Type Reset Value Description 31 16 DATA_Z RO 0x0000 15 0 DATA_Y RO 0x0000 3 9 12 6 10 0x88 READ_DATA_SET2 Details Table SCU Sensor Control Unit 316 Local Address 0x88 Register Type WO write only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DATA_READ_DONE Bits Name Type Reset Value Description 31 1 ...

Page 497: ...x0000e400 3 9 12 8 SCU_SEQ_REG Register List Table SCU Sensor Control Unit 317 Offset Address Transaction Port Name Type Size bits Description Reset Value 0x0 EXTERNAL_STT0 RO 32 0x00000000 0x4 EXTERNAL_STT1 RO 32 0x00000000 0x8 START_CTRL WO 32 0x00000000 0x10 ISOPSTT RW 32 0x00000000 0x14 ISOPINT RW 32 0x00000000 0x18 POWER_CTRL RW 32 0x00000000 0x20 TIME_STAMP_MSB RO 32 0x00000000 0x24 TIME_STA...

Page 498: ...me Type Reset Value Description 31 TIMER_INT2 RO 0x0 30 TIMER_INT1 RO 0x0 29 TIMER_INT0 RO 0x0 28 FIFO1_ALL_ON_STT RO 0x0 Indicates that the power supply state of FIFO SRAM 32KByte region is All On 27 FIFO0_ALL_ON_STT RO 0x0 Indicates that the power supply state of FIFO SRAM 8KByte region is All On 26 MATH_PROC_READ_DATA_R EADY RO 0x0 Indicates the status that the readout from MATH_PROC is possibl...

Page 499: ...OST_FULL RO 0x0 Indicates that more data than designated exist in the RX FIFO of I2C1 15 I2C0_ACTIVE RO 0x0 Indicates the operation active status of I2C0 14 I2C0_MASTER_ON_HOLD RO 0x0 Indicates that the status is I2C0 TX_FIFO Empty but a STOP command has not been issued 13 I2C0_RX_ALMOST_FULL RO 0x0 Indicates that more data than designated exist in the RX FIFO of I2C0 12 PWD_I2C_ON_STT RO 0x0 Powe...

Page 500: ...1 RO 0x0 28 24 I2C1_FSM_STATUS RO 0x00 FSM status of I2C1 23 21 Reserved RO 0x0 Reserved 20 16 I2C0_FSM_STATUS RO 0x00 FSM status of I2C0 15 13 MATH_EVENT_F RO 0x0 The status of Math Function interrupt to the CPU 12 10 MATH_EVENT_R RO 0x0 The status of Math Function interrupt to the CPU 9 APB_ACCESS_ERR RO 0x0 Indicates 1 when APB error occurs 8 DRAM_ALL_ON_STT RO 0x0 Indicates the power supply st...

Page 501: ... 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EXE_ERR Reserved EXE_DONE Bits Name Type Reset Value Description 31 26 Reserved WO 0x00 Reserved 25 16 EXE_ERR WO 0x000 Indicates error notification of each sequencer when executed 15 10 Reserved WO 0x00 Reserved 9 0 EXE_DONE WO 0x000 Indicates execution completed notification of each sequencer ...

Page 502: ... Type Reset Value Description 31 LPADC_ACCESS_INHIBIT_ACK3 RW 0x0 30 LPADC_ACCESS_INHIBIT_ACK2 RW 0x0 29 LPADC_ACCESS_INHIBIT_ACK1 RW 0x0 28 17 Reserved RO 0x000 Reserved 16 ISOP_READY RW 0x0 Indicates 1 when the boot of the internal sequencer has been completed 15 6 Reserved RO 0x000 Reserved 5 HPADC1_ACCESS_INHIBIT_ACK RW 0x0 ACK output in response to the INHIBIT request 4 HPADC0_ACCESS_INHIBIT_...

Page 503: ...4 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ISOP_INT Bits Name Type Reset Value Description 31 4 Reserved RO 0x0000000 Reserved 3 0 ISOP_INT RW 0x0 Information interrupt output to the CPU used for SW definition ...

Page 504: ...5 Reserved RO 0x00 Reserved 24 APB_ACCESS_ERR_CLR WO 0x0 Clear the APB_ACCESS_ERR in EXTERNAL_STT1 23 18 Reserved RO 0x00 Reserved 17 FIFO1_RETENTION_REQ RW 0x0 Requests for the retention of the power supply status of FIFO SRAM 32 KByte region 16 FIFO0_RETENTION_REQ RW 0x0 Requests for the retention of the power supply status of FIFO SRAM 8 KByte region 15 10 Reserved RO 0x00 Reserved 9 FIFO1_ALL_...

Page 505: ... Value Description 31 0 TIME_STAMP_46_15 RO 0x00000000 Time stamp information with 47 bit data width on the MSB side 3 9 12 8 8 0x24 TIME_STAMP_LSB Details Table SCU Sensor Control Unit 325 Local Address 0x24 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIME_STAMP_31_0 Bits Name Type Reset Value Description ...

Page 506: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MON1 Reserved MON0 Bits Name Type Reset Value Description 31 26 Reserved RO 0x00 Reserved 25 16 MON1 RW 0x000 Indicates debug monitor output for the external pin output 15 10 Reserved RO 0x00 Reserved 9 0 MON0 RW 0x000 Indicates debug monitor output for the external pin output ...

Page 507: ...K_EN Bits Name Type Reset Value Description 31 5 Reserved RO 0x0000000 Reserved 4 0 CLK_EN RW 0x00 3 9 12 8 11 0x190 TIMER_SEL Details Table SCU Sensor Control Unit 328 Local Address 0x190 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIMWE_SEL2 TIMWE_SEL1 TIMWE_SEL0 Bits Name Type Reset Value Descr...

Page 508: ..._S_TIMSTAMP0 RO 32 0x00000000 0x10 D0_W0_S_TIMSTAMP1 RO 32 0x00000000 0x20 D0_W1_S_CTRL0 RW 32 0xA0000000 0x24 D0_W1_S_CTRL1 RW 32 0x00000000 0x28 D0_W1_S_STATUS RO 32 0x00000000 0x2C D0_W1_S_TIMSTAMP0 RO 32 0x00000000 0x30 D0_W1_S_TIMSTAMP1 RO 32 0x00000000 0x40 D0_W2_S_CTRL0 RW 32 0xA0000000 0x44 D0_W2_S_CTRL1 RW 32 0x00000000 0x48 D0_W2_S_STATUS RO 32 0x00000000 0x4C D0_W2_S_TIMSTAMP0 RO 32 0x0...

Page 509: ...0000 0x100 N0_W_S_CTRL0 RW 32 0xA0000000 0x104 N0_W_S_CTRL1 RW 32 0x00000000 0x108 N0_W_S_STATUS RO 32 0x00000000 0x10C N0_W_S_TIMSTAMP0 RO 32 0x00000000 0x110 N0_W_S_TIMSTAMP1 RO 32 0x00000000 0x120 N1_W_S_CTRL0 RW 32 0xA0000000 0x124 N1_W_S_CTRL1 RW 32 0x00000000 0x128 N1_W_S_STATUS RO 32 0x00000000 0x12C N1_W_S_TIMSTAMP0 RO 32 0x00000000 0x130 N1_W_S_TIMSTAMP1 RO 32 0x00000000 0x140 N2_W_S_CTRL...

Page 510: ...STAMP0 RO 32 0x00000000 0x1F0 N7_W_S_TIMSTAMP1 RO 32 0x00000000 0x200 V0_W_C_CTRL0 RW 32 0xA0000000 0x204 V0_W_C_CTRL1 RW 32 0x00000000 0x208 V0_W_C_STATUS RO 32 0x00000000 0x20C V0_W_C_TIMSTAMP0 RO 32 0x00000000 0x210 V0_W_C_TIMSTAMP1 RO 32 0x00000000 0x214 V0_W_C_TIMSTAMP_SET0 RW 32 0x00000000 0x218 V0_W_C_TIMSTAMP_SET1 RW 32 0x00000000 0x220 V1_W_C_CTRL0 RW 32 0xA0000000 0x224 V1_W_C_CTRL1 RW 3...

Page 511: ...x2A4 V5_W_C_CTRL1 RW 32 0x00000000 0x2A8 V5_W_C_STATUS RO 32 0x00000000 0x2AC V5_W_C_TIMSTAMP0 RO 32 0x00000000 0x2B0 V5_W_C_TIMSTAMP1 RO 32 0x00000000 0x2B4 V5_W_C_TIMSTAMP_SET0 RW 32 0x00000000 0x2B8 V5_W_C_TIMSTAMP_SET1 RW 32 0x00000000 0x2C0 V6_W_C_CTRL0 RW 32 0xA0000000 0x2C4 V6_W_C_CTRL1 RW 32 0x00000000 0x2C8 V6_W_C_STATUS RO 32 0x00000000 0x2CC V6_W_C_TIMSTAMP0 RO 32 0x00000000 0x2D0 V6_W_...

Page 512: ...0 D0_R1_C_TIMSTAMP0 RO 32 0x00000000 0x1014 D0_R1_C_TIMSTAMP1 RO 32 0x00000000 0x1020 D0_R2_C_CTRL0 RW 32 0x0000FFFF 0x1024 D0_R2_C_CTRL1 RW 32 0x00000000 0x1028 D0_R2_C_STATUS0 RO 32 0x00000000 0x102C D0_R2_C_STATUS1 RO 32 0x00000000 0x1030 D0_R2_C_TIMSTAMP0 RO 32 0x00000000 0x1034 D0_R2_C_TIMSTAMP1 RO 32 0x00000000 0x1040 D1_R1_C_CTRL0 RW 32 0x0000FFFF 0x1044 D1_R1_C_CTRL1 RW 32 0x00000000 0x104...

Page 513: ...0x10E0 N3_R1_C_CTRL0 RW 32 0x0000FFFF 0x10E4 N3_R1_C_CTRL1 RW 32 0x00000000 0x10E8 N3_R1_C_STATUS0 RO 32 0x00000000 0x10EC N3_R1_C_STATUS1 RO 32 0x00000000 0x10F0 N3_R1_C_TIMSTAMP0 RO 32 0x00000000 0x10F4 N3_R1_C_TIMSTAMP1 RO 32 0x00000000 0x1100 N4_R1_C_CTRL0 RW 32 0x0000FFFF 0x1104 N4_R1_C_CTRL1 RW 32 0x00000000 0x1108 N4_R1_C_STATUS0 RO 32 0x00000000 0x110C N4_R1_C_STATUS1 RO 32 0x00000000 0x11...

Page 514: ...A8 D1_R3_CH_STATUS0 RO 32 0x00000000 0x11AC D1_R3_CH_STATUS1 RO 32 0x00000000 0x11B0 D1_R3_CH_TIMSTAMP0 RO 32 0x00000000 0x11B4 D1_R3_CH_TIMSTAMP1 RO 32 0x00000000 0x11C0 D0_R0_H_CTRL0 RW 32 0x0000FFFF 0x11C4 D0_R0_H_CTRL1 RW 32 0x00000000 0x11C8 D0_R0_H_STATUS0 RO 32 0x00000000 0x11CC D0_R0_H_STATUS1 RO 32 0x00000000 0x11D0 D0_R0_H_TIMSTAMP0 RO 32 0x00000000 0x11D4 D0_R0_H_TIMSTAMP1 RO 32 0x00000...

Page 515: ... N3_R0_H_TIMSTAMP0 RO 32 0x00000000 0x1274 N3_R0_H_TIMSTAMP1 RO 32 0x00000000 0x1280 N4_R0_H_CTRL0 RW 32 0x0000FFFF 0x1284 N4_R0_H_CTRL1 RW 32 0x00000000 0x1288 N4_R0_H_STATUS0 RO 32 0x00000000 0x128C N4_R0_H_STATUS1 RO 32 0x00000000 0x1290 N4_R0_H_TIMSTAMP0 RO 32 0x00000000 0x1294 N4_R0_H_TIMSTAMP1 RO 32 0x00000000 0x12A0 N5_R0_H_CTRL0 RW 32 0x0000FFFF 0x12A4 N5_R0_H_CTRL1 RW 32 0x00000000 0x12A8...

Page 516: ...0000 0x1340 V2_R_H_CTRL0 RW 32 0x0000FFFF 0x1344 V2_R_H_CTRL1 RW 32 0x00000000 0x1348 V2_R_H_STATUS0 RO 32 0x00000000 0x134C V2_R_H_STATUS1 RO 32 0x00000000 0x1350 V2_R_H_TIMSTAMP0 RO 32 0x00000000 0x1354 V2_R_H_TIMSTAMP1 RO 32 0x00000000 0x1360 V3_R_H_CTRL0 RW 32 0x0000FFFF 0x1364 V3_R_H_CTRL1 RW 32 0x00000000 0x1368 V3_R_H_STATUS0 RO 32 0x00000000 0x136C V3_R_H_STATUS1 RO 32 0x00000000 0x1370 V3...

Page 517: ...32 0x00000000 0x13EC V7_R_H_STATUS1 RO 32 0x00000000 0x13F0 V7_R_H_TIMSTAMP0 RO 32 0x00000000 0x13F4 V7_R_H_TIMSTAMP1 RO 32 0x00000000 0x1400 V8_R_H_CTRL0 RW 32 0x0000FFFF 0x1404 V8_R_H_CTRL1 RW 32 0x00000000 0x1408 V8_R_H_STATUS0 RO 32 0x00000000 0x140C V8_R_H_STATUS1 RO 32 0x00000000 0x1410 V8_R_H_TIMSTAMP0 RO 32 0x00000000 0x1414 V8_R_H_TIMSTAMP1 RO 32 0x00000000 0x1420 V9_R_H_CTRL0 RW 32 0x000...

Page 518: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_ OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITI ON_SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 519: ...000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 13 Reserved RO 0x0 Reserved 12 ENABLE_ADC_ INTERVAL RW 0x0 Uses ADC_INTERVAL instead of PRE_DIVIDER 11 8 ADC_INTERVA L RW 0x0 When ENABLE_ADC_INTERVAL is 1 ADC_INTERVAL is used as a sampling interval instead of PRE_DIVIDER Note ADC_INTERVAL must be bigger than 1 7 5 Reserved RO 0x0 Reserved 4 OVERWRITE_IF _FULL ...

Page 520: ...7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicate...

Page 521: ...p integer part of second Time stamp which supports the newest data in the FIFO by second unit 3 9 12 10 5 0x10 D0_W0_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 334 Local Address 0x10 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 15...

Page 522: ... 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 523: ...O_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_IF_F ULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE_SIZ E RW 0x0 Number of...

Page 524: ... 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicat...

Page 525: ...amp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 10 0x30 D0_W1_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 339 Local Address 0x30 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 15...

Page 526: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 527: ...FO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_IF_F ULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO Full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE_SIZ E RW 0x0 Number o...

Page 528: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 529: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 15 0x50 D0_W2_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 344 Local Address 0x50 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 1...

Page 530: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 531: ...FO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_IF_F ULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE_SIZ E RW 0x0 Number o...

Page 532: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 533: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 20 0x70 D0_W3_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 349 Local Address 0x70 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 1...

Page 534: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 535: ...7 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 13 Reserved RO 0x0 Reserved 12 ENABLE_ADC_ INTERVAL RW 0x0 Uses ADC_INTERVAL instead of PRE_DIVIDER 11 8 ADC_INTERVA L RW 0x0 ADC_INTERVAL is used as a sampling interval instead of PRE_DIVIDER Note ADC_INTERVAL must be bigger than 1 7 5 Reserved RO 0x0 Reserved 4 OVERWRITE_IF _FULL RW 0x0 OVERWR...

Page 536: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 537: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 25 0x90 D1_W0_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 354 Local Address 0x90 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 1...

Page 538: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 539: ...FO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_IF_F ULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE_SIZ E RW 0x0 Number o...

Page 540: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 541: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 30 0xB0 D1_W1_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 359 Local Address 0xB0 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 1...

Page 542: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 543: ...FO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_ IF_FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE _SIZE RW 0x0 Number o...

Page 544: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 545: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 35 0xD0 D1_W2_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 364 Local Address 0xD0 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 1...

Page 546: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 547: ...FO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_ IF_FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE _SIZE RW 0x0 Number o...

Page 548: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 549: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 40 0xF0 D1_W3_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 369 Local Address 0xF0 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 1...

Page 550: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 551: ...7 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 13 Reserved RO 0x0 Reserved 12 ENABLE_ADC_ INTERVAL RW 0x0 Uses ADC_INTERVAL instead of PRE_DIVIDER 11 8 ADC_INTERVA L RW 0x0 ADC_INTERVAL is used as a sampling interval instead of PRE_DIVIDER Note ADC_INTERVAL must be bigger than 1 7 5 Reserved RO 0x0 Reserved 4 OVERWRITE_IF _FULL RW 0x0 OVERWR...

Page 552: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 553: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 45 0x110 N0_W_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 374 Local Address 0x110 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 ...

Page 554: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 555: ...7 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 13 Reserved RO 0x0 Reserved 12 ENABLE_ADC_ INTERVAL RW 0x0 Uses ADC_INTERVAL instead of PRE_DIVIDER 11 8 ADC_INTERVA L RW 0x0 ADC_INTERVAL is used as a sampling interval instead of PRE_DIVIDER Note ADC_INTERVAL must be bigger than 1 7 5 Reserved RO 0x0 Reserved 4 OVERWRITE_IF _FULL RW 0x0 OVERWR...

Page 556: ... 8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_PHAS E RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 557: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 50 0x130 N1_W_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 379 Local Address 0x130 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 ...

Page 558: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 559: ...7 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 13 Reserved RO 0x0 Reserved 12 ENABLE_ADC_ INTERVAL RW 0x0 Uses ADC_INTERVAL instead of PRE_DIVIDER 11 8 ADC_INTERVA L RW 0x0 ADC_INTERVAL is used as a sampling interval instead of PRE_DIVIDER Note ADC_INTERVAL must be bigger than 1 7 5 Reserved RO 0x0 Reserved 4 OVERWRITE_IF _FULL RW 0x0 OVERWR...

Page 560: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 561: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 55 0x150 N2_W_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 384 Local Address 0x150 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 ...

Page 562: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 563: ...7 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 13 Reserved RO 0x0 Reserved 12 ENABLE_ADC_ INTERVAL RW 0x0 Uses ADC_INTERVAL instead of PRE_DIVIDER 11 8 ADC_INTERVA L RW 0x0 ADC_INTERVAL is used as a sampling interval instead of PRE_DIVIDER Note ADC_INTERVAL must be bigger than 1 7 5 Reserved RO 0x0 Reserved 4 OVERWRITE_IF _FULL RW 0x0 OVERWR...

Page 564: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 565: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 60 0x170 N3_W_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 389 Local Address 0x170 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 ...

Page 566: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 567: ...7 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 13 Reserved RO 0x0 Reserved 12 ENABLE_ADC_ INTERVAL RW 0x0 Uses ADC_INTERVAL instead of PRE_DIVIDER 11 8 ADC_INTERVA L RW 0x0 ADC_INTERVAL is used as a sampling interval instead of PRE_DIVIDER Note ADC_INTERVAL must be bigger than 1 7 5 Reserved RO 0x0 Reserved 4 OVERWRITE_IF _FULL RW 0x0 OVERWR...

Page 568: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 569: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 65 0x190 N4_W_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 394 Local Address 0x190 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 ...

Page 570: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 571: ...7 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 13 Reserved RO 0x0 Reserved 12 ENABLE_ADC_ INTERVAL RW 0x0 Uses ADC_INTERVAL instead of PRE_DIVIDER 11 8 ADC_INTERVA L RW 0x0 ADC_INTERVAL is used as a sampling interval instead of PRE_DIVIDER Note ADC_INTERVAL must be bigger than 1 7 5 Reserved RO 0x0 Reserved 4 OVERWRITE_IF _FULL RW 0x0 OVERWR...

Page 572: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 573: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 70 0x1B0 N5_W_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 399 Local Address 0x1B0 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 ...

Page 574: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 575: ...7 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 13 Reserved RO 0x0 Reserved 12 ENABLE_ADC_ INTERVAL RW 0x0 Uses ADC_INTERVAL instead of PRE_DIVIDER 11 8 ADC_INTERVA L RW 0x0 ADC_INTERVAL is used as a sampling interval instead of PRE_DIVIDER Note ADC_INTERVAL must be bigger than 1 7 5 Reserved RO 0x0 Reserved 4 OVERWRITE_IF _FULL RW 0x0 OVERWR...

Page 576: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 577: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 75 0x1D0 N6_W_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 404 Local Address 0x1D0 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 ...

Page 578: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 579: ...7 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 13 Reserved RO 0x0 Reserved 12 ENABLE_ADC_ INTERVAL RW 0x0 Uses ADC_INTERVAL instead of PRE_DIVIDER 11 8 ADC_INTERVA L RW 0x0 ADC_INTERVAL is used as a sampling interval instead of PRE_DIVIDER Note ADC_INTERVAL must be bigger than 1 7 5 Reserved RO 0x0 Reserved 4 OVERWRITE_IF _FULL RW 0x0 OVERWR...

Page 580: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 581: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 80 0x1F0 N7_W_S_TIMSTAMP1 Details Table SCU Sensor Control Unit 409 Local Address 0x1F0 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 ...

Page 582: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 583: ...FO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_ IF_FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE _SIZE RW 0x0 Number o...

Page 584: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 585: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 85 0x210 V0_W_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 414 Local Address 0x210 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 ...

Page 586: ...sor Control Unit 416 Local Address 0x218 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIME_STAMP_INTERVAL Reserved LATEST_BASE_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 16 TIME_STAMP_INT ERVAL RW 0x0000 Time stamp interval virtual sensor partition only TIME...

Page 587: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 588: ...FO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_ IF_FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE _SIZE RW 0x0 Number o...

Page 589: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 590: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 92 0x230 V1_W_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 421 Local Address 0x230 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 ...

Page 591: ...sor Control Unit 423 Local Address 0x238 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIME_STAMP_INTERVAL Reserved LATEST_BASE_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 16 TIME_STAMP_INT ERVAL RW 0x0000 Time stamp interval virtual sensor partition only TIME...

Page 592: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_ OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITI ON_SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 593: ...FO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_ IF_FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO Full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE _SIZE RW 0x0 Number o...

Page 594: ...8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indica...

Page 595: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 99 0x250 V2_W_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 428 Local Address 0x250 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 ...

Page 596: ...nsor Control Unit 430 Local Address 0x258 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIME_STAMP_INTERVAL Reserved LATEST_BASE_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 16 TIME_STAMP_IN TERVAL RW 0x0000 Time stamp interval virtual sensor partition only TIM...

Page 597: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 598: ...IFO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_ IF_FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO Full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE _SIZE RW 0x0 Number ...

Page 599: ... 8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indic...

Page 600: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 106 0x270 V3_W_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 435 Local Address 0x270 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31...

Page 601: ...nsor Control Unit 437 Local Address 0x278 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIME_STAMP_INTERVAL Reserved LATEST_BASE_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 16 TIME_STAMP_INT ERVAL RW 0x0000 Time stamp interval virtual sensor partition only TIM...

Page 602: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_ OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITI ON_SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 603: ...IFO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_ IF_FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO Full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE _SIZE RW 0x0 Number ...

Page 604: ... 8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indic...

Page 605: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 113 0x290 V4_W_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 442 Local Address 0x290 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31...

Page 606: ...nsor Control Unit 444 Local Address 0x298 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIME_STAMP_INTERVAL Reserved LATEST_BASE_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 16 TIME_STAMP_IN TERVAL RW 0x0000 Time stamp interval virtual sensor partition only TIM...

Page 607: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 608: ...IFO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_ IF_FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO Full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE _SIZE RW 0x0 Number ...

Page 609: ... 8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indic...

Page 610: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 120 0x2B0 V5_W_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 449 Local Address 0x2B0 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31...

Page 611: ...nsor Control Unit 451 Local Address 0x2B8 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIME_STAMP_INTERVAL Reserved LATEST_BASE_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 16 TIME_STAMP_IN TERVAL RW 0x0000 Time stamp interval virtual sensor partition only TIM...

Page 612: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 613: ...IFO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_ IF_FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO Full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE _SIZE RW 0x0 Number ...

Page 614: ... 8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indic...

Page 615: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 127 0x2D0 V6_W_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 456 Local Address 0x2D0 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31...

Page 616: ...nsor Control Unit 458 Local Address 0x2D8 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIME_STAMP_INTERVAL Reserved LATEST_BASE_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 16 TIME_STAMP_INT ERVAL RW 0x0000 Time stamp interval virtual sensor partition only TIM...

Page 617: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 618: ...IFO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_ IF_FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO Full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE _SIZE RW 0x0 Number ...

Page 619: ... 8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indic...

Page 620: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 134 0x2F0 V7_W_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 463 Local Address 0x2F0 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31...

Page 621: ...nsor Control Unit 465 Local Address 0x2F8 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIME_STAMP_INTERVAL Reserved LATEST_BASE_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 16 TIME_STAMP_IN TERVAL RW 0x0000 Time stamp interval virtual sensor partition only TIM...

Page 622: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 623: ...IFO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_ IF_FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO Full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE _SIZE RW 0x0 Number ...

Page 624: ... 8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indic...

Page 625: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 141 0x310 V8_W_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 470 Local Address 0x310 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31...

Page 626: ...nsor Control Unit 472 Local Address 0x318 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIME_STAMP_INTERVAL Reserved LATEST_BASE_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 16 TIME_STAMP_IN TERVAL RW 0x0000 Time stamp interval virtual sensor partition only TIM...

Page 627: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_START_OFST FIFO_PARTITION_SIZE Bits Name Type Reset Value Description 31 16 FIFO_START_OFST RW 0xA000 Start address offset Means the start address offset of the RAM for the FIFO by Byte unit 15 0 FIFO_PARTITION_ SIZE RW 0x0000 Partition size 1 Sets partition size minus 1 by Sample unit ...

Page 628: ...IFO_RESETReserved OVERWRITE_IF_FULL FIFO_SAMPLE_SIZE Bits Name Type Reset Value Description 31 17 Reserved RO 0x0000 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO Clears the writing pointer to 0 15 5 Reserved RO 0x000 Reserved 4 OVERWRITE_IF _FULL RW 0x0 OVERWRITE_IF_FULL overview Sets whether to overwrite or not at FIFO Full 0 does not overwrite 1 overwrites 3 0 FIFO_SAMPLE_ SIZE RW 0x0 Number ...

Page 629: ... 8 7 6 5 4 3 2 1 0 FIFO_WRITE_PTR Reserved FIFO_WRITE_PHASE Bits Name Type Reset Value Description 31 16 FIFO_WRITE_ PTR RO 0x0000 Writing pointer address of the FIFO The start address where the next data is written by Byte unit 15 4 Reserved RO 0x000 Reserved 3 0 FIFO_WRITE_ PHASE RO 0x0 Write phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indic...

Page 630: ...tamp integer part of second Time stamp which supports the newest data in the FIFO Second unit 3 9 12 10 148 0x330 V9_W_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 477 Local Address 0x330 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATEST_TIMESTAMP_LSB Bits Name Type Reset Value Description 31...

Page 631: ...nsor Control Unit 479 Local Address 0x338 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIME_STAMP_INTERVAL Reserved LATEST_BASE_TIMESTAMP_LSB Bits Name Type Reset Value Description 31 Reserved RO 0x0 Reserved 30 16 TIME_STAMP_IN TERVAL RW 0x0000 Time stamp interval virtual sensor partition only TIM...

Page 632: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_ MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 633: ... output is fixed to 0 24 FIFO_ENAB LE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 634: ...Table SCU Sensor Control Unit 482 Local Address 0x1008 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO Number of sample unit ...

Page 635: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 636: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 156 0x1014 D0_R1_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 485 Local Address 0x1014 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 637: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 638: ... output is fixed to 0 24 FIFO_ENAB LE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 639: ...rol Unit 488 Local Address 0x1028 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number ...

Page 640: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 641: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 162 0x1034 D0_R2_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 491 Local Address 0x1034 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 642: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 643: ... output is fixed to 0 24 FIFO_ENAB LE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 644: ...rol Unit 494 Local Address 0x1048 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number ...

Page 645: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 646: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 168 0x1054 D1_R1_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 497 Local Address 0x1054 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 647: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 648: ... output is fixed to 0 24 FIFO_ENAB LE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 649: ...rol Unit 500 Local Address 0x1068 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number ...

Page 650: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 651: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 174 0x1074 D1_R2_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 503 Local Address 0x1074 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 652: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 653: ...e output is fixed to 0 24 FIFO_ENABLE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 654: ...rol Unit 506 Local Address 0x1088 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number ...

Page 655: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 656: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 180 0x1094 N0_R1_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 509 Local Address 0x1094 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 657: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 658: ...e output is fixed to 0 24 FIFO_ENABLE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 659: ...rol Unit 512 Local Address 0x10A8 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number ...

Page 660: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 661: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 186 0x10B4 N1_R1_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 515 Local Address 0x10B4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 662: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 663: ...e output is fixed to 0 24 FIFO_ENABLE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 664: ...rol Unit 518 Local Address 0x10C8 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number ...

Page 665: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 666: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 192 0x10D4 N2_R1_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 521 Local Address 0x10D4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 667: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 668: ...e output is fixed to 0 24 FIFO_ENABLE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 669: ...rol Unit 524 Local Address 0x10E8 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number ...

Page 670: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 671: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 198 0x10F4 N3_R1_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 527 Local Address 0x10F4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 672: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 673: ...e output is fixed to 0 24 FIFO_ENABLE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 674: ...rol Unit 530 Local Address 0x1108 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number ...

Page 675: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 676: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 204 0x1114 N4_R1_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 533 Local Address 0x1114 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 677: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 678: ...e output is fixed to 0 24 FIFO_ENABLE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 679: ...rol Unit 536 Local Address 0x1128 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number ...

Page 680: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 681: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 210 0x1134 N5_R1_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 539 Local Address 0x1134 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 682: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 683: ...e output is fixed to 0 24 FIFO_ENABLE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 684: ...rol Unit 542 Local Address 0x1148 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number ...

Page 685: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 686: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 216 0x1154 N6_R1_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 545 Local Address 0x1154 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 687: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 688: ...e output is fixed to 0 24 FIFO_ENABLE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset of the FIFO The value of the readout pointer is forced to set the same val...

Page 689: ...rol Unit 548 Local Address 0x1168 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number ...

Page 690: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 691: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 222 0x1174 N7_R1_C_TIMSTAMP1 Details Table SCU Sensor Control Unit 551 Local Address 0x1174 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 692: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 693: ...s fixed to 0 24 FIFO_ENABLE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset the readout pointer for the FIFO The value of the readout pointer is forced to set t...

Page 694: ...trol Unit 554 Local Address 0x1188 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number...

Page 695: ...READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 F...

Page 696: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 228 0x1194 D0_R3_CH_TIMSTAMP1 Details Table SCU Sensor Control Unit 557 Local Address 0x1194 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Desc...

Page 697: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 698: ...s fixed to 0 24 FIFO_ENABLE RW 0x0 Operation permission of the FIFO readout function When 1 is indicated the operation is permitted When 0 is indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset the readout pointer for the FIFO The value of the readout pointer is forced to set t...

Page 699: ...trol Unit 560 Local Address 0x11A8 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number...

Page 700: ...READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 F...

Page 701: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 234 0x11B4 D1_R3_CH_TIMSTAMP1 Details Table SCU Sensor Control Unit 563 Local Address 0x11B4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Desc...

Page 702: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 703: ...the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset the readout pointer for the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_ RESET WO 0x0 Reset of the readout pointer for the FIFO If the readout ...

Page 704: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 705: ...READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 F...

Page 706: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 240 0x11D4 D0_R0_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 569 Local Address 0x11D4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 707: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 708: ...the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Reset the readout pointer for the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_ RESET WO 0x0 Reset of the readout pointer for the FIFO If the readout ...

Page 709: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 710: ...READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 F...

Page 711: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 246 0x11F4 D1_R0_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 575 Local Address 0x11F4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 712: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 713: ... indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is...

Page 714: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 715: ...O_READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3...

Page 716: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 252 0x1214 N0_R0_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 581 Local Address 0x1214 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 717: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 718: ... indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is...

Page 719: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 720: ...READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 F...

Page 721: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 258 0x1234 N1_R0_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 587 Local Address 0x1234 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 722: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 723: ... indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is...

Page 724: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 725: ...READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 F...

Page 726: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 264 0x1254 N2_R0_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 593 Local Address 0x1254 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 727: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 728: ... indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is...

Page 729: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 730: ...READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 F...

Page 731: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 270 0x1274 N3_R0_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 599 Local Address 0x1274 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 732: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 733: ... indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is...

Page 734: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 735: ...READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 F...

Page 736: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 276 0x1294 N4_R0_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 605 Local Address 0x1294 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 737: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 738: ... indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_RE SET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is...

Page 739: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 740: ...READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 F...

Page 741: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 282 0x12B4 N5_R0_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 611 Local Address 0x12B4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 742: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 743: ... indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is...

Page 744: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 745: ...READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 F...

Page 746: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 288 0x12D4 N6_R0_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 617 Local Address 0x12D4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 747: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding registe...

Page 748: ... indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is...

Page 749: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 750: ...READ_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 F...

Page 751: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 294 0x12F4 N7_R0_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 623 Local Address 0x12F4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descr...

Page 752: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding register...

Page 753: ...indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is ...

Page 754: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 755: ...EAD_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 FI...

Page 756: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 300 0x1314 V0_R_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 629 Local Address 0x1314 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descri...

Page 757: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding register...

Page 758: ...indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is ...

Page 759: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 760: ...EAD_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 FI...

Page 761: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 306 0x1334 V1_R_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 635 Local Address 0x1334 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descri...

Page 762: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding register...

Page 763: ...indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is ...

Page 764: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 765: ...EAD_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 FI...

Page 766: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 312 0x1354 V2_R_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 641 Local Address 0x1354 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descri...

Page 767: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding register...

Page 768: ...indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is ...

Page 769: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 770: ...EAD_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 FI...

Page 771: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 318 0x1374 V3_R_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 647 Local Address 0x1374 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descri...

Page 772: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding register...

Page 773: ...indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is ...

Page 774: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 775: ...EAD_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 FI...

Page 776: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 324 0x1394 V4_R_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 653 Local Address 0x1394 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descri...

Page 777: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding register...

Page 778: ...indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is ...

Page 779: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 780: ...EAD_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 FI...

Page 781: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 330 0x13B4 V5_R_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 659 Local Address 0x13B4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descri...

Page 782: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding register...

Page 783: ...indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is ...

Page 784: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 785: ...EAD_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 FI...

Page 786: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 336 0x13D4 V6_R_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 665 Local Address 0x13D4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descri...

Page 787: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding register...

Page 788: ...indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_RE SET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is ...

Page 789: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 790: ...EAD_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 FI...

Page 791: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 342 0x13F4 V7_R_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 671 Local Address 0x13F4 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descri...

Page 792: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding register...

Page 793: ...indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is ...

Page 794: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 795: ...EAD_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 FI...

Page 796: ... of second Register for reading out the data in the FIFO Can read out the earliest data in the FIFO 3 9 12 10 348 0x1414 V8_R_H_TIMSTAMP1 Details Table SCU Sensor Control Unit 677 Local Address 0x1414 Register Type RO read only Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OLDEST_TIMESTAMP_LSB Bits Name Type Reset Value Descri...

Page 797: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WATER_MARK Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 WATER_MARK RW 0xFFFF Watermark value sample unit for interrupt DMA control When the number of valid data in the FIFO is the same as the value or more an interrupt occurs a request for DMA transfer begins The interrupt request only occurs when the corresponding register...

Page 798: ...indicated the function operates in a way that the readout side does not recognize that data is written to the FIFO 23 17 Reserved RO 0x00 Reserved 16 FIFO_RESET WO 0x0 Clear of the FIFO The value of the readout pointer is forced to set the same value of the writing pointer 15 9 Reserved RO 0x00 Reserved 8 FIFO_PHASE_R ESET WO 0x0 Reset of the readout pointer for the FIFO If the readout pointer is ...

Page 799: ...y Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_AVAIABLE_DATA_NUM Bits Name Type Reset Value Description 31 16 Reserved RO 0x0000 Reserved 15 0 FIFO_AVAIABLE_ DATA_NUM RO 0x0000 The number of data stored in the FIFO The number of data remaining in the FIFO Number of sample unit ...

Page 800: ...EAD_ PHASE RO 0x0 Readout phase of the data in the FIFO The data position in a sample data stored in the FIFO by Byte unit 0 indicates that it is delimited of the sample data 7 6 Reserved RO 0x0 Reserved 5 FIFO_EMPT Y_BYTE RO 0x0 Indicates 1 when the number of the valid data byte in the FIFO is 0 4 FIFO_EMPT Y_SAMPLE RO 0x0 Indicates 1 when the number of the valid data sample in the FIFO is 0 3 FI...

Page 801: ...equencer n n 0 9 SEQ_OUT_FORMAT_n 0x0024 n x 0x20 RW Output format setting of sequencer n n 0 9 SEQ_MATH_PROC_OFST_GAIN_n _m 0x0028 n x 0x04 m x 0x20 RW Offset value and gain value of vector element n of sequencer m n 0 2 m 0 9 Corresponds to n 0 X value n 1 Y value n 2 Z value Reserved 0x0034 n x 0x20 to 0x003c n x 0x20 Reserved n 0 9 SEQ_INSTRUCTION_n 0x0160 n x 0x04 RW Sequencer n instructions ...

Page 802: ...e SCU Sensor Control Unit 684 OFFSET 0x0004 NAME Field Name Bit RW Description SCU_SW_REVISION_TIME Reserved 31 24 Reserved 23 0 RO Time that the SCU SW was built The HHMMSS can be obtained in hexadecimal E g 100615 This parameter must be written during startup of the internal sequencer and cannot be updated later 3 9 12 11 3 SCU_SW_REVISION_GIT_HASH Table SCU Sensor Control Unit 685 OFFSET 0x0008...

Page 803: ... 12 11 5 SEQ_PROPERTY_n Table SCU Sensor Control Unit 687 OFFSET 0x0020 n x 0x20 n 0 9 NAME Field Name Bit RW Description SEQ_PROPERTY_ n Reserved 31 29 Reserved INST_LEN 28 24 RW Sets the number of sequence commands of the sequencer 0 corresponds to 1 command 0 to 31 INST_OFST 22 16 RW Sets the start offset of the sequence command of the sequencer 0 corresponds to no offset 0 to 127 SEQ_OUT_SEL 1...

Page 804: ...7 Reserved 19 15 Reserved MATH_WRITE_BYTE _SWAPT 16 RW Format for writing to the MATH_PROC Set to 1 when swapping 8 bit 2 Byte data to 16 bits Reserved 15 8 Reserved FIFO_WRITE_LEN 7 4 RW Selects how many Bytes of data read out from the sensor to write to the FIFO 0 means 1 Byte 0 to 15 FIFO_WRITE_START _OFST 3 0 RW Selects from which Byte of data read out from the sensor to start writing to the F...

Page 805: ...on is repeated The actual number of repeats 1 is set When TERMINATE is 1 the sequencer is completed within the main loop being executed after the data transfer has been completed After confirming the data the sequencer executes instructions from the next instruction after TERMINATE during the next execution Caution When I2C command is executed only writing or the last command of I2C command string...

Page 806: ...DC2_ENABLE 26 RW When using the sequencer to read out values from the LPADC2 this is 1 LPADC1_ENABLE 1 25 RW When using the sequencer to read out values from the LPADC1 this is 1 LPADC0_ENABLE 24 RW When using the sequencer to read out values from the LPADC0 this is 1 HPADC1_FIFO_WRITE_ID 23 20 RW Selects the FIFO_ID 0 to 15 to which data read out from the HPADC1 is written HPADC0_FIFO_WRITE_ID 19...

Page 807: ...RIORITY 3 D0_W3_S Prohibited setting at ADC_PRIORITY 4 D1_W0_S 5 D1_W1_S Prohibited setting at ADC_PRIORITY 6 D1_W2_S Prohibited setting at ADC_PRIORITY 7 D1_W3_S Prohibited setting at ADC_PRIORITY 8 N0_W_S 9 N1_W_S 10 N2_W_S 11 N3_W_S 12 N4_W_S 13 N5_W_S 14 N6_W_S 15 N7_W_S 3 9 12 11 10 ADC_MATH_PROC_OFST_GAIN_n Table SCU Sensor Control Unit 694 OFFSET 0x0264 n x 0x04 n 0 6 NAME Field Name Bit RW...

Page 808: ... 23 20 Reserved WRITE_SAMPLE_NUM 19 8 RW When WRITE_CTRL is 2 if selected condition is satisfied the number of samples selected here are written to the FIFO 0 means one time 0 to 4095 Reserved 7 6 Reserved EVENT_ID 5 4 When WRITE_CTRL is 1 or 2 the condition ID selected here is referenced Select from 0 to 2 Reserved 3 2 Reserved WRITE_CTRL 1 0 0 Always writes 1 Does not write until the condition s...

Page 809: ...Reserved 15 9 Reserved PW_CTRL_EN1 8 RW Performs power down control of the later half 32 KBytes region of the FIFO SRAM Turns ON the SRAM when any of the sequencers within the SCU starts up and switches to the low power mode which holds values of SRAM when writing to the FIFO is completed Reserved 7 1 Reserved PW_CTRL_EN0 0 RW Performs power down control of the first half 8 KBytes region of the FI...

Page 810: ... The following describes the procedures of sequencer complete interrupt request 1 Sequencer completion request change the bit of the corresponding sequencer of START_MODE0 within SCU_REG from 1 to 0 2 Check that Sleep setting is released If not released set HPADC0_ACCESS_INHIBIT_REQ within SCU_REG to 1 SLEEP release and prohibition 3 Clear the SCU interrupt factor 4 Disable the iSoP3 IRQ interrupt...

Page 811: ... twice and after checking clear the sample data loss flag to 0 9 Set HPADC0_ACCESS_INHIBIT_REQ to 0 SLEEP enable 10 End of the procedure 3 9 12 11 15 SYNCHRO_iSoP2CPU Table SCU Sensor Control Unit 699 OFFSET 0x02c8 NAME Field Name Bit RW Description SYNCHRO_iSoP2CPU Reserved 31 30 Reserved SEQ_ID 0 RW After the sequencer ID suspend interrupt if the sequencer is executed the error is notified 1 mea...

Page 812: ...LPADC HPADC power supply On 5 PWD_SCU reset release 6 LPADC functional block reset release 7 HPADC functional block reset release 8 XOSC RCOSC clock set 9 PWD_SCU clock set 10 SPI clock supply start 11 I2C0 I2C1 clock supply start 12 LPADC clock supply start 13 HPADC clock supply start 14 LPADC HPADC operation enable 15 Sensor interrupt input terminal set 16 SPI terminal set 17 I2C0 terminal set 1...

Page 813: ...ble 2 HPADC0 data output disable 3 HPADC1 data output disable 4 Sequencer suspend 5 Sequencer reset 6 LPADC HPADC operation suspend 7 RCOSC XOSC clock supply stop 8 LPADC clock supply stop 9 HPADC clock supply stop 10 I2C clock supply stop 11 SPI clock supply stop 12 SCU clock supply stop 13 HPADC power supply stop 14 LPADC power supply stop 15 PWD_SCU power supply stop 3 9 13 3 Sequencer Initiali...

Page 814: ... 3 I2C0 sequencer operation initial settings Section 3 9 13 6 5 I2C1 sequencer operation initial settings Section 3 9 13 6 5 LPADC operation parameter settings Section 3 9 13 6 6 LPADC data output start Section 3 9 13 6 6 LPADC conversion settings Section 3 9 13 6 6 HPADC0 operation parameter settings Section 3 9 13 6 7 HPADC0 data output start Section 3 9 13 6 7 HPADC1 operation parameter setting...

Page 815: ...ere shows the setting for external clock mode system configuration using TCXO For the internal oscillation mode system configuration using crystal oscillator set ON_XO_OSC_EN_SET OFF_XO_OSC_EN_CLR ON_XO_OSCOUT_EN_SET and OFF_XO_OSCOUT_EN_CLR to 1 b1 and set ON_XO_EXT_EN_SET and OFF_XO_EXT_EN_CLR to 1 b0 24 OFF_XO_OSC _EN_CLR 1 b0 20 ON_XO_OSCO UT_EN_SET 1 b0 19 OFF_XO_OSC OUT_EN_CLR 1 b0 18 ON_XO_...

Page 816: ...k selection 0 High speed clock 1 Low speed clock 0x0018d ec0 0 LV_CLK_U32_ SEL1 Clock selection 0 High speed clock 1 Low speed clock 0x0018d f80 0 LV_ADC0_SE LSTAGE 1 b0 ADC0 stage selection 7 4 LV_ADC0_DE LAYADJUST 4 b1100 ADC0 internal clock delay amount adjustment signal 0x0018d fc0 0 LV_ADC1_SE LSTAGE 1 b0 ADC0 stage selection 7 4 LV_ADC1_DE LAYADJUST 4 b1100 ADC0 internal clock delay amount a...

Page 817: ...E is 1 PWD_SCU Power ON Wait RCOSC XOSC LPADC HPADC Power ON TOPREG 0x0048 11 0 CLR 12 h00D Sets the following bits to 1 RMW OR 3 I2C communication error interrupt during power supply control 2 Timeout error occurrence interrupt during power supply control 0x004C 11 0 MSK 12 hFF2 Sets the following bits to 0 RMW AND 3 I2C communication error interrupt during power supply control 2 Timeout error oc...

Page 818: ...XRST_SCU_HPADC 1 b1 LPADC reset release For clock control refer to the PMU 3 4 Chapter Table SCU Sensor Control Unit 702 Sub Reset Control Event Control Register Location Address bit Name Setting Value Descriptions LPADC Operation Enable SCU ADC IF 0x0018de00 0 LV_ADC_EN 1 b1 LPADC operation enable 0x0018de10 0 SW_RESET 1 b1 FIFO reset HPADC0 Operation Enable SCU ADC IF 0x0018de84 0 LV_ADC0_EN 1 b...

Page 819: ...CXD5602 User Manual 819 1010 Confirmati on IF 0x0018de90 0 SW_RESET 0 Confirms whether turns to 0 0x0018ded0 0 SW_RESET 0 Confirms whether turns to 0 ...

Page 820: ...00 CH0 3 b001 CH1 3 b010 CH2 3 b011 CH3 3 b100 CH0 CH1 3 b101 CH0 CH1 CH2 CH3 Table SCU Sensor Control Unit 704 Startup Settings Event Control Register Location Address bit Name Setting Value Descriptions Sequencer Operation Parameter Settings SCU SCU _REG Follow the API Sequencer Program Download SCU SCU _REG Follow the API Sequencer Operation Parameter Setting SCU SCU _REG Follow the API Interru...

Page 821: ...RMW AND 13 CK_SCU_SEQ On Off Clock Supply TOPREG 0x071C 4 SCU_REQ 1 b1 PWD_SCU sequencer clock enable CK_SCU_SEQ CRG Interrupt Wait Waits for the clock enable completion interrupt from the CRG Interrupt Confirmation TOPREG 0x04F4 21 0 STAT 22 h002000 0 Interrupt confirmation confirms that the following bit turns to 1 13 CK_SCU_SEQ On Off Interrupt Clear TOPREG 0x04EC 21 0 CLR 22 h002000 Sets the f...

Page 822: ...ing ratio selection 0 bypass 1 1 2 15 1 32768 LPADC Operation Parameter Settings SCU ADC IF 0x0018d e24 3 0 FIFO_WAT ERMARK 4 d8 LPADC FIFO Watermark 5 DMA_HS_ EN 1 b0 LPADC DMA signal usage enable disable 11 8 SAMP_RA TIO LPADC sampling ratio selection 0 bypass 1 1 2 15 1 32768 HPADC0 Operation Parameter Settings SCU ADC IF 0x0018d e94 4 0 FIFO_WAT ERMARK 5 d16 HPADC0 FIFO Watermark 5 DMA_HS_ EN ...

Page 823: ...t 705 Output Disable Settings Event Control Register Location Address bit Name Setting Value Descriptions LPADC Output Disable SCU ADCIF 0x0018de18 3 0 FIFO_EN 4 h0 Refer to Table SCU Sensor Control Unit 708 HPADC0 Output Disable SCU ADCIF 0x0018de98 0 DECIFIFO_EN 1 b0 Same as above HPADC1 Output Disable SCU ADCIF 0x0018ded8 0 DECIFIFO_EN 1 b0 Same as above Sequencer Suspend SCU SCU_R EG 0x0019502...

Page 824: ...r to the PMU Chapter 3 4 Sequencer Reset TOPREG 0x0704 7 XRST_SCU_ISOP 1 b1 FIFO Initialization Refer to Table SCU Sensor Control Unit 721 START_CTR L Related Register Settings SCU SCU 0x001950 28 START_CTRL_COMMON Refer to Section 3 9 12 3 5 0x001950 2c START_MODE0 0 e g Refer to Section 3 9 12 3 6 0x001950 30 START_MODE1 0 e g Refer to Section 3 9 12 3 7 0x001950 34 START_INTERVAL3_0 0x5432 e g ...

Page 825: ... e g Refer to Section 3 9 12 3 25 0x001950 88 DECIMATION_PARAM1 0x0F0F0F0 0 e g Refer to Section 3 9 12 3 26 0x001950 8c MATHFUNC_SEL 0 e g Refer to Section 3 9 12 3 27 0x001950 90 MATHFUNC_POS0 0 e g Refer to Section 3 9 12 3 28 0x001950 94 MATHFUNC_POS1 0 e g Refer to Section 3 9 12 3 29 0x001950 98 MATHFUNC_POS2 0 e g Refer to Section 3 9 12 3 30 0x001950 a0 MATHFUNC_PARAM_0_0 0 e g Refer to Se...

Page 826: ...3 44 0x001950 ec MATHFUNC_PARAM_C1_0_1_ MSB 0 e g Refer to Section 3 9 12 3 45 0x001950 f0 MATHFUNC_PARAM_C1_0_1_L SB 0 e g Refer to Section 3 9 12 3 46 0x001950 f4 MATHFUNC_PARAM_C2_0_1_ MSB 0 e g Refer to Section 3 9 12 3 47 0x001950 f8 MATHFUNC_PARAM_C2_0_1_L SB 0 e g Refer to Section 3 9 12 3 48 0x001950 fc MATHFUNC_PARAM_C3_0_1_ MSB 0 e g Refer to Section 3 9 12 3 49 0x001951 00 MATHFUNC_PARA...

Page 827: ... 12 3 63 0x001951 38 MATHFUNC_PARAM_1_1 0 e g Refer to Section 3 9 12 3 64 0x001951 3c MATHFUNC_PARAM_C0_1_1_ MSB 0 e g Refer to Section 3 9 12 3 65 0x001951 40 MATHFUNC_PARAM_C0_1_1_L SB 0 e g Refer to Section 3 9 12 3 66 0x001951 44 MATHFUNC_PARAM_C1_1_1_ MSB 0 e g Refer to Section 3 9 12 3 67 0x001951 48 MATHFUNC_PARAM_C1_1_1_L SB 0 e g Refer to Section 3 9 12 3 68 0x001951 4c MATHFUNC_PARAM_C2...

Page 828: ...3 82 0x001951 84 MATHFUNC_PARAM_C3_2_0_L SB 0 e g Refer to Section 3 9 12 3 83 0x001951 88 MATHFUNC_PARAM_C4_2_0_ MSB 0 e g Refer to Section 3 9 12 3 84 0x001951 8c MATHFUNC_PARAM_C4_2_0_L SB 0 e g Refer to Section 3 9 12 3 85 0x001951 90 MATHFUNC_PARAM_2_1 0 e g Refer to Section 3 9 12 3 86 0x001951 94 MATHFUNC_PARAM_C0_2_1_ MSB 0 e g Refer to Section 3 9 12 3 87 0x001951 98 MATHFUNC_PARAM_C0_2_1...

Page 829: ...VENT_PARAM1_THRESH 0 e g Refer to Section 3 9 12 3 101 0x001951 d0 EVENT_PARAM1_COUNT0 0 e g Refer to Section 3 9 12 3 102 0x001951 d4 EVENT_PARAM1_COUNT1 0 e g Refer to Section 3 9 12 3 103 0x001951 d8 EVENT_PARAM1_COUNT2 0 e g Refer to Section 3 9 12 3 104 0x001951 dc EVENT_PARAM2_THRESH 0 e g Refer to Section 3 9 12 3 105 0x001951 e0 EVENT_PARAM2_COUNT0 0 e g Refer to Section 3 9 12 3 106 0x001...

Page 830: ...n SCU SPI Refer to Section 3 9 13 6 4 Initial Settings for I2C0 Sequencer Operation SCU I2C0 Refer to Section 3 9 13 6 5 Initial Setting for I2C1 Sequencer Operation SCU I2C1 Refer to Section 3 9 13 6 5 Boot Completion Wait SCU SCU 0x001950 20 1 ENABLE_READY Read Only 1 b1 optional Confirms 1 b1 Sequencer Startup SCU SCU 0x001950 20 0 ENABLE_ALL_SEQ 1 b1 LPADC Operation Start SCU ADC IF Refer to S...

Page 831: ...ration Event Control Register Location Address bit Name Setting Values Descriptions Inhibit Request SCU SCU 0x00195024 1 I2C0_ACCESS_INHIBIT_REQ 1 b1 Request Acceptance Confirmation SCU SCU 0x00195024 9 I2C0_ACCESS_INHIBIT_ACK Read Only 1 b1 Confirm that it is 1 b1 I2C0 Register Setting SCU SPI as necessary Refer to Section 3 9 13 6 5 I2C0 Sequencer Operation Initial Setting SCU SPI Refer to Secti...

Page 832: ...5602 User Manual 832 1010 Setting necessary 3 9 13 6 5 I2C1 Sequencer Operation Initial Setting SCU SPI Refer to Section 3 9 13 6 5 Inhibit Request Release SCU SCU 0x00195024 2 I2C1_ACCESS_INHIBIT_REQ 1 b0 ...

Page 833: ...MA signal usage enable disable 11 8 SAMP_RATIO LPADC sampling ratio selection 0 bypass 1 1 2 15 1 32768 0x0018d e1c 3 0 FIFO_WATERMARK LPADC FIFO Watermark 5 DMA_HS_EN LPADC DMA signal usage enable disable 11 8 SAMP_RATIO LPADC sampling ratio selection 0 bypass 1 1 2 15 1 32768 0x0018d e20 3 0 FIFO_WATERMARK LPADC FIFO Watermark 5 DMA_HS_EN LPADC DMA signal usage enable disable 11 8 SAMP_RATIO LPA...

Page 834: ...ptions 0x0018de94 4 0 FIFO_WATERMARK HPADC0 FIFO Watermark 5 DMA_HS_EN HPADC0 DMA signal usage enable disable 10 8 DECI_RATIO HPADC0 decimation ratio selection 0 bypass 1 1 2 7 1 128 0x0018de98 0 DECIFIFO_EN 1 HPADC0 Decimation FIFO operation enable disable 3 9 13 6 8 HPADC1 Operation Settings For the control register specifications refer to the ADC Chapter 3 21 Table SCU Sensor Control Unit 712 H...

Page 835: ...CXD5602 User Manual 835 1010 enable disable ...

Page 836: ... the partition start address 15 0 FIFO_PARTITION_SIZE Selects the partition size 0x0018 0044 3 0 FIFO_SAMPLE_SIZE Selects the number of Bytes per sample 4 OVERWRITE_IF_FULL Selects the operation mode during FIFO full 16 FIFO_RESET 1 Resets the FIFO writing side D0_W3 _S 0x0018 0060 31 16 FIFO_START_OFST Selects the partition start address 15 0 FIFO_PARTITION_SIZE Selects the partition size 0x0018 ...

Page 837: ... 15 0 FIFO_PARTITION_SIZE Selects the partition size 0x0018 0124 3 0 FIFO_SAMPLE_SIZE Selects the number of Bytes per sample 4 OVERWRITE_IF_FULL Selects the operation mode during FIFO full 16 FIFO_RESET 1 Resets the FIFO writing side N2_W_ S 0x0018 0140 31 16 FIFO_START_OFST Selects the partition start address 15 0 FIFO_PARTITION_SIZE Selects the partition size 0x0018 0144 3 0 FIFO_SAMPLE_SIZE Sel...

Page 838: ...ample 4 OVERWRITE_IF_FULL Selects the operation mode during FIFO full 16 FIFO_RESET 1 Resets the FIFO writing side 0x0018 0218 30 16 TIME_STAMP_INTERV AL Sets the intervals of FIFO writing only for virtual sensor partition This value is added to the LATEST_TIME_STAMP each time writing to the FIFO_WRITE_REG is performed V1_W_ C 0x0018 0220 31 16 FIFO_START_OFST Selects the partition start address 1...

Page 839: ...FO full 16 FIFO_RESET 1 Resets the FIFO writing side 0x0018 02b8 30 16 TIME_STAMP_INTERV AL Sets the intervals of FIFO writing only for virtual sensor partition V6_W_ C 0x0018 02c0 31 16 FIFO_START_OFST Selects the partition start address 15 0 FIFO_PARTITION_SIZE Selects the partition size 0x0018 02c4 3 0 FIFO_SAMPLE_SIZE Selects the number of Bytes per sample 4 OVERWRITE_IF_FULL Selects the opera...

Page 840: ...1 Almost Full Interrupt Permission optional 9 D0_R1_C 10 D0_R2_C 11 D1_R1_C 12 D1_R2_C 13 N0_R1_C 14 N1_R1_C 15 N2_R1_C 16 N3_R1_C 17 N4_R1_C 18 N5_R1_C 19 N6_R1_C 20 N7_R1_C 21 D0_R3_CH 22 D1_R3_CH 0x00195420 22 9 OVER_RUN 1 Enables writing occurrence error interrupt during Full optional For bit assignment refer to ALMOST_FULL 0x00195440 22 9 UNDER_RUN 1 Enables readout occurrence error interrupt...

Page 841: ... FIFO_DMA_ENAB LE Sets output permission of DMA handshake signal 24 FIFO_ENABLE 1 Readout side FIFO operation permission 16 FIFO_RESET 1 Resets the readout side FIFO N2_R1_ C 0x001810c0 15 0 WATER_MARK Sets Watermark 0x001810c4 25 FIFO_DMA_ENAB LE Sets output permission of DMA handshake signal 24 FIFO_ENABLE 1 Readout side FIFO operation permission 16 FIFO_RESET 1 Resets the readout side FIFO N3_R...

Page 842: ...sets the readout side FIFO D1_R3_ CH 0x001811a0 15 0 WATER_MARK Sets Watermark 0x001811a4 25 FIFO_DMA_ENAB LE Sets output permission of DMA handshake signal 24 FIFO_ENABLE 1 Readout side FIFO operation permission 16 FIFO_RESET 1 Resets the readout side FIFO D0_R0_ H 0x001811c0 15 0 WATER_MARK Sets Watermark 0x001811c4 25 FIFO_DMA_ENAB LE Sets output permission of DMA handshake signal 24 FIFO_ENABL...

Page 843: ...24 FIFO_ENABLE 1 Readout side FIFO operation permission 16 FIFO_RESET 1 Resets the readout side FIFO N5_R0_ H 0x001812a0 15 0 WATER_MARK Sets Watermark 0x001812a4 25 FIFO_DMA_ENAB LE Sets output permission of DMA handshake signal 24 FIFO_ENABLE 1 Readout side FIFO operation permission 16 FIFO_RESET 1 Resets the readout side FIFO N6_R0_ H 0x001812c0 15 0 WATER_MARK Sets Watermark 0x001812c4 25 FIFO...

Page 844: ...WATER_MARK Sets Watermark 0x001813c4 24 FIFO_ENABLE 1 Readout side FIFO operation permission 16 FIFO_RESET 1 Resets the readout side FIFO V7_R_H 0x001813e0 15 0 WATER_MARK Sets Watermark 0x001813e4 24 FIFO_ENABLE 1 Readout side FIFO operation permission 16 FIFO_RESET 1 Resets the readout side FIFO V8_R_H 0x00181400 15 0 WATER_MARK Sets Watermark 0x00181404 24 FIFO_ENABLE 1 Readout side FIFO operat...

Page 845: ... 1st time is mandatory 2nd time on is optional 0x00180278 14 0 LATEST_BASE_TIME STAMP_LSB 0x00180268 3 0 FIFO_WRITE_PHASE Confirmation optional and readout of the writing phase FIFO data write V4_W_C 0x00180294 31 0 LATEST_BASE_TIME STAMP_MSB Writes the reference time stamp 1st time is mandatory 2nd time on is optional 0x00180298 14 0 LATEST_BASE_TIME STAMP_LSB 0x00180288 3 0 FIFO_WRITE_PHASE Conf...

Page 846: ...8 3 0 FIFO_WRITE_PHASE Confirmation optional and readout of the writing phase FIFO data write V9_W_C 0x00180334 31 0 LATEST_BASE_TIME STAMP_MSB Writes the reference time stamp 1st time is mandatory 2nd time on is optional 0x00180338 14 0 LATEST_BASE_TIME STAMP_LSB 0x00180328 3 0 FIFO_WRITE_PHASE Confirmation optional and readout of the writing phase FIFO data write Table SCU Sensor Control Unit 71...

Page 847: ...normality occurrence factor confirmation optional 1 FIFO_UNDER_RUN 0x00181044 0 FIFO_OVER_RUN_CLR Abnormality occurrence factor clear optional 1 FIFO_UNDER_RUN_CLR D1_ R2_ C FIFO data readout 0x00181070 31 0 OLDEST_TIMESTAMP_MSB Time stamp readout optional 0x00181074 14 0 OLDEST_TIMESTAMP_LSB 0x0018106c 11 8 FIFO_READ_PHASE Readout phase confirmation optional 0x00181064 8 FIFO_PHASE_RESET Readout ...

Page 848: ...CLR Abnormality occurrence factor clear optional 1 FIFO_UNDER_RUN_CLR N3_ R1_ C FIFO data readout 0x001810f0 31 0 OLDEST_TIMESTAMP_MSB Time stamp readout optional 0x001810f4 14 0 OLDEST_TIMESTAMP_LSB 0x001810ec 11 8 FIFO_READ_PHASE Readout phase confirmation optional 0x001810e4 8 FIFO_PHASE_RESET Readout phase reset optional 0x001810ec 0 FIFO_OVER_RUN Abnormality occurrence factor confirmation opt...

Page 849: ...00181170 31 0 OLDEST_TIMESTAMP_MSB Time stamp readout optional 0x00181174 14 0 OLDEST_TIMESTAMP_LSB 0x0018116c 11 8 FIFO_READ_PHASE Readout phase confirmation optional 0x00181164 8 FIFO_PHASE_RESET Readout phase reset optional 0x0018116c 0 FIFO_OVER_RUN Abnormality occurrence factor confirmation optional 1 FIFO_UNDER_RUN 0x00181164 0 FIFO_OVER_RUN_CLR Abnormality occurrence factor clear optional 1...

Page 850: ... 11 8 FIFO_READ_PHASE Readout phase confirmation optional 0x001811e4 8 FIFO_PHASE_RESET Readout phase reset optional 0x001811ec 0 FIFO_OVER_RUN Abnormality occurrence factor confirmation optional 1 FIFO_UNDER_RUN 0x001811e4 0 FIFO_OVER_RUN_CLR Abnormality occurrence factor clear optional 1 FIFO_UNDER_RUN_CLR N0_ R0_ H FIFO data readout 0x00181210 31 0 OLDEST_TIMESTAMP_MSB Time stamp readout option...

Page 851: ...ional 0x0018126c 0 FIFO_OVER_RUN Abnormality occurrence factor confirmation optional 1 FIFO_UNDER_RUN 0x00181264 0 FIFO_OVER_RUN_CLR Abnormality occurrence factor clear optional 1 FIFO_UNDER_RUN_CLR N4_ R0_ H FIFO data readout 0x00181290 31 0 OLDEST_TIMESTAMP_MSB Time stamp readout optional 0x00181294 14 0 OLDEST_TIMESTAMP_LSB 0x0018128c 11 8 FIFO_READ_PHASE Readout phase confirmation optional 0x0...

Page 852: ...ptional 1 FIFO_UNDER_RUN 0x001812e4 0 FIFO_OVER_RUN_CLR Abnormality occurrence factor clear optional 1 FIFO_UNDER_RUN_CLR V0_ R_H FIFO data readout 0x00181310 31 0 OLDEST_TIMESTAMP_MSB Time stamp readout optional 0x00181314 14 0 OLDEST_TIMESTAMP_LSB 0x0018130c 11 8 FIFO_READ_PHASE Readout phase confirmation optional 0x00181304 8 FIFO_PHASE_RESET Readout phase reset optional 0x0018130c 0 FIFO_OVER_...

Page 853: ...ctor clear optional 1 FIFO_UNDER_RUN_CLR V4_ R_H FIFO data readout 0x00181390 31 0 OLDEST_TIMESTAMP_MSB Time stamp readout optional 0x00181394 14 0 OLDEST_TIMESTAMP_LSB 0x0018138c 11 8 FIFO_READ_PHASE Readout phase confirmation optional 0x00181384 8 FIFO_PHASE_RESET Readout phase reset optional 0x0018138c 0 FIFO_OVER_RUN Abnormality occurrence factor confirmation optional 1 FIFO_UNDER_RUN 0x001813...

Page 854: ...ut 0x00181410 31 0 OLDEST_TIMESTAMP_MSB Time stamp readout optional 0x00181414 14 0 OLDEST_TIMESTAMP_LSB 0x0018140c 11 8 FIFO_READ_PHASE Readout phase confirmation optional 0x00181404 8 FIFO_PHASE_RESET Readout phase reset optional 0x0018140c 0 FIFO_OVER_RUN Abnormality occurrence factor confirmation optional 1 FIFO_UNDER_RUN 0x00181404 0 FIFO_OVER_RUN_CLR Abnormality occurrence factor clear optio...

Page 855: ...criptions TOPREG 0x0018 1 0 SCU_FIFO0 0 Table SCU Sensor Control Unit 720 Transition Process to FIFO 32 KByte Retention Control Register Location Address bit Name Setting Values Descriptions TOPREG 0x0018 3 2 SCU_FIFO1 1 Table SCU Sensor Control Unit 721 Transition Process to FIFO 8 KByte All ON Control Register Location Address bit Name Setting Values Descriptions TOPREG 0x0018 3 2 SCU_FIFO1 3 0x...

Page 856: ...SYNCHRO_iSoP2CPU parameter None When sample data loss occurs this can be known by the time stamp shift ADCIF The FIFO for the LPADC ch n within the ADCIF has overflowed LPADC_OVER_RUNn n 0 3 None ADCIF The FIFO for the HPADC ch n within the ADCIF has overflowed HPADCn_OVER_RUN n 1 2 None ADCIF An abnormal readout from the FIFO within the ADCIF has occurred ADCIF_READ_ERR None ADCIF The FIFO partit...

Page 857: ...tions in Section 3 9 12 11 ADC_PROPERTY _ENABLE Set ADC_PROPERTY _ENABLE to enable before enabling the _D2 _EN within the SCU_ADCIF_REG The SCU_RAM cannot be accessed during SLEEP 3 9 15 2 Decimation Partition Input Data The data input to the decimation partition all paths to the Write FIFOs must be Calculation Operable Type This restriction is the same during FORTH_THROUGH mode and when the decim...

Page 858: ... MATH_PROC to the completion of preparing the data for output The following shows the registers that cannot be dynamically changed Table SCU Sensor Control Unit 725 MATH_PROC Registers that cannot be Dynamically Changed Register Bit Field Description Effect of Changing Dynamically DEC_CLR DEC0_COMM ON_CLR Register Clear of DEC0 integrator The integrator cannot be reset because the initial state of...

Page 859: ... MATH_FUNCTION cannot be turned ON dynamically since the calculation results sometimes are not output MATHF_EN0 Operation permission of Math Function 0 WID1 The FIFO Partition ID assigned to Math Function 1 Same as above MATHF_EN1 Operation permission of Math Function 1 WID2 The FIFO Partition ID assigned to Math Function 2 Same as above MATHF_EN2 Operation permission of Math Function 2 The change...

Page 860: ...et Slave by writing it to TAR Write to IC_SS_HCNT to set HIGH period of SCL Write to IC_SS_LCNT to set LOW period of SCL Write to IC_INTR_MASK to enable all interrupts Write to IC_RX_TL to set Rx FIFO threshold level Write to IC_TX_TL to set Tx FIFO threshold level Write 1 to IC_ENABLE to enable DW_apb_i2c Command is Write Yes No RX_FULL interrupt asserted Yes Read IC_DATA_CMD 7 0 to retrieve rece...

Page 861: ...E0 PRE_DIVIDER 0 START_PHASE0 5 START_ INTERVAL0 3 SEQ_EXE0 Figure SCU Sensor Control Unit 90 Basic Startup Timing Figure SCU Sensor Control Unit 91 shows an example of when the startup delays The delay of sampling start Td in the below Figure cannot be known from the outside CPU because it depends on the relation between the startup timing the START_PHASEn and the ICOUNT2 For example if startup i...

Page 862: ...C readout the time stamp of the ADC will be incorrect This is because 0xA must be set in the START_INTERVALn field of the START_INTERVAL register within the SCU_REG when using the One shot Sequencer 3 9 15 10 Converting the LATEST Time Stamp to the OLDEST Time Stamp The LATEST_TIMESTAMP can be converted to the OLDEST_TIMESTAMP Due to the restrictions of the OLDEST_TIMESTAMP refer to Section 3 9 15...

Page 863: ...he CH_SEL_MODE value the intermediate parameter used here In the case of 4 two channel mode SEL_DIV 1 In the case of 5 four channel mode SEL_DIV 2 Other SEL_DIV 0 32 kHz frequency division setting register of SCU_ADCIF LPADC_D1 SAMP_RATIO 0x0214 PWD_SCU region for LPADC0 LPADC_D4 SAMP_RATIO 0x021C PWD_SCU region for LPADC1 LPADC_D5 SAMP_RATIO 0x0220 PWD_SCU region for LPADC2 LPADC_D6 SAMP_RATIO 0x...

Page 864: ...V 2 XOSC_DIV 4 When LV_CLK_XOSC_DIV 3 XOSC_DIV 6 Sets whether to use XOSC RCOSC of SCU_ADCIF or 32 kHz input for each HPADC HPADC0_A0 LV_CLK_U32_SEL0 0x0280 PWD_SCU region HPADC1_A0 LV_CLK_U32_SEL1 0x02C0 PWD_SCU region Decimation ratio of CIC filter for each HPADC HPADC0_D1 DECI_RATIO 0x0294 PWD_SCU region HPADC1_D1 DECI_RATIO 0x02D4 PWD_SCU region Pick up the decimation ratio of CIC filter withi...

Page 865: ...o 0 when not using decimation Calculation Equation Sampling frequency FREQ_SEQ 32768 PRE_DIVIDER 1 2 START_INTERVAL0 or 1 or 2 or 3 or 4 or 5 or 6 or 7 or 8 or 9 2 one of N1 to N6 INTERVAL 32768 FREQ_LPADC 3 9 15 12 Time Stamp Fluctuation The fluctuation of time stamps depends on the execution time of each task When tasks that were not executed in the main loop are executed or when tasks that were...

Page 866: ...ng HPADC data HPADC SPI I2C0 I2C1 LPADC SPI I2C0 I2C1 LPADC the variation of time stamp for SPI Figure SCU Sensor Control Unit 92 Time Stamp Fluctuation by the Presence Absence of HPADC Execution 3 9 15 13 Time Stamp Readout Restrictions The time stamp within the SCU is comprised of MSB 32 bits the seconds digits and LSB 15 bits the seconds and smaller than seconds digits However atomic access is ...

Page 867: ...currently in use The sample decimation circuit of the LPADC is controlled by the counter the output value is cnt_out which increments each time data is output from the LPADC The counter operates at a clock of 32 kHz and countup is performed at the timing that data is output from the LPADC the LPADC_DATAEN in Figure SCU Sensor Control Unit 93 When cnt_out 2 SAMP_RATIO 1 the value of the cnt_out is ...

Page 868: ...eset of the internal counter is not performed and the sampling frequency is changed from low to high a large delay may occur The delay until the first datum can be extracted is as follows When the first time each channel of LPADC is started up 1 RPOST RPOST RPRE seconds E g When 256 Hz approximately 3 9 ms After the LPADC stops startup with sampling frequency changed not resetting the LPADC In the...

Page 869: ...PADC Section 3 9 15 14 3 9 15 16 Decimation Partition Write FIFO and Read FIFO Connection Combinations In principle the Write FIFOs and Read FIFOs of the decimation partition must be connected in a one to one relation as shown in the example in Figure SCU Sensor Control Unit 94 One to N connections as shown in Figure SCU Sensor Control Unit 95 are functionally capable of realizing equivalent proce...

Page 870: ...itializing the writing side FIFO Before performing reset of the readout side the initial setting of the Write FIFO must be completed because the hardware uses the reset of the readout side FIFO as the trigger to copy the pointer of the writing side FIFO to the readout side Initialization of the writing side FIFO means the below sequences Table SCU Sensor Control Unit 728 Write FIFO Initialization ...

Page 871: ...ual 871 1010 Simultaneously DMA handshake signal output permission setting _R _ _CTRL1 FIFO_DMA_ENABLE Readout side FIFO operation permission _R _ _CTRL1 FIFO_ENABLE For FIFO restrictions also refer to Section 3 9 8 10 ...

Page 872: ...r and SCU_RAM Reading and Writing When the internal sequencer is in SLEEP you cannot read or write from to the control registers or SCU_RAM Recover the internal sequencer from SLEEP before reading or writing from to the control registers or SCU_RAM ...

Page 873: ... the SPI bus by directly controlling the registers of the SPI from the SYSCPU Since control from the sequencer and control from the SYSCPU are exclusive they cannot be performed simultaneously This is used for data transmit receive Tx Rx mode SPI4 Power domain PWD_APP_SUB Supports only the master mode There is only one line of Chip Select This is used for data transmit receive Tx Rx mode or data t...

Page 874: ..._ahb_gear ck_com_gear MHz 48 750 39 000 26 000 8 192 0 032768 SPI0 SCK Tx Rx mode Mbps 12 188 9 750 6 500 4 096 0 016384 SCU ck_scu_pre MHz 13 000 8 192 0 032768 SPI3 SCK Tx Rx mode Mbps 6 500 4 096 0 016384 APP CK_APP MHz 97 500 156 000 26 000 8 192 0 032768 SPI4 SCK Tx Rx mode Mbps 9 750 9 750 13 000 4 096 0 016384 SPI4 SCK Tx mode Mbps 48 750 39 000 13 000 4 096 0 016384 SPI5 SCK Tx Rx mode Mbp...

Page 875: ...chronous Serial Port PL022 register 0x041AB028 0x041AB08C Reserved RO Reserved 0x0 0x041AB090 CS_MODE RW Chip Select 0x0 0x041AB094 SSP_CS RW Chip Select setting 0x1 0x041AB098 Reserved RW Reserved 0x0 0x041AB09C 0x041ABFDC Reserved RO Reserved 0x0 0x041ABFE0 0x041ABFFC PrimeCell Synchronous Serial Port PL022 register ...

Page 876: ...active 3 10 2 3 Clock and Reset Figure SPI 96 shows the clock and reset system diagram of the SPI0 To access the SPI0 register supply the clock to the AHB APB Bus Bridge SWRESET_BUS XRST_SPIM CK GATE SYSIOP_SUB_CKEN SPIM 1 M CKDIV_COM CK_COM 0 3 2 1 RCOSC XOSC RTC_CLK_IN 32 768kHz AHB APB BusBridge CK GATE 1 M SYSIOP_SUB_CKEN AHB_BRG_COMIF ck_cpu_bus CKDIV_CPU_DSP_BUS CK_M0 ck_rf_pll_1 PWD_RESET0 ...

Page 877: ...to the SPI0 1 Clock supply start to the AHB APB Bus Bridge SYSIOP_SUB_CKEN COM_BRG 1 b1 SYSIOP_SUB_CKEN AHB_BRG_COMIF 1 b1 2 Reset release SWRESET_BUS XRST_SPIM 1 b1 3 Clock supply start SYSIOP_SUB_CKEN SPIM 1 b1 3 10 2 4 2 Clock Supply Stop Perform the following control to stop supplying the SSPCLK clock and PCLK clock to the SPI0 1 Clock supply stop SYSIOP_SUB_CKEN SPIM 1 b0 ...

Page 878: ...ommunication slave selection 0x0 0x0418D09C 0x0418D3FC Reserved RO Reserved 0x0 3 10 3 2 Register Descriptions Table SPI 751 shows descriptions of the registers added for control of Chip Select Table SPI 735 SPI3 Register Descriptions Address Register Name Bit Field Name Type Bit Initial Value Description 0x0418D090 CS_MODE Reserved RO 15 1 0 Reserved cs_mode RW 0 1 b0 Chip Select CS 0 Uses CS of ...

Page 879: ...SCU SEL_SCU_XTAL 0 3 2 1 0 1 RTC_CLK_IN 32 768kHz 1 250 ck_scu_pre CKSEL_SCU SEL_SCU_32K Reserved CKSEL_SCU SEL_SCU SPI3 PCLK SSPCLK nSSPRST PRESETn Figure SPI 97 SPI3 Clock and Reset System 3 10 3 4 Clock Supply Start and Stop 3 10 3 4 1 Clock Supply Start Perform the following control to start supplying the SSPCLK clock and PCLK clock to the SPI3 1 Reset release SWRESET_SCU XRST_SCU_SPI 1 b1 2 C...

Page 880: ... reset system diagram of the SPI4 0 3 2 1 RCOSC SYSPLL XOSC RTC_CLK_IN 32 768kHz 0 3 2 1 0 1 1 2 1 3 1 4 1 5 APP_CKSEL APP_PLL_DIV5 CK GATE APP_CKEN APP APP_CKSEL STAT_APP_CLK_SEL4 APP_CKSEL STAT_SP_CLK_SEL4 GEAR_IMG_SPI gear_n_spi GEAR_IMG_WSPI gear_m_img_wspi GEAR_IMG_WSPI gear_n_img_wspi SPI4 SPI5 PCLK SSPCLK PCLK SSPCLK CK_APP UART2 GEAR_IMG_UART gear_m_uart GEAR_IMG_UART gear_n_uart CK GATE N...

Page 881: ...tting GEAR_AHB gear_m_ahb arbitrary denominator setting of the division ratio GEAR_AHB gear_n_ahb arbitrary numerator setting of the division ratio CK_GATE_AHB ck_gate_img 1 b1 4 SPI4 control clock supply and division ratio setting GEAR_IMG_SPI gear_m_spi arbitrary denominator setting of the division ratio GEAR_IMG_SPI gear_n_spi 1 b1 3 10 4 3 2 Clock Supply Stop Perform the following control to s...

Page 882: ...ar_n_spi GEAR_IMG_WSPI gear_m_img_wspi GEAR_IMG_WSPI gear_n_img_wspi SPI4 SPI5 PCLK SSPCLK PCLK SSPCLK CK_APP UART2 GEAR_IMG_UART gear_m_uart GEAR_IMG_UART gear_n_uart CK GATE N M GEAR_AHB gear_m_ahb GEAR_AHB gear_n_ahb CK_GATE_AHB ck_gate_img RESET xrs_img PWD_RESET0 PWD_APP PCLK PRESETn UARTCLK IMG_RST_X nSSPRST PRESETn nSSPRST PRESETn nUARTRST 1 M CK GATE 1 M CK GATE 1 M CK GATE GEAR_IMG_SPI ge...

Page 883: ... GEAR_AHB gear_m_ahb arbitrary denominator setting of the division ratio GEAR_AHB gear_n_ahb arbitrary numerator setting of the division ratio CK_GATE_AHB ck_gate_img 1 b1 4 SPI5 control clock supply and division ratio setting GEAR_IMG_WSPI gear_m_wspi arbitrary denominator setting of the division ratio GEAR_IMG_WSPI gear_n_wspi 1 b1 3 10 5 3 2 Clock Supply Stop Perform the following control to st...

Page 884: ...r clock and the voltage mode High Performance mode Low Power mode The following table shows each combination and the maximum transfer rates Table Table UART 738 XOSC 26 MHz High Performance Mode Clock source XOSC RCOSC RTC frequency MHz 195 000 156 000 26 000 8 192 0 032768 SYSIOP ck_ahb_gear ck_com_gear MHz 48 750 39 000 26 000 8 192 0 032768 UART1 baudrate bps 1843200 1843200 921600 460800 1200 ...

Page 885: ...ck to the AHB APB Bus Bridge CK GATE SYSIOP_SUB_CKEN UART1 SWRESET_BUS XRST_UART1 CK GATE SYSIOP_SUB_CKEN COM_UART_PCLK CK_COM_BRG CK GATE SYSIOP_SUB_CKEN COM_BRG 1 M CKDIV_COM CK_COM 0 3 2 1 RCOSC XOSC RTC_CLK_IN 32 768kHz AHB APB BusBridge CK GATE 1 M SYSIOP_SUB_CKEN AHB_BRG_COMIF ck_cpu_bus ck_rf_pll_1 PWD_RESET0 PWD_SYSIOP_SUB ck_ahb_gear ck_com_gear SYSPLL 0 3 2 1 0 1 1 2 1 3 1 4 1 5 CKSEL_RO...

Page 886: ...k supply start SYSIOP_SUB_CKEN COM_UART_PCLK 1 b1 SYSIOP_SUB_CKEN UART1 1 b1 3 11 2 3 2 Clock Supply Stop Perform the following control to stop supplying the UARTCLK clock and PCLK clock to the UART1 1 Clock supply stop SYSIOP_SUB_CKEN COM_UART_PCLK 1 b0 SYSIOP_SUB_CKEN UART1 1 b0 3 11 3 UART2 3 11 3 1 Register List Table UART 765 shows a register list of the UART2 Table UART 741 UART2 Register Li...

Page 887: ...PP_CKSEL APP_PLL_DIV5 CK GATE APP_CKEN APP APP_CKSEL STAT_APP_CLK_SEL4 APP_CKSEL STAT_SP_CLK_SEL4 Figure UART 101 UART2 Clock and Reset System 3 11 3 3 Clock Supply Start and Stop 3 11 3 3 1 Clock Supply Start Perform the following control to start supplying the UARTCLK clock and PCLK clock to the UART2 1 Reset release PWD_RESET0 PWD_APP 1 b1 RESET xrs_img 1 b1 2 Supply the CK_APP For details refe...

Page 888: ... 3 3 2 Clock Supply Stop Perform the following control to stop supplying the UARTCLK clock and PCLK clock to the UART2 1 UART2 control clock stop GEAR_IMG_UART gear_n_uart 1 b0 2 UART2 register s clock stop CK_GATE_AHB ck_gate_img 1 b0 ...

Page 889: ...2 5 m Signal strength is 130 dBm Test circuit as shown in the figure below Time To First Fix TTFF Item GPS GPS GLONASS Unit Remark Cold Start 35 35 s Signal strength is 130 dBm Test circuit as shown in the figure below Hot Start 2 2 s Sensitivity Item GPS GPS GLONASS Unit Remark Cold Start 147 147 dBm Test circuit as shown in the figure below Hot Start 160 160 dBm Tracking 161 161 dBm Test Circuit...

Page 890: ...D5602 User Manual 890 1010 Noise Filter An embedded noise filter for GNSS signals It is automatically enabled at the optimum settings for the input noise RF Performance Item Min Typ Max Unit Total NF 3 db ...

Page 891: ...plication Processor The application processor integrates six Cortex M4 processors with FPU ADSP to meet the requirements of wearable and IoT devices which demand operation in low power and performance optimized consumer applications with the ability to scale in speed up to 156 0 MHz the Arm Cortex M4 Processor The key features include Arm Cortex M4 processor with FPU ISA Support Thumb Thumb 2 tech...

Page 892: ...mats Programmable polarity of video sync signal Capture frame control supported Input image size JPEG Only up to 5 M pixels Y C Only up to 480 x 360 JPEG Y C 2 M WQVGA JPEG High Quality mode 5 M WQVGA JPEG Normal Quality mode Parallel Input rate Up to 54 MHz SPI Interface for external display PrimeCell Synchronous Serial Port PL022 Display resolution High Performance mode Up to 320 240 15 fps 24 b...

Page 893: ...ctivity and Storage Domain The key features are USB 2 0 Device Complies with USB 2 0 Specification High speed up to 480 Mbps Not supported at Low Power mode On chip USB PHY transceiver Supports MSC MTP CDC PTP ACM and HID class Multi function Interface 0 1 2 SD Host Controller Interface SD Memory Card Protocol version 3 0 compatible 8 KByte 32 bit x 2048 word x2 FIFOs for Tx Rx Communication speed...

Page 894: ...requency Low power mode 128fs 64fs of bit clock frequency Slave clock High Performance mode 256fs 128fs 64fs of bit clock frequency Low power mode 128fs 64fs of bit clock frequency Sampling rate High Performance mode Master mode 192 kHz 96 kHz 48 kHz Slave mode 192 kHz 96 kHz 48 kHz 44 1 kHz 16 kHz 8 kHz Low Power mode Master mode 96 kHz 48 kHz Slave mode 96 kHz 48 kHz 44 1 kHz 16 kHz 8 kHz Two ch...

Page 895: ... main functional blocks of the Application Domain are connected Each has a different maximum operating frequency depending on the supported XOSC frequency and the SYSPLL oscillating frequency In addition element circuits such as AudioCodec USB eMMC that are connected to the APP SUB Bus have the same maximum frequencies as the APP MAIN Bus For the maximum operating frequencies of external communica...

Page 896: ... gear_m_uart 1 M CK GATE GEAR_IMG_SPI gear_n_spi GEAR_IMG_SPI gear_m_spi 1 M CK GATE GEAR_IMG_WSPI gear_n_wspi GEAR_IMG_WSPI gear_m_wspi CK_GATE_AHB ck_gate_img CK_GATE_AHB ck_gate_kaki CK_GATE_AHB ck_gate_sake CK_GATE_AHB ck_gate_dmac CK_GATE_AHB ck_gate_aud CK_GATE_AHB ck_gate_dsp0 5 CK_GATE_AHB ck_gate_mmc CK_GATE_AHB ck_gate_sdio GEAR_PER_SDIO gear_m_sdio CK_GATE_AHB ck_gate_usb GEAR_PER_USB g...

Page 897: ... Graphics IMG_RST_X CIS I F IDMAC HRESETn ADMAC HRESETn Crypto eMMC MMC_I_RST_N USB USBD_SYS_RST_N_I SDIO HRESETN XRST AUDIO XRST ADSP PWD_RESET0 PWD_APP RESET xrs_dsp0 5 RESET xrs_aud RESET xrs_img RESET xrs_usb RESET xrs_sdio RESET xrs_mmc RESET xrs_mmc_crg RESET xrs_dsp_gen XRSTS XRSTK XRST Figure APP 103 Application Domain Reset System ...

Page 898: ...itial Value Description 0x0410341C APP_DIV Reserved RO 31 3 0 Reserved AU_MCLK RW 2 0 0 AUDIO XOSC division ratio setting 0 clock not divided 1 clock divided by 2 2 clock divided by 3 3 clock divided by 4 4 clock divided by 5 5 clock divided by 6 6 clock divided by 7 7 clock divided by 8 Table APP 745 Clock Switching Registers Address Register Name Bit Field Name Type Bit Initial Value Description...

Page 899: ...L STAT_SP_CLK_SEL4 2 b10 XOSC 2 b11 RTC Clock APP_PLL_DI V5 RW 7 0 Clock divided by 4 or 5 for CK_APP SYSPLL 0 clock divided by 4 1 clock divided by 5 Reserved RW 6 0 0 Reserved Table APP 746 Clock Enable Registers Address Register Name Bit Field Name Type Bit Initial Value Description 0x04103414 APP_CKEN Reserved RO 31 4 0 Reserved AHB RW 3 0 Clock Enable of CK_APP_AHB 0 Clock stopped 1 Clock sup...

Page 900: ...hb gear_m_ahb must not be written If that is done gear_n_ahb will be overwritten to 7 h7f and gear_m_ahb to 7 h7f Operationally it means 1 1 0x0E011004 GEAR_IMG_UART Reserved RO 31 17 0 Reserved gear_n_uart RW 16 0 UART2 Clock Enable 0 Clock stopped 1 Clock supplied Reserved RO 15 7 0 Reserved gear_m_uart RW 6 0 7 h4 Division ratio setting of UART2 clock denominator 0 must not be written 0x0E01100...

Page 901: ...ion ratio setting of USB clock denominator 0 must not be written 0x0E011014 GEAR_M_IMG_VENB gear_m_img_ venb RW 31 0 0 Division ratio setting of VideoTG denominator Set values are not reflected until they are written in GEAR_N_IMG_VENB 0 or values which are applicable to the formula GEAR_N_IMG_VENB GEAR_M_IMG_VENB must not be written 0x0E011018 GEAR_N_IMG_VENB gear_n_img_v enb RW 31 0 0 Division r...

Page 902: ...MC DRV Clock Enabler 0 Clock stopped 1 Clock supplied cken_emmc_c lkin RW 0 0 eMMC Clock Enabler 0 Clock stopped 1 Clock supplied 0x0E011030 RESET Reserved RO 31 23 0 Reserved xrs_dsp_gen RW 22 0 DSP GENERAL Reset Register 0 Reset assert 1 Reset release xrs_dsp5 RW 21 0 Reset Register for ADSP5 0 Reset assert 1 Reset release xrs_dsp4 RW 20 0 Reset Register for ADSP4 0 Reset assert 1 Reset release ...

Page 903: ...t release Reserved RO 7 5 0 Reserved xrs_img RW 4 0 Image Reset Register 0 Reset assert 1 Reset release Reserved RO 3 1 0 Reserved xrs_aud RW 0 0 PWD_AUD Reset Register 0 Reset assert 1 Reset release 0x0E011040 CK_GATE_AHB Reserved RO 31 29 0 Reserved ck_gate_dmac RW 28 0 ADMAC ClockGate Register 0 Clock stopped 1 Clock supplied Reserved RO 27 22 0 Reserved ck_gate_dsp5 RW 21 0 ADSP5 ClockGate Reg...

Page 904: ...te_usb RW 8 0 USB AHB Bus ClockGate Register 0 Clock stopped 1 Clock supplied Reserved RO 7 5 0 Reserved ck_gate_img RW 4 0 Image AHB Bus ClockGate Register 0 Clock stopped 1 Clock supplied Reserved RO 3 1 0 Reserved ck_gate_aud RW 0 0 Audio AHB Bus ClockGate Register 0 Clock stopped 1 Clock supplied Table APP 748 APP SRAM Tile Clock Gating Registers Address Register Name Bit Field Name Type Bit I...

Page 905: ...ck stopped 1 Clock supplied tile5_clk_gati ng_enb RW 5 0 APP SRAM Tile 5 ClockGate 0 Clock stopped 1 Clock supplied tile4_clk_gati ng_enb RW 4 0 APP SRAM Tile 4 ClockGate 0 Clock stopped 1 Clock supplied tile3_clk_gati ng_enb RW 3 0 APP SRAM Tile 3 ClockGate 0 Clock stopped 1 Clock supplied tile2_clk_gati ng_enb RW 2 0 APP SRAM Tile 2 ClockGate 0 Clock stopped 1 Clock supplied tile1_clk_gati ng_en...

Page 906: ...set of ADSP 3 13 4 Description of APP_DSP Function 3 13 4 1 Overview and Features The APP_DSP is a sub block in the Application Domain It consists of the following 1 six Cortex M4 processors with FPU 2 1 5 Mbyte of SRAM 3 Audio and Imaging 2D Graphics CIF I F 4 Storage eMMC USB 5 buses to connect 1 to 5 functional blocks above The APP_DSP is mainly used for executing Main program and controlling o...

Page 907: ...dio SYSIOP Bus protection MID po wer protection MID po wer protection MID po wer protection MID po wer Imaging 2D protection MID po wer protection MID po wer protection MID po wer Storage Connectivity ADMAC protection MID po wer Crypto AES protection MID po wer protection MID po wer protection MID AHB to APB Clock Reset Generator General Purpose Registers General Purpose Registers Address Converte...

Page 908: ...debug block which offers SWD Trace and Cross Trigger functions 8 I D Multiplexor This function multiplexes ICode bus and DCode bus of the Cortex M4 processor with FPU in order of fixed priority DCode has a higher priority than ICode BUS 9 Address Map The Address Map enables to access memories and control a variety of programable functions via buses 10 Address Converter This function converts addre...

Page 909: ...gister List Address Register Name Type Description Initial Value 0x0E002040 PID RO Processor ID 0x0E002044 DSP_SLEEPING RO SLEEPING Signal Monitor 0 0x0E002048 WD_TIM_RES RO Watchdog Timer Status 0 0x0E010000 BUS_ERROR0 WO BUS ERROR Clear Register 0 0x0E010004 BUS_ERROR1 RO BUS ERROR Cause Register Error Type 0 0x0E010008 BUS_ERROR2 RO BUS ERROR Cause Register Master ID 0 0x0E012004 0x0E012020 ACN...

Page 910: ..._DISABLE RW Exclusive Access Control 1 0xE0043000 Timer RW Refer to Section 3 13 4 7 0xE0044000 Watchdog Timer RW Refer to Section 3 13 4 8 0xE0045000 Interrupt controller RW Refer to Section 3 13 4 6 For details refer to Section of the Interrupt 3 3 ...

Page 911: ...pported Nested Vectored Interrupt Controller NVIC The NVIC supports 128 interrupts The priority of each interrupt can be set in 256 steps Wakeup Interrupt Controller WIC Wakeup Interrupt Controller WIC is equipped WIC Support Signal The WIC interface uses NMI EDBGRQ RXEV and IRQ 127 0 to detect Wakeup Interrupts Trace Support Level The ITM TPIU DWT trigger and counter are supported The ETM and HTM...

Page 912: ...scription 0x0E002040 PID PID RO 3 0 1 Processor ID 1 Each processor can read the value which are indicated in Table APP 786 Table APP 754 Processor List Processor Name Processor ID ADSP0 2 ADSP1 3 ADSP2 4 ADSP3 5 ADSP4 6 ADSP5 7 3 13 4 6 Interrupt Controller The 128 bit interrupt signals are connected to each processor By using the interrupt controller confirmation of the interrupt state interrupt...

Page 913: ...eference Manual are equipped One timer for every processor six timers in total are equipped Since the registers of the Watchdog Timer for each processor are in the Private Peripheral Bus area they can be accessed in Privileged Mode only For detailed control method refer to AMBA Design Kit Technical Reference Manual The base address of the control register is 0xE0044000 Each control register can be...

Page 914: ...NMI Interrupt input Register 128 Cortex M4 PID5 IRQ NMI Interrupt input Register 128 Cortex M4 PID6 IRQ NMI Interrupt input Register 128 Cortex M4 PID7 IRQ NMI Interrupt input Register WDT WDTRES WDTINT WDT WDTRES WDTINT WDT WDTRES WDTINT WDT WDTRES WDTINT WDT WDTRES WDTINT WD_TIM_RES 5 0 to System and I O Processor Figure APP 105 WDTRES Connection All the WDTRES signal status of the ADSP can be c...

Page 915: ... Timer of ADSP1 wd_tim_res_0 RO 0 0 Reset status of Watchdog Timer of ADSP0 3 13 4 9 SLEEPING Signal Monitor You can confirm whether each ADSP is in stopped state Sleep now or Sleep on exit mode or not by reading registers shown below Table APP 756 SLEEPING Signal Register List Address Register Name Bit Field Name Type Bit Initial Value Description 0x0E002044 DSP_SLEEPING Reserved RO 31 6 0 Reserv...

Page 916: ...h FPU FPB unit contains the following components Two literal comparators Two literal comparators for matching against literal loads from Code space and remapping to a corresponding area in System space Six instruction comparators Six instruction comparators for matching against instruction fetches from Code space and remapping to a corresponding area in System space Alternatively you can configure...

Page 917: ...region 0x00000000 0x1FFFFFFC DCode bus is used for data and the debug access of the code memory region 0x00000000 0x1FFFFFFF and System bus is used for instruction fetch data and the debug access of the address regions 0x20000000 0xDFFFFFFF and 0xE0100000 0xFFFFFFFF Please note that 0x22000000 0x23FFFFFF region and 0x42000000 0x43FFFFFF region of the Application Processor View cannot be accessed T...

Page 918: ..._PERI 0x0E103000 Reserved 0x0E105000 USB 0x0E200000 eMMC 0x0E201000 SDIO 0x0E202000 Reserved 0x0E203000 Audio 20KB 0x0E300000 Reserved 0x0E305000 0x0FFFFFFF 0x04000000 0x08000000 0x0C000000 Reserved 0x0E002000 SMP_BUSERR_REG 0x0E010000 SMP_CRG 0x0E011000 Reserved 48KB 0x0E012000 SMP_ADR_CONV 0x0E021000 0x0E013000 SMP_GEN_REG 0x0E014000 SMP_UNPROT_GEN_REG 0x0E003000 area 0 64KB area 1 64KB area 15 ...

Page 919: ...FFFFF input address output address 1MB virtual region 32MB 32MB 32MB 32MB 32MB 32MB Figure APP 107 Input Output Addresses of Address Converter Address converter can be set on each ADSP furthermore on 16 areas of each 64 Kbyte individually As Figure APP 108 indicates address converter realizes the above conversion function that identifies areas by using input address bit 19 16 and replaces output a...

Page 920: ...rsion enabled when the address is 1MB from the beginning Address 15 0 5 4 6 00 Reserved 01 SYS Window 10 GNS Window 11 APP Window 7 9 8 10 Start Window 32MB Area Figure APP 108 Address Conversion Operation Scheme Timing control function of reflecting the address converter setting is not equipped For this reason set value change must be performed during the period that there are no bus transactions...

Page 921: ... ACNV_P N _DST_2 AREA_5 RW 26 16 0x005 Destination address after conversion of ADSP N area 5 320 384 KByte address area AREA_4 RW 10 0 0x004 Destination address after conversion of ADSP N area 4 256 320 KByte address area 0x02012010 N 0x020 ACNV_P N _DST_3 AREA_7 RW 26 16 0x007 Destination address after conversion of ADSP N area 7 448 512 KByte address area AREA_6 RW 10 0 0x006 Destination address...

Page 922: ...fter conversion of ADSP N area F 960 1024 KByte address area AREA_E RW 10 0 0x00E Destination address after conversion of ADSP N area E 896 960 KByte address area Note about N E g ADSP0 means that N 0 ADSP1 means that N 1 in the same way ADSP5 means that N 5 Examples of Address Conversion Below are setting examples showing conversion from 0x00000000 0x0001FFFF region into 0x0D000000 0x0D01FFFF reg...

Page 923: ...1 1 0x0D00 0x0D01 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ACNV_P0_DST_0 AREA_0 0x700 ACNV_P0_DST_0 AREA_1 0x701 0x0000 0x0001 0 0 0 0 0 0 0 1 Figure APP 109 Example of Address Conversion Conversion of Bit Assignment for ADSP0 APP Window 0x00000000 0x00000000 ADSP0 input address ADSP0 output address 64KB 0x00010000 64KB 0x0D000000 64KB 64KB 0x0C000000 0x0D010000 0x0D020000 APP Window 0x00000000 0x00000...

Page 924: ...ve success response Switch BUS_SNOOP_DISABLE at the timing when LDREX STREX is ensured not to be issued In the case that it was switched while LDREX or STREX are in use the snooping of the Bus will be finished When BUS_SNOOP_DISABLE bus_snoop_disable 1 b1 Bus Snooper is reset Held status is cleared Only internal flag is cleared Table APP 759 Exclusive Access Register Address Register Name Bit Fiel...

Page 925: ...ress to snoop issued from the master obtaining exclusive access right refer to Figure APP 112 Access phase Respons phase snoop_flag exfail_flag snoop_mid snoop_addr A0 MID0 D0 ExR A0 MID0 D1 ExW A0 MID0 APP SRAM N success success Figure APP 111 Success Case 1 of Exclusive Access snoop_flag exfail_flag snoop_mid snoop_addr A0 MID0 D0 ExR A0 MID0 D1 ExW A0 MID0 APP SRAM N success success D0 ExR A1 M...

Page 926: ... snoop_addr A0 MID0 D0 ExR A0 MID0 D2 ExW A0 MID0 APP SRAM N success fail D1 W A0 MID1 success Write invalid Access phase Respons phase Figure APP 113 Failure Case 1 of Exclusive Access snoop_flag exfail_flag snoop_mid snoop_addr A0 MID1 D0 ExR A0 MID1 D2 ExW A0 MID1 APP SRAM N success success D0 ExR A0 MID0 success D1 ExW A0 MID0 fail Write invalid Access phase Respons phase Figure APP 114 Failur...

Page 927: ...features of monitoring of exclusive accesses to APP SUB Bus Failure will be returned to the exclusive write ExW However in the case that BUS_SNOOP_DISABLE bus_snoop_disable 1 b1 success will be returned Even if for failure cases write to the slave is performed Success will be returned to the exclusive read ExR ...

Page 928: ...ON the power domain PWD_APP if required Refer to 3 13 4 16 2 section step3 Start the ADSP Refer to 3 13 4 16 3 section Perform the ADSP s stop control in the following order step1 Stop the ADSP Refer to 3 13 4 16 6 section step2 Turn OFF the power domain PWD_APP_DSP if required Refer to 3 13 4 16 7 section step3 Stop the clock turn OFF the power domain PWD_APP if required For power supply control ...

Page 929: ...pter 3 4 1 Clock division ratio setting GEAR_AHB gear_m_ahb arbitrary division ratio denominator write GEAR_AHB gear_n_ahb arbitrary division ratio numerator write 2 Clock supply Initialization of internal circuit CK_GATE_AHB ck_gate_dsp N 1 3 Clock stop CK_GATE_AHB ck_gate_dsp N 0 4 ADSP start preparation Transfer the program codes to the APP SRAM and do the address converter setting For address ...

Page 930: ..._dsp N 0 2 Clock stop CK_GATE_AHB ck_gate_dsp N 0 3 Reset release RESET xrs_dsp N 1 4 Clock supply CK_GATE_AHB ck_gate_dsp N 1 3 13 4 16 6 ADSP Stop Control ADSP stop using System and I O Processor or ADSP other than the target ADSP Note about N E g ADSP0 means that N 0 ADSP1 means that N 1 in the same way ADSP5 means that N 5 Precondition The ADSP must be in SLEEPING state so that uncompleted acc...

Page 931: ...equency operating at 26 MHz as an example The SYSIOP offers the following functions System and I O Processor This is the processor block referred to as SYSCPU hereinafter that is centered around the Arm Cortex M0 The following functions are equipped Arm Cortex M0 The communication unit that performs communication between the Application Processor and CPU and between the GNSS DSP and CPU Interrupt ...

Page 932: ...that are used according to the application SYDMAC memory to memory transfer and Crypto engine SYSUBDMAC Crypto engine SPI FLASH Interface and Configurable I O SDMAC Sensor Engine HDMAC Host Interface RTC The timer block that counts the time using the RTC clock For details see Section 3 6 COMMIF Has each of the interface circuits of the I2C SPI UART I2C Interface for Configurable I O Communication ...

Page 933: ...LASH For details refer to Section 3 10 HOSTIFC The I F block for communication with the CXD5602 s external host In addition to supporting the I2C UART SPI communication I F sequential control is also possible for reduced power consumption For details refer to Section 0 Debugger I F A debugger interface circuit It has a user authentication function that uses a debug path ...

Page 934: ... correspond to each function block of the SYSIOP are as follows PWD_CORE 256 KByte SRAM in System Control and I O Processor Memory PWD_SYSIOP System and I O Processor DMAC SYDMAC HDMAC SDMAC HOSTIFC Debugger I F FREQDISC RTC PWD_SYSIOP_SUB COMMIF Block SPI FLASH Interface 128 KByte ROM in System Control and I O Processor Memory Crypto Engine in System Control and I O Domain SYSUBDMAC ...

Page 935: ...ol 3 14 3 1 SYSIOP Clock Configuration Diagram Figure SYSIOP Clock and Reset Control 116 shows the SYSIOP clock configuration diagram Within the figure the SEL number DIV number and CG SYS SUB number are linked to the numbers within Table SYSIOP Clock and Reset Control 802 Table SYSIOP Clock and Reset Control 807 and Table SYSIOP Clock and Reset Control 808 For areas where the register names are d...

Page 936: ...d 1 250 ck_rtc_pre SPI Flash Controller HCLK SFCLK SFC_HCLK CK GATE CG SUB07 CK GATE CG SUB08 CK GATE CG SUB09 1 M ck_sfc_sfclk_gear DIV 3 1 2 ck_sfc_hclk_low_gear AHB AHB BusBridge CK GATE CG SYS14 0 3 2 1 CKSEL_SCU SEL_SCU ck_scu_pre Reserved Crypto HCLK CK GATE CG SUB06 0 1 ck_32k_pre 1 250 0 3 2 1 Register PCLK CK_RTC RTC0 CK_RTC_INV CK_RTC Register PCLK CK_RTC CKSEL_SCU SEL_SCU_32K RF_CLK_IN ...

Page 937: ...0 26 000 8 192 0 032768 System and I O Processor MHz 32 500 31 200 26 000 8 192 0 032768 System Bus MHz 32 500 31 200 26 000 8 192 0 032768 SYSPLL 3 14 3 3 Clock Switching Confirmation 3 14 3 3 1 Function Details The clock source of the clock supplied to each block can be changed using the API The selected clock can be confirmed by reading the register ...

Page 938: ...SYSPLL clock not divided 2 b01 SYSPLL clock divided by 2 2 b10 SYSPLL clock divided by 4 2 b11 SYSPLL clock divided by 4 Reserved RO 19 18 0 Reserved SEL_FREQD IS RW 17 16 2 b00 Indicated as SEL 4 in Figure SYSIOP Clock and Reset Control 116 FREQDISC clock source switching 2 b00 RCOSC 2 b01 XOSC 2 b10 The frequency divided clock selected by CKSEL_SYSIOP SEL_FD_PLL 2 b11 Prohibited setting Reserved...

Page 939: ...F_PLL_1_DIV 2 b11 RTC Clock 0x041004D0 CKSEL_S YSIOP_S UB Reserved RO 31 1 0 Reserved SEL_UART1 RW 0 0 Indicated as SEL 6 in Figure SYSIOP Clock and Reset Control 116 UART1 clock source switching 1 Reserved 0 The clock selected by CKDIV_COM CK_COM 3 14 3 4 Clock Frequency Division Switching Confirmation 3 14 3 4 1 Function Details Using the API the frequency division ratio of the target clock can ...

Page 940: ...sion B and Table SYSIOP Clock and Reset Control 805 for frequency division C Table SYSIOP Clock and Reset Control 763 System and I O Processor Frequency Division Setting CKDIV_CPU_DSP_BUS CK_M0 Frequency Division A 0 1 1 2 2 3 3 4 Register value 1 28 29 29 30 30 31 31 32 Table SYSIOP Clock and Reset Control 764 AHB Clock Frequency Division Setting CKDIV_CPU_DSP_BUS CK_AHB Frequency Division B 0 1 ...

Page 941: ...oller based on the ck_cpu_bus ck_sfc_sfclk_gear frequency division D ck_sfc_hclk_low_gear frequency division D x 2 Note Refer to Table SYSIOP Clock and Reset Control 806 for the frequency division D Table SYSIOP Clock and Reset Control 766 Frequency Division Setting of Clock for the SPI Flash Controller CKDIV_CPU_DSP_BUS SFC_HCLK_LOW Frequency Division D 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10...

Page 942: ...28 0 Indicated as DIV 3 in Figure SYSIOP Clock and Reset Control 116 Frequency division setting ratio against System and I O Processor clock of ck_sfc_sfclk_gear 0 divided by 1 1 divided by 2 2 divided by 3 3 divided by 4 4 divided by 5 5 divided by 6 6 divided by 7 7 divided by 8 8 divided by 9 9 divided by 10 10 divided by 16 11 divided by 32 12 divided by 64 13 divided by 128 14 divided by 256 ...

Page 943: ...n Figure SYSIOP Clock and Reset Control 116 Frequency division setting ratio against CPU clock of AHB clock 0 divided by 1 1 divided by 2 2 divided by 4 3 divided by 8 4 divided by 6 5 6 7 Prohibited settings Reserved RO 15 5 0 Reserved CK_M0 RW 4 0 0 Indicated as DIV 0 in Figure SYSIOP Clock and Reset Control 116 Frequency division setting ratioagainst ck_cpu_bus of System and I O Processor 0 div...

Page 944: ...dicated as DIV 5 in Figure SYSIOP Clock and Reset Control 116 HOSTIFC frequency switching setting 0 divided by 1 1 divided by 2 30 divided by 31 31 divided by 32 0x04100518 GEAR_STAT Reserved RO 31 3 0 Reserved SFC_STA T RO 2 0 Indicated as DIV 3 in Figure SYSIOP Clock and Reset Control 116 Update status of CKDIV_CPU_DSP_BUS SFC_HCLK_LOW setting value 0 Update completed 1 Update in progress AHB_ST...

Page 945: ...SIOP Clock and Reset Control 116 Update status of CKDIV_CPU_DSP_BUS CK_M0 setting value 0 Update completed 1 Update in progress 3 14 3 5 Clock Enable Confirmation 3 14 3 5 1 Function Details Using the API supply stop control of the clocks supplied to each block can be performed ...

Page 946: ... Control 116 Clock enable for SPI2 HOSI2C RW 16 0 Indicated as CG SYS16 in Figure SYSIOP Clock and Reset Control 116 Clock enable for I2C3 HOSTIFC_SEQ RW 15 0 Indicated as CG SYS15 in Figure SYSIOP Clock and Reset Control 116 Clock enable for HOSTIFC processor BRG_SCU RW 14 0 Indicated as CG SYS14 in Figure SYSIOP Clock and Reset Control 116 Clock enable for AHB APB bridge between PWD_SYSIOP and P...

Page 947: ... FREQDISC APB RW 8 1 Indicated as CG SYS08 in Figure SYSIOP Clock and Reset Control 116 Clock enable for the APB within PWD_SYSIOP AHB_DMAC2 RW 7 0 Indicated as CG SYS07 in Figure SYSIOP Clock and Reset Control 116 Clock enable for SYDMAC AHB_DMAC1 RW 6 0 Indicated as CG SYS06 in Figure SYSIOP Clock and Reset Control 116 Clock enable for HDMAC AHB_DMAC0 RW 5 0 Indicated as CG SYS05 in Figure SYSIO...

Page 948: ...ART0 RW 0 0 Indicated as CG SYS00 in Figure SYSIOP Clock and Reset Control 116 UART0 communication clock enable 0x04103420 SYSIOP_SUB_C KEN Reserved RO 31 17 0 Reserved COM_UART_PC LK RW 16 0 Indicated as CG SUB10 in Figure SYSIOP Clock and Reset Control 116 Clock enable for APB of UART1 Reserved RO 15 10 0 Reserved SFC_HCLK_LO W RW 9 1 Indicated as CG SUB09 in Figure SYSIOP Clock and Reset Contro...

Page 949: ...SIOP Clock and Reset Control 116 Clock enable for UART1 AHB_DMAC3 RW 2 0 Indicated as CG SUB02 in Figure SYSIOP Clock and Reset Control 116 Clock enable for SYSUBDMAC COM_BRG RW 1 0 Indicated as CG SUB01 in Figure SYSIOP Clock and Reset Control 116 Clock enable for AHB asynchronous bridge master of I2C2 UART1 and SPI0 AHB_BRG_COM IF RW 0 0 Indicated as CG SUB00 in Figure SYSIOP Clock and Reset Con...

Page 950: ...XRST_HOS_SEQ AHB APB BusBridge System and I O Processor RST_CPU_P0_X SYSIOP_MAIN_BUS HRESTn FreqDisc PRESETn RTC0 PRESETn RTC1 PRESETn AHB APB BusBridge SPI Flash Controller HRESETn AHB AHB BusBridge Crypto XRST_SK RST_CPU_SYS_X RST 0 PWD_RESET0 PWD_SYSIOP_SUB Auto PWD_SYSIOP_SUB Power Domain ON RST 3 RST 8 PWD_RESET0 PWD_SYSIOP_SUB RST 2 RST 5 RST 7 PRESETn RST 6 RST 1 Figure SYSIOP Clock and Res...

Page 951: ...17 Reset for I2C4 0 Reset is performed 1 Reset release Reserved RO 15 12 0 Reserved XRST_I2CM_SU B RW 11 0 Indicated as RST 8 in Figure SYSIOP Clock and Reset Control 117 Reset for I2C2 XRST_UART0 RW 10 0 Indicated as RST 7 in Figure SYSIOP Clock and Reset Control 117 Reset for UART0 XRST_HOSTIFC _ISOP RW 9 0 Indicated as RST 6 in Figure SYSIOP Clock and Reset Control 117 Reset for HOSTIFC Sequenc...

Page 952: ...al 952 1010 XRST_SFC RW 1 1 Indicated as RST 1 in Figure SYSIOP Clock and Reset Control 117 Reset for SPI Flash Controller XRST_SPIM RW 0 0 Indicated as RST 0 in Figure SYSIOP Clock and Reset Control 117 Reset for SPI0 ...

Page 953: ...requency support Master clock High performance mode 256fs 128fs 64fs of bit clock frequency Low power mode 128fs 64fs of bit clock frequency Slave clock High performance mode 256fs 128fs 64fs of bit clock frequency Low power mode 128fs 64fs of bit clock frequency Sampling rate High performance mode Master mode 192kHz 96kHz 48kHz Slave mode 192kHz 96kHz 48kHz 44 1kHz 16kHz 8kHz Low power mode Maste...

Page 954: ...p to 24 552MHz 3 17 eMMC eMMC Interface eMMC 4 41 Protocol compatible only SDR mode 1K Byte 32bit x 256word x2 FIFOs for Tx Rx Communication speeds High Performance mode up to 39 000MHz Low Power mode up to 24 552MHz 3 18 USB USB 2 0 Device Complies with USB2 0 Specification High speed up to 480 Mbps Not supported at Low Power mode On chip USB PHY transceiver Supports MSC MTP CDC PTP ACM and HID c...

Page 955: ... to 480x360 JPEG Y C 2M WQVGA JPEG High Quality mode 5M WQVGA JPEG Normal Quality mode Parallel Input rate up to 54MHz 3 20 2D Graphics 2D Graphics accelerator Bit Block Transfer Rotator Supported image format YCbCr422 RGB565 Supported rotate degree 0 90 180 270 degrees Color space Conversion YCbCr422 RGB565 3 operand raster operation ROP3 Alpha blending Scaling Horizontal direction x1 64 to x64 V...

Page 956: ...ADC and two channels of 32 rows are prepared for the HPADC Each channel has an interface for DMA REQ ACK signals to perform DMA processing and for interrupt signals to perform Watermark Level detection Furthermore the ADCIF module has a register block to control analog circuits and the APB interface to exchange data with the CPU and the SCU internal sequencer For data storage at the SCU and the FI...

Page 957: ...AD_LV_DOUT R R for GNSS toggle data 0 1 toggle data 0 1 2 3 HPADC_Wrapper HPAD_HV_AIN0 HPAD_HV_AIN1 HPAD_LV_DATA_EN0 HPAD_LV_DOUT0 HPAD_LV_DATA_EN1 HPAD_LV_DOUT1 1 SEN_AIN2 1 SEN_AIN3 1 SEN_AIN4 1 SEN_AIN5 decimation decimation SCU_ADCIF_FIFO L0 16 words SCU_ADCIF_FIFO L1 16 words SCU_ADCIF_FIFO L2 16 words SCU_ADCIF_FIFO L3 16 words decimation decimation 2 s Comp CIC3 Filter 2 s Comp CIC3 Filter ...

Page 958: ...el power supply domains there are module areas for power supply control shown below Power supply control registers for such areas are held in the TOPREG Table ADC 772 Power Supply Information Target for Power Supply Control Address Offset Bit Bit Name TOPREG Description LPADC 0x0004 29 WEN_LPADC LPADC Power supply control Write Enable 0 Disable 1 Enable 13 LPADC LPADC Power supply control 0 OFF 1 ...

Page 959: ...SCU Main 1 CK_SCU_SCU_SC 13 MHz 13 MHz Controls SCU Main CPU only 1 CK_SCU_XOSC 13 MHz 13 MHz For HPADC CK_SCU_RC8M 8 MHz 8 MHz For HPADC CK_SCU_U32KL 32 kHz 32 kHz For LPADC CK_SCU_U32KH 32 kHz 32 kHz For HPADC 1 For CK_SCU_SCU and CK_SCU_SCU_SC refer to Section of the Clock Control described in Chapter of the SCU 3 9 The following describes the schematic diagram of the clock control ...

Page 960: ...ADC are controlled by the following register Table ADC 774 Clock Control Register List Control from Block Name Register Name Offset Comment CPU TOPREG SCU_CKEN 0x071c TOPREG control area For EN 1 and EN 2 in Figure ADC 120 and the summary of clock source selection refer to Section of the Clock Control described in Chapter of the SCU 3 9 3 21 5 2 Clock for the LPADC CK_SCU_U32KL This is a clock to ...

Page 961: ...ncy division of CK_SCU_XOSC and CK_SCU_RC8M can be set in the HPADC and the setting is controlled by the ADCIF register in the SCU as well The following describes the summary of input clock selection Table ADC 775 Input Clock Selection Clock Source Divider Circuit Clock Port Remarks RCRTC RCOSC divided by 250 Select one number from 1 2 4 32768 to divide frequency CK_SCU_32KL For LPADC Select one n...

Page 962: ... GPIO I O Config 0x0704 4 XRST_SCU_LPADC 1 b1 0 Reset 1 Reset release HPADC PMU CRG GPIO I O Config 0x0704 2 XRST_SCU_HPADC 1 b1 3 21 7 Interrupt The ADCIF is equipped in the SCU For the details of the interrupt refer to the chapter 3 3 Interrupt 3 21 8 FIFO writing Process The following describes the data flow LPADC0 LPADC1 LPADC2 MATH_PROC Sequencer Processing FIFO LPADC3 HPADC0 HPADC1 ADCIF Fig...

Page 963: ...termark multiple of the eight samples The remaining number of the 8 FIFO data 8 INTERVAL sec 165 scu_clock_freq Hz In this formula INTERVAL means sample s interval second 3 21 9 Gain Control 3 21 9 1 Gain Control of the LPADC The LPADC has a fixed voltage range there is no gain control Input the data with appropriate signal level based on the LSI s specifications and perform appropriate signal pro...

Page 964: ...cale Attenuator Output 1st Amplifier Output differential Amplifier Output ATT Gain1st Gain2nd ADC output Data 1 6Vpp 0 8Vpp 0 8Vpp 0 8Vppd 0 8Vpp 0 8Vpp 0 8Vppd 0 8Vpp 1023 Dout 0 0 8Vppd 0 2Vpp 0 2Vpp 1023 Dout 0 0 8Vppd 0 16Vpp 0 16Vpp 0 32Vpp 1023 Dout 0 6dB 8dB 6dB 0 8Vpp 12dB 0 8Vppd 0 4Vpp 1023 Dout 0 0 8Vpp 6dB 0 4Vpp gain 0dB setting Total gain 6dB setting Total gain 12dB setting Total gai...

Page 965: ...nce bottleneck HPADC 37 000 41 000 The following describes the sensor conditions with sensor operation Six byte read transfer per event for each sensor three axes are assumed The total of the sampling frequencies of all SPI sensors is 820 Hz 1 Hz when the clock is 32 kHz The total of the sampling frequencies of all I2C sensors is 180 Hz 1 Hz when the clock is 32 kHz The SPI s transfer rate is abou...

Page 966: ...nization Function with PWM 3 21 11 1 PWM Output Based on ADC The PWM output can be performed based on the AD data confirmation signals synchronization signals from the ADC LPADC HPADC For details refer to Section 3 9 11 PWM Control described in Chapter of the SCU 3 21 11 2 ADC Data Import Based on the PWM Output Based on the rise of the PWM output timing of importing the ADC data in the SCU can be...

Page 967: ...g two element vector 0x00000000 0x280 HPADC0_A0 RW 32 HPADC0 clock selection 0x00000000 0x284 HPADC0_A1 RW 32 HPADC0 enable control 0x00000000 0x288 HPADC0_A2 RW 32 HPADC0 clock enable control 0x00000000 0x28C HPADC0_A3 RW 32 HPADC0 LPF control 0x00000100 0x290 HPADC0_D0 RW 32 HPADC0 software reset 0x00000000 0x294 HPADC0_D1 RW 32 HPADC0 basic setting 0x00000010 0x298 HPADC0_D2 RW 32 Permission pr...

Page 968: ...write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LV_ADC_EN Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 LV_ADC_EN RW 0x0 Permission prohibition of the LPADC operation Switching between standby and move 1 b0 standby 1 b1 active default ...

Page 969: ... 9 8 7 6 5 4 3 2 1 0 Reserved LV_CH_SEL_INV Reserved LV_CH_SEL_MODE Bits Name Type Reset Value Description 31 10 Reserved RO 0x000000 Reserved 9 8 LV_CH_SEL_INV RW 0x0 ADCH selector for GNSS sets only a CH which are in operation shown below 2 b00 CH0 2 b01 CH1 2 b10 CH2 2 b11 CH3 7 3 Reserved RO 0x00 Reserved 2 0 LV_CH_SEL_MODE RW 0x0 LPADC channel switching mode 3 b000 CH0 3 b001 CH1 3 b010 CH2 3...

Page 970: ... Address 0x210 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SW_RESET Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 SW_RESET RW 0x0 LPADC software reset common to each LPADC ...

Page 971: ...ed 20 12 SAMP_RATIO2 RW 0x000 Bit0 Synchronization signal from the PWM0 is enabled Bit1 Synchronization signal from the PWM1 is enabled Bit2 Synchronization signal from the PWM2 is enabled Bit3 Synchronization signal from the PWM3 is enabled Bit4 Synchronization signal from the PWM4 is enabled Bit5 Synchronization signal from the PWM5 is enabled Bit6 Synchronization signal from the PWM6 is enabled...

Page 972: ...1 5 0x218 LPADC_D2 Details Permission Prohibition of the LPADC ADC Data Acceptance Table ADC 785 Local Address 0x218 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FIFO_EN Bits Name Type Reset Value Description 31 4 Reserved RO 0x0000000 Reserved 3 0 FIFO_EN RW 0x0 Permission prohibition of the LPADC...

Page 973: ...ed 20 12 SAMP_RATIO2 RW 0x000 Bit0 Synchronization signal from the PWM0 is enabled Bit1 Synchronization signal from the PWM1 is enabled Bit2 Synchronization signal from the PWM2 is enabled Bit3 Synchronization signal from the PWM3 is enabled Bit4 Synchronization signal from the PWM4 is enabled Bit5 Synchronization signal from the PWM5 is enabled Bit6 Synchronization signal from the PWM6 is enabled...

Page 974: ...XD5602 User Manual 974 1010 5 DMA_HS_EN RW 0x0 Permission prohibition of using LPADC DMA signals 4 Reserved RO 0x0 Reserved 3 0 FIFO_WATERMARK RW 0x8 LPADC FIFO Watermark Determination of the DMA traffic ...

Page 975: ...ed 20 12 SAMP_RATIO2 RW 0x000 Bit0 Synchronization signal from the PWM0 is enabled Bit1 Synchronization signal from the PWM1 is enabled Bit2 Synchronization signal from the PWM2 is enabled Bit3 Synchronization signal from the PWM3 is enabled Bit4 Synchronization signal from the PWM4 is enabled Bit5 Synchronization signal from the PWM5 is enabled Bit6 Synchronization signal from the PWM6 is enabled...

Page 976: ...XD5602 User Manual 976 1010 5 DMA_HS_EN RW 0x0 Permission prohibition of using LPADC DMA signals 4 Reserved RO 0x0 Reserved 3 0 FIFO_WATERMARK RW 0x8 LPADC FIFO Watermark Determination of the DMA traffic ...

Page 977: ...ed 20 12 SAMP_RATIO2 RW 0x000 Bit0 Synchronization signal from the PWM0 is enabled Bit1 Synchronization signal from the PWM1 is enabled Bit2 Synchronization signal from the PWM2 is enabled Bit3 Synchronization signal from the PWM3 is enabled Bit4 Synchronization signal from the PWM4 is enabled Bit5 Synchronization signal from the PWM5 is enabled Bit6 Synchronization signal from the PWM6 is enabled...

Page 978: ...XD5602 User Manual 978 1010 5 DMA_HS_EN RW 0x0 Permission prohibition of using LPADC DMA signals 4 Reserved RO 0x0 Reserved 3 0 FIFO_WATERMARK RW 0x8 LPADC FIFO Watermark Determination of the DMA traffic ...

Page 979: ...12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LV_CLK_XOSC_DIV Reserved LV_CLK_OSC_SEL Bits Name Type Reset Value Description 31 6 Reserved RO 0x0000000 Reserved 5 4 LV_CLK_XOSC_DIV RW 0x0 Division ratio setting port when using the XOSC clock 0 clock divided by 2 1 clock divided by 3 2 clock divided by 4 3 clock divided by 6 3 1 Reserved RO 0x0 Reserved 0 LV_CLK_OSC_SEL RW 0x0 Clock selection port when per...

Page 980: ...gister Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LV_BGR_EN Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 LV_BGR_EN RW 0x0 LV BGR Circuit Enable Switching between standby and move 1 b0 standby 1 b1 active default ...

Page 981: ...791 Local Address 0x250 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VECTOR_SEL Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 VECTOR_SEL RW 0x0 Permission prohibition of handling two element vector ...

Page 982: ...0 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LV_CLK_U32_SEL0 Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 LV_CLK_U32_SEL0 RW 0x0 Clock selection port 0 high speed clock 1 low speed clock ...

Page 983: ...EF_EN LV_LPF0_EN LV_ADC0_EN Bits Name Type Reset Value Description 31 3 Reserved RO 0x00000000 Reserved 2 LV_ADC0_REF_EN RW 0x0 ADC0 REF circuit enable port Setting for the ADC reference and operation mode 0 0 standby 0 1 external enable 1 0 active default 1 1 active 1 LV_LPF0_EN RW 0x0 LPF0 enable control port 0 0 standby 0 1 standby 1 0 active default 1 1 prohibited setting 0 LV_ADC0_EN RW 0x0 P...

Page 984: ... Local Address 0x288 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LV_CLKOUT0_EN Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 LV_CLKOUT0_EN RW 0x0 ADC0 clock output enable port ...

Page 985: ...ved LV_LPF0_XSTARTUP LV_ADC0_REFCTRL Reserved LV_ADC0_REFLP_EN LV_ADC0_PREAMPLP_EN Bits Name Type Reset Value Description 31 26 Reserved RO 0x00 Reserved 25 24 LV_LPF0_ATT_SEL RW 0x0 Attenuator gain switching at LPF input part Refer to Section 3 21 9 1 2 b00 x1 default 2 b01 x0 75 2 b10 x0 5 2 b11 x0 25 prohibited setting 23 Reserved RO 0x0 Reserved 22 20 LV_LPF0_MODE RW 0x0 Switching port of the ...

Page 986: ...1100 x0 71 4 b1101 x0 63 4 b1110 x0 56 4 b1111 x0 5 15 12 LV_LPF0_GAIN1ST RW 0x0 LPF gain switching function first stage amplifier Refer to Section 3 21 9 1 4 b0000 x1 default 4 b0001 x1 25 4 b0010 x1 5 4 b1110 x4 5 4 b1111 x4 75 11 10 LV_LPF0_FC RW 0x0 LPF frequency band switching function 2 b00 75 kHz default 2 b01 150 kHz 2 b10 37 5 kHz 2 b11 No LPF Amplifier only 9 Reserved RO 0x0 Reserved 8 L...

Page 987: ... b1000 X3 X1 4 b1001 X3 X2 4 b1010 X3 X3 4 b1011 X3 X4 4 b1100 X1 X4 4 b1101 X2 X4 4 b1110 X3 X4 4 b1111 X4 X4 3 2 Reserved RO 0x0 Reserved 1 LV_ADC0_REFLP_EN RW 0x0 Low power mode signal of the voltage reference circuit 0 0 Standby 0 1 Standby 1 0 active default 1 1 Prohibited setting 0 LV_ADC0_PREAMPLP _EN RW 0x0 ADC0 PreAMP low power mode signal Control used when monitoring the ADC sampling clo...

Page 988: ...DC 796 Local Address 0x290 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SW_RESET Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 SW_RESET RW 0x0 HPADC0 software reset ...

Page 989: ..._RATIO2 RW 0x000 Bit0 Synchronization signal from the PWM0 is enabled Bit1 Synchronization signal from the PWM1 is enabled Bit2 Synchronization signal from the PWM2 is enabled Bit3 Synchronization signal from the PWM3 is enabled Bit4 Synchronization signal from the PWM4 is enabled Bit5 Synchronization signal from the PWM5 is enabled Bit6 Synchronization signal from the PWM6 is enabled Bit7 Synchro...

Page 990: ...ohibition of the HPADC0 ADC Data Acceptance Table ADC 798 Local Address 0x298 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DECIFIFO_EN Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 DECIFIFO_EN RW 0x0 Permission prohibition of the HPADC0 Decimation and FIFO operation ...

Page 991: ...0 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LV_CLK_U32_SEL1 Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 LV_CLK_U32_SEL1 RW 0x0 Clock selection port 0 high speed clock 1 low speed clock ...

Page 992: ...ADC1_REF_EN LV_LPF1_EN LV_ADC1_EN Bits Name Type Reset Value Description 31 3 Reserved RO 0x00000000 Reserved 2 LV_ADC1_REF_EN RW 0x0 ADC1 REF circuit enable port ADC reference operation mode setting 0 0 standby 0 1 external enable 1 0 active default 1 1 active 1 LV_LPF1_EN RW 0x0 LPF1 enable control port 0 0 standby 0 1 standby 1 0 active default 1 1 prohibited setting 0 LV_ADC1_EN RW 0x0 Permiss...

Page 993: ... Local Address 0x2C8 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LV_CLKOUT1_EN Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 LV_CLKOUT1_EN RW 0x0 ADC1 clock output enable port ...

Page 994: ...LV_LPF1_XSTARTUP LV_ADC1_REFCTRL Reserved LV_ADC1_REFLP_EN LV_ADC1_PREAMPLP_EN Bits Name Type Reset Value Description 31 26 Reserved RO 0x00 Reserved 25 24 LV_LPF1_ATT_SEL RW 0x0 Attenuator gain switching at LPF input part Refer to Section 3 21 9 1 2 b00 x1 default 2 b01 x0 75 2 b10 x0 5 2 b11 x0 25 prohibited setting 23 Reserved RO 0x0 Reserved 22 20 LV_LPF1_MODE RW 0x0 Switching port of the LPF ...

Page 995: ...b1100 x0 71 4 b1101 x0 63 4 b1110 x0 56 4 b1111 x0 5 15 12 LV_LPF1_GAIN1ST RW 0x0 LPF gain switching function first stage amplifier Refer to Section 3 21 9 1 4 b0000 x1 default 4 b0001 x1 25 4 b0010 x1 5 4 b1110 x4 5 4 b1111 x4 75 11 10 LV_LPF1_FC RW 0x0 LPF frequency band switching function 2 b00 75 kHz default 2 b01 150 kHz 2 b10 37 5 kHz 2 b11 No LPF Amplifier only 9 Reserved RO 0x0 Reserved 8 ...

Page 996: ...switching 3 b000 700mV default 3 b001 750mV 3 b010 800mV 3 b011 850mV 3 b100 500mV 3 b101 550mV 3 b110 600mV 3 b111 650mV 3 2 Reserved RO 0x0 Reserved 1 LV_ADC1_REFLP_EN RW 0x0 Low power mode signal of the REF circuit 0 0 standby 0 1 standby 1 0 active default 1 1 prohibited setting 0 LV_ADC1_PREAMPLP _EN RW 0x0 ADC1 PreAMP low power mode signal Control used when monitoring the ADC sampling clock ...

Page 997: ...DC 803 Local Address 0x2D0 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SW_RESET Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 SW_RESET RW 0x0 HPADC1 software reset ...

Page 998: ..._RATIO2 RW 0x000 Bit0 Synchronization signal from the PWM0 is enabled Bit1 Synchronization signal from the PWM1 is enabled Bit2 Synchronization signal from the PWM2 is enabled Bit3 Synchronization signal from the PWM3 is enabled Bit4 Synchronization signal from the PWM4 is enabled Bit5 Synchronization signal from the PWM5 is enabled Bit6 Synchronization signal from the PWM6 is enabled Bit7 Synchro...

Page 999: ...CXD5602 User Manual 999 1010 5 DMA_HS_EN RW 0x0 Permission prohibition of using HPADC1 DMA signals 4 0 FIFO_WATERMARK RW 0x10 HPADC1 FIFO Watermark ...

Page 1000: ...al Address 0x2D8 Register Type RW read write Reset Value 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DECIFIFO_EN Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 Reserved 0 DECIFIFO_EN RW 0x0 Permission prohibition of the HPADC1 Decimation and the FIFO operation ...

Page 1001: ...ODE RO 0xADC1F000 Revision code of the SCU_ADCIF register map revision of the last three digits 3 21 12 1 27 0x3D4 SCU_ADCIF_CKPOWER Details Table ADC 807 Local Address 0x3D4 Register Type RW read write Reset Value 0x00000001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CK_POWEREN Bits Name Type Reset Value Description 31 1 Reserved RO 0x00000000 R...

Page 1002: ... CK_SCU_SCU is OFF turn it ON when setting registers Set the registers of the LPADC If necessary turn CK_SCU_SCU OFF after the setting is completed Caution CK_SCU_U32KL is the main clock of the LPADC therefore it cannot be stopped when using the LPADC 3 21 14 Restrictions 3 21 14 1 Delay at the LPADC Startup When starting the LPADC up there will be maximum one sampling period of delay until the fi...

Page 1003: ...CXD5602 User Manual 1003 1010 3 21 15 Error Handling Some error interrupts for the ADC may occur Refer to Section 3 9 14 of the Errror Handling described in Chapter of the SCU ...

Page 1004: ...Connectivity and Audio equipped with six Arm Cortex M4 processors with FPU 32 bit RISC indicated in エラー参照元が見つかりません Refer to Section 2 5 1 as well APP_DSP The APP_DSP corresponds to the functional block of the Application Domain excluding Imaging Storage and Audio APP MAIN Bus The APP MAIN Bus means the matrix bus which connects Application Processor with the APP SRAM and the APP SUB Bus APP SRAM ...

Page 1005: ...s the frequency band of the GNSS signal RTC Real Time Clock For the RTC refer to Chapter 3 6 SCU Sensor Domain The SCU is the block which is equipped with the HPADC LPADC and the interface to the external sensors Please check エラー参照元が見つかりません For details refer to Chapter 3 9 Sleep Sleep is the status that any of the power domains of the CXD5602 becomes OFF or any of the DSPs belonging to the power...

Page 1006: ... means Cortex M0 and Arm Cortex M4 processor with FPU 32 bit RISC in the CXD5602 4 2 Reference PrimeCell µDMA Controller PL230 Technical Reference Manual PrimeCell DMA Controller PL080 Technical Reference Manual PrimeCell Single Master DMA Controller PL081 Technical Reference Manual PrimeCell Synchronous Serial Port PL022 Technical Reference Manual PrimeCell UART PL011 Technical Reference Manual A...

Page 1007: ...CXD5602 User Manual 1007 1010 Revision History Date Revision Description 2019 07 05 1 0 0 Initial version ...

Page 1008: ...ference purpose only and the availability and disclosure of such Product Information and its usage by Customer shall not be construed as giving any indication that Sony its subsidiaries and or its licensors will license any right including intellectual property rights in such Product Information by any implication or otherwise Furthermore even if circuit examples are included in this specification...

Page 1009: ...OF LIABILITY TO THE EXTENT PERMITTED BY LAW SONY ITS SUBSIDIARIES AND OR THEIR AUTHORIZED REPRESENTATIVES SHALL NOT BE LIABLE FOR ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR BREACH OF ANY EXPRESS OR IMPLIED WARRANTY BREACH OF CONTRACT NEGLIGENCE STRICT LIABILITY OR UNDER ANY OTHER LEGAL THEORY RELATED TO THE PRODUCTS AND PRODUCT INFORMATION INCLUDING BUT NOT LIMITED TO ANY DAMAGES ARISING OUT OF L...

Page 1010: ...ontent relating to the Products contained in this specification may be revised or updated by Sony at Sony s sole discretion without prior notice to the Customer and Customer shall abide by their latest versions Such revisions or updates will be made available to Customer in a way as Sony deems appropriate Ensure that you have read and reviewed the notices contained in our delivery specification as...

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