Sony CXD5602, User Manual

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CXD5602 User Manual
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3.5 Clock and Reset (Clock Reset Generator)
3.5.1 Overview
The Clock Reset Generator (CRG) is the block that controls the clock and reset of the overall CXD5602.
For the clock sources, there are XOSC and RCOSC, SYSPLL, RTC Clock, and RF. The RTC Clock is supplied
from the outside of the CXD5602.
Clock control includes clock switching, clock supply, and clock stop. Reset control includes reset enable, reset
release, and reset enable using the WDT.
Since clock control and reset control are performed using the API, this Section describes the information for
confirming the statuses of the clock and reset.
3.5.2 Clock Scheme for CRG
Figure Clock and Reset (Clock Reset Generator)-33 shows the overall clock scheme for the CRG, while Figure
Clock and Reset (Clock Reset Generator)-34 shows the details. In Figure Clock and Reset (Clock Reset
Generator)-34, the registers indicated as ANA (number), SEL (number), and CG (number) are explained in the
register descriptions provided in the CRG Section. For descriptions on CKDIV_CPU_DSP_BUS.CK_M0,
CKDIV_CPU_DSP_BUS.CK_AHB , and CKDIV_CPU_DSP_BUS.CK_APB, refer to Section 3.14.3.