Modem SPI Register Descriptions
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor
5-9
Bit 11
arb_busy_mask
— The Packet RAM arbiter busy error
interrupt mask bit controls the arb_busy_err interrupt on
the IRQ pin.
1 = Allows arb_busy_err to generate an interrupt on
the IRQ pin.
0 = When arb_busy_err status bit is set, IRQ pin is not
asserted.
Bit 10
strm_data_mask
— The Stream Mode data error
interrupt mask bit controls the strm_data_irq interrupt
on the IRQ pin.
1 = Allows strm_data_err to generate an interrupt on
the IRQ pin.
0 = When strm_data_err status bit is set, IRQ pin is not
asserted.
Bit 9
pll_lock_mask
— The LO1 unlock detect mask bit
controls the pll_lock_irq interrupt on the IRQ pin.
1 = Allows pll_lock_irq to generate an interrupt on the
IRQ pin.
0 = When pll_lock_irq status bit is set, IRQ pin is not
asserted.
Bit 8
acoma_en
— The Acoma Mode enable bit controls
Doze Mode. Acoma is an enhanced power save mode
within Doze.
1 = The MC1321x stays in Doze until ATTN asserted.
Event Timer and Prescaler clocks disabled for
additional current savings.
0 = Normal operation. Doze is exited by TC2 match or
ATTN assertion.
Bit 4
doze_mask
— The Doze timer interrupt mask bit
controls the doze_irq interrupt on the IRQ pin.
1 = Allows doze_irq to generate an interrupt on the
IRQ pin.
0 = When doze_irq status bit is set, IRQ pin is not
asserted.
Bit 3
tmr4_mask
— The Event Timer four interrupt mask bit
controls the tmr4_irq interrupt on the IRQ pin.
1 = Allows tmr4_irq to generate an interrupt on the
IRQ pin.
0 = When tmr4_irq status bit is set, IRQ pin is not
asserted.
Bit 2
tmr3_mask
— The Event Timer three interrupt mask bit
controls the tmr3_irq interrupt on the IRQ pin.
1 = Allows tmr3_irq to generate an interrupt on the
IRQ pin.
0 = When tmr3_irq status bit is set, IRQ pin is not
asserted.
Bit 1
tmr2_mask
— The Event Timer two interrupt mask bit
controls the tmr2_irq interrupt on the IRQ pin.
1 = Allows tmr2_irq to generate an interrupt on the
IRQ pin.
0 = When tmr2_irq status bit is set, IRQ pin is not
asserted.
Bit 0
tmr1_mask
— The Event Timer one interrupt mask bit
controls the tmr1_irq interrupt on the IRQ pin.
1 = Allows tmr1_irq to generate an interrupt on the
IRQ pin.
0 = When tmr1_irq status bit is set, IRQ pin is not
asserted.
Table 5-7. Register 05 Description (continued)
Name
Description
Operation
Summary of Contents for freescale semiconductor MC13211
Page 40: ...MC1321x Pins and Connections MC1321x Reference Manual Rev 1 6 2 6 Freescale Semiconductor...
Page 166: ...Modem Modes of Operation MC1321x Reference Manual Rev 1 6 7 22 Freescale Semiconductor...
Page 172: ...Modem Interrupt Description MC1321x Reference Manual Rev 1 6 8 6 Freescale Semiconductor...
Page 186: ...MCU Modes of Operation MC1321x Reference Manual Rev 1 6 10 8 Freescale Semiconductor...
Page 208: ...MCU Memory MC1321x Reference Manual Rev 1 6 11 22 Freescale Semiconductor...
Page 244: ...MCU Parallel Input Output MC1321x Reference Manual Rev 1 6 13 20 Freescale Semiconductor...
Page 288: ...MCU Central Processor Unit CPU MC1321x Reference Manual Rev 1 6 15 20 Freescale Semiconductor...
Page 308: ...MCU Timer PWM TPM Module MC1321x Reference Manual Rev 1 6 17 16 Freescale Semiconductor...
Page 338: ...Inter Integrated Circuit IIC MC1321x Reference Manual Rev 1 6 19 14 Freescale Semiconductor...
Page 372: ...Development Support MC1321x Reference Manual Rev 1 6 21 20 Freescale Semiconductor...
