NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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MCU Timer/PWM (TPM Module)
MC1321x Reference Manual, Rev. 1.6
17-6 Freescale Semiconductor
forces the PWM signal low. If ELSnA = 1, the counter overflow forces the PWM signal low and the output
compare forces the PWM signal high.
Figure 17-2. PWM Period and Pulse Width (ELSnA = 0)
When the channel value register is set to $0000, the duty cycle is 0 percent. By setting the timer channel
value register (TPM1CnVH:TPM1CnVL) to a value greater than the modulus setting, 100 percent duty
cycle can be achieved. This implies that the modulus setting must be less than $FFFF to get 100 percent
duty cycle.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register,
TPM1CnVH or TPM1CnVL, write to buffer registers. In Edge-PWM Mode, values are transferred to the
corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and
the value in the TPM1CNTH:TPM1CNTL counter is $0000. (The new duty cycle does not take effect until
the next full period.)
17.4.3 Center-Aligned PWM Mode
This type of PWM output uses the Up-/down-counting Mode of the timer counter (CPWMS = 1). The
output compare value in TPM1CnVH:TPM1CnVL determines the pulse width (duty cycle) of the PWM
signal and the period is determined by the value in TPM1MODH:TPM1MODL.
TPM1MODH:TPM1MODL should be kept in the range of $0001 to $7FFF because values outside this
range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output.
pulse width = 2 x (TPM1CnVH:TPM1CnVL) Eqn. 17-1
period = 2 x (TPM1MODH:TPM1MODL);
for TPM1MODH:TPM1MODL = $0001–$7FFF Eqn. 17-2
If the channel value register TPM1CnVH:TPM1CnVL is zero or negative (bit 15 set), the duty cycle will
be 0 percent. If TPM1CnVH:TPM1CnVL is a positive value (bit 15 clear) and is greater than the (non zero)
modulus setting, the duty cycle will be 100 percent because the duty cycle compare will never occur. This
implies the usable range of periods set by the modulus register is $0001 through $7FFE ($7FFF if
generation of 100 percent duty cycle is not necessary). This is not a significant limitation because the
resulting period is much longer than required for normal applications.
TPM1MODH:TPM1MODL = $0000 is a special case that should not be used with Center-aligned PWM
Mode. When CPWMS = 0, this case corresponds to the counter running free from $0000 through $FFFF,
PERIOD
PULSE
WIDTH
OVERFLOW OVERFLOW OVERFLOW
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
TPM1C