NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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MCU Internal Clock Generator (ICG)
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 14-11
14.3.9 Fixed Frequency Clock
The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is
equal to the internal bus clock, BUSCLK, in FBE Mode. In FEE Mode, XCLK is equal to ICGERCLK
÷
2
when the following conditions are met:
• (P
×
N)
÷
R
≥
4 where P is determined by RANGE (see Table 14-4 ), N and R are determined by
MFD and RFD, respectively (see Table 14-5 ).
• LOCK = 1.
If the above conditions are not true, then XCLK is equal to BUSCLK.
When the ICG is in either FEI or SCM Mode, XCLK is turned off. Any peripherals which can use XCLK
as a clock source must not do so when the ICG is in FEI or SCM Mode.
14.3.10 High Gain Oscillator
The oscillator has the option of running in a high gain oscillator (HGO) Mode, which improves the
oscillator's resistance to EMC noise when running in FBE or FEE Modes. This option is selected by
writing a 1 to the HGO bit in the ICGC1 register. HGO is used with both the high and low range oscillators
but is only valid when REFS = 1 in the ICGC1 register. When HGO = 0, the standard low-power oscillator
is selected.
If the high gain option is to be switched after the initial write to the ICGC1 register, then the ICG should
first be changed to SCM or FEI Mode to stop the external oscillator. Then the HGO bit can be modified
and FEE or FBE Mode can be re-selected in the same write to ICGC1. The oscillator will go through the
standard start-up delay before the ICG switches to the external oscillator.
FBE
(10)
FBE
(10)
X 0 — ICGERCLK/R ERCS = 1 —
FEE
(11)
X 0 — ICGERCLK/R —
LOCS = 1 &
ERCS = 1
FEE
(11)
FEE
(11)
0
f
ICGERCLK
2/f
ICGERCLK
ICGDCLK/R
3
ERCS = 1 and
DCOS = 1
—
1
f
ICGERCLK
128/f
ICGERCLK
ICGDCLK/R
(2)
ERCS = 1 and
DCOS = 1
—
1
CLKST will not update immediately after a write to CLKS. Several bus cycles are required before CLKST updates to the new
value.
2
The reference frequency has no effect on ICGOUT in SCM, but the reference frequency is still used in making the comparisons
that determine the DCOS bit
.
3
After initial LOCK; will be ICGDCLK/2R during initial locking process and while FLL is re-locking after the MFD bits are
changed.
Table 14-2. ICG State Table (continued)
Actual
Mode
(CLKST)
Desired
Mode
(CLKS)
Range
Reference
Frequency
(f
REFERENCE
)
Comparison
Cycle Time
ICGOUT
Conditions
1
for
CLKS = CLKST
Reason
CLKS1 =
CLKST