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MCU Modes of Operation

MC1321x Reference Manual, Rev. 1.6

Freescale Semiconductor

10-5

If Stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after
taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in
the MCU taking the appropriate interrupt vector.

A separate self-clocked source (

≈

1 kHz) for the real-time interrupt allows a wake up from Stop2 or Stop3

Mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in
that case the real-time interrupt cannot wake the MCU from stop.

10.6.4

Active BDM Enabled in Stop Mode

Entry into the Active Background Mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in the

Chapter 11, “MCU Memory”

. If ENBDM is set when the CPU executes a

STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
Stop Mode so background debug communication is still possible. In addition, the voltage regulator does
not enter its low-power standby state but maintains full internal regulation. If the user attempts to enter
either Stop1 or Stop2 with ENBDM set, the MCU will instead enter Stop3.

Most background commands are not available in Stop Mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or Wait
Mode. The BACKGROUND command can be used to wake the MCU from stop and enter Active
Background Mode if the ENBDM bit is set. After the device enters background debug mode, all
background commands are available. The table below summarizes the behavior of the MCU in stop when
entry into the background debug mode is enabled.

10.6.5

LVD Enabled in Stop Mode

The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits in SPMSC1 when
the CPU executes a STOP instruction, then the voltage regulator remains active during Stop Mode. If the
user attempts to enter either Stop1 or Stop2 with the LVD enabled for stop (LVDSE = 1), the MCU will
instead enter Stop3. The table below summarizes the behavior of the MCU in stop when the LVD is
enabled.

Table 10-2. BDM Enabled Stop Mode Behavior

Mode

PDC

PPDC

CPU, Digital
Peripherals,

FLASH

RAM

ICG

ATD

Regulator

I/O Pins

RTI

Stop3

Don’t

care

Don’t

care

Standby

Standby

Active

Disabled

1

1

Either ATD Stop Mode or Power-Down Mode depending on the state of ATDPU.

Active

States held

Optionally on

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Summary of Contents for freescale semiconductor MC13211

Page 1: ...Document Number MC1321xRM Rev 1 6 05 2010 MC13211 212 213 ZigBee Compliant Platform 2 4 GHz Low Power Transceiver for the IEEE 802 15 4 Standard plus Microcontroller Reference Manual...

Page 2: ...particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including wit...

Page 3: ...5 5 ZigBee Compliant Network Stack 1 7 1 6 System Block Diagram 1 8 1 7 802 15 4 Modem Overview 1 9 1 7 1 Modem Block Diagram 1 9 1 7 2 Modem Data Transfer Modes 1 9 1 7 3 Modem Packet Structure 1 10...

Page 4: ...urations and External Connections 3 18 3 10 1 RF Interface Pins 3 18 3 10 2 Controlling RF Modes of Operation 3 21 3 10 3 RF Control Output CT_Bias 3 22 3 11 MC1321x Timer Resources 3 23 3 11 1 MCU TP...

Page 5: ...ransactions 4 15 4 9 1 SPI Singular Transaction Signalling 4 15 4 9 2 SPI Singular Transaction Protocol 4 16 4 10 Modem Symbol Data Format 4 17 4 11 Modem SPI Recursive Transactions 4 18 4 11 1 Recurs...

Page 6: ...rrent_Time_A Register 26 5 30 5 31 Current_Time_B Register 27 5 30 5 32 GPIO_Data_In Register 28 5 31 5 33 Chip_ID Register 2C 5 32 5 34 RX_Status Register 2D 5 32 5 35 Timestamp_A Register 2E 5 33 5...

Page 7: ...z PLL Out of Lock Interrupt 7 20 Chapter 8 Modem Interrupt Description 8 1 Modem Interrupts 8 1 8 1 1 Modem Interrupt Sources 8 1 8 1 2 Output Pin IRQ 8 3 8 2 PLL_lock_irq Status Bit and Operation 8 3...

Page 8: ...s 10 1 10 3 Run Mode 10 1 10 4 Active Background Mode 10 1 10 5 Wait Mode 10 2 10 6 Stop Modes 10 3 10 6 1 Stop1 Mode 10 3 10 6 2 Stop2 Mode 10 4 10 6 3 Stop3 Mode 10 4 10 6 4 Active BDM Enabled in St...

Page 9: ...2 7 1 Interrupt Pin Request Status and Control Register IRQSC 12 8 12 7 2 System Reset Status Register SRS 12 9 12 7 3 System Background Debug Force Reset Register SBDFR 12 11 12 7 4 System Options Re...

Page 10: ...3 External Clock Connections 14 4 14 2 4 External Crystal Resonator Connections 14 4 14 3 Functional Description 14 5 14 3 1 Off Mode Off 14 5 14 3 2 Self Clocked Mode SCM 14 5 14 3 3 FLL Engaged Inte...

Page 11: ...ng Mode IMM 15 5 15 4 4 Direct Addressing Mode DIR 15 5 15 4 5 Extended Addressing Mode EXT 15 5 15 4 6 Indexed Addressing Mode 15 5 15 5 Special Operations 15 6 15 5 1 Reset Sequence 15 7 15 5 2 Inte...

Page 12: ...us and Control Register TPM1CnSC 17 12 17 6 5 Timer x Channel Value Registers TPM1CnVH TPM1CnVL 17 14 Chapter 18 MCU Serial Communications Interface SCI 18 1 Features 18 1 18 2 SCI System Description...

Page 13: ...Frequency Divider Register IIC1F 19 4 19 4 5 IIC Control Register IIC1C 19 7 19 4 6 IIC Status Register IIC1S 19 8 19 4 7 IIC Data I O Register IIC1D 19 9 19 5 Functional Description 19 9 19 5 1 IIC P...

Page 14: ...ommunication Details 21 3 21 2 3 BDC Commands 21 5 21 2 4 Coding Structure Nomenclature 21 5 21 2 5 BDC Hardware Breakpoint 21 8 21 3 On Chip Debug System DBG 21 8 21 3 1 Comparators A and B 21 8 21 3...

Page 15: ...erations Describes system level considerations of the MC1321 modem and MCU Chapter 4 MC1321x Serial Peripheral Interface SPI Shows how the MC1321x modem and CPU communicate primarily through the onboa...

Page 16: ...BI Describes how the KBI module allows up to eight pins to act as additional interrupt sources Chapter 17 MCU Timer PWM TPM Module Details how the TPM uses one input output I O pin per channel and how...

Page 17: ...ction Device FFD C Full Function Device Coordinator FLI Frame Length Indicator GTS Guaranteed Time Slot HW Hardware IRQ Interrupt Request ISR Interrupt Service Routine LO Local Oscillator MAC Medium A...

Page 18: ...terface SSCS Service Specific Convergence Layer SW Software VCO Voltage Controlled Oscillator References The following sources were referenced to produce this book 1 IEEE 802 15 4 Standard 2 Freescale...

Page 19: ...f the HCS08 Family of Microcontroller Units MCU same die as MC9S08GBA and can provide up to 60KB of flash memory and 4KB of RAM The onboard MCU allows the communications stack and also the application...

Page 20: ...for proper performance of the radio the following modem registers must be over programmed Register 0x31 to 0xA0C0 Register 0x34 to 0xFEC6 These registers must be over programmed for MC1321x devices in...

Page 21: ...15 4 and ZigBee software 9mm x 9mm x 1mm 71 pin LGA Table 1 1 Devices in the MC1321x Family Device Operating Temp Range TA Package Memory Options Description MC13211 40 to 85 C LGA 1KB RAM 16KB Flash...

Page 22: ...oard interrupt KBI 8 channel 8 10 bit ADC Two independent serial communication interfaces SCI Multiple clock source options Internal clock generator ICG with 243 kHz oscillator that has 0 2 trimming r...

Page 23: ...ions Freescale provides a powerful software environment called the Freescale BeeKit Wireless Connectivity Toolkit BeeKit is a comprehensive codebase of wireless networking libraries application templa...

Page 24: ...ented mode transmission and reception automatically enabled in conditions of radio interference Robustness and ease of use Essential functionality to build and support a CE network The SynkroRF Networ...

Page 25: ...Layer the application support layer ASL facilitates information exchange between the Application Support Sub Layer APS and application objects Finally ZigBee Device Objects ZDO in addition to other ma...

Page 26: ...ansceiver Transmit Receive Switch Analog Receiver Analog Transmitter Frequency Generator Buffer RAM IRQArbiter RAMArbiter Power Management Voltage Regulators HCS08CPU FlashMemory RAM LowVoltage Interr...

Page 27: ...PAO_P PAO_M MOSI MISO SPICLK RXTXEN CE ATTN GPIO5 GPIO6 GPIO7 Receive Packet RAM Transmit Packet RAM 1 Transmit RAM Arbiter Receive RAM Arbiter PA VCO Crystal Oscillator Symbol Generation FCS Generati...

Page 28: ...and FLI are parsed and used to detect the payload data and FCS which are stored in RAMin Packet Mode A two byte FCS is calculated on the received data and compared to the FCS value appended to the tra...

Page 29: ...4 PHY spread and then up converted to the transmit frequency If the MC1321x is in Packet Mode data is processed as an entire packet The data is first loaded into the TX buffer The MCU then requests th...

Page 30: ...at is CT_bias is at VDDA voltage for transmit and is at ground for receive The internal T R switch enables the signal to an onboard LNA for receive and enables the onboard PAs for transmit Use of the...

Page 31: ...61 268 BYTES MAX MCU CORE 1 CHANNEL TIMER PWM MODULE TPM1 PTB7 AD1P7 PORT B PTE5 SPSCK PTE4 MOSI PTE6 PTE7 INTERFACE MODULE SCI2 MCU SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAG...

Page 32: ...normally a full function SPI bus with both master and slave capability and programmable clock interface Because the SPI is dedicated to the modem and internally tied to the modem SPI port the MCU SPI...

Page 33: ...known condition 1 8 4 MCU Internal Clock Distribution Some of the modules inside the MCU have clock source choices Figure 1 9 shows a simplified clock connection diagram Figure 1 9 MCU Internal Clock...

Page 34: ...tion The modem requires a 16MHz crystal for its source oscillator and can also supply a selectable frequency clock out CLKO The CLKO frequency can be programmed for 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 62 5...

Page 35: ...RXD2 PTC4 PTC2 SDA1 PTC3 SCL1 PTA3 KBI1P3 PTC5 PTC6 PTC7 PTE0 TXD1 PTE1 RXD1 VDDD VDDINT GPIO5 GPIO6 GPIO7 XTAL1 XTAL2 VDDLO2 VDDLO1 VDDVCO VBATT PTD2 TPM1CH2 CLKO VDD GPIO1 GPIO2 GPIO3 GPIO4 SM PAO_...

Page 36: ...t G Bit 0 Background Mode Select PTG0 is output only Pin is I O when used as BDM function 8 PTG1 XTAL Digital Input Output MCU Port G Bit 1 Crystal oscillator output Full I O when not used as clock so...

Page 37: ...this pin by using it as a 16 MHz source Measure 16 MHz output at CLKO programmed for 16 MHz 29 VDDLO2 Power Input Modem LO2 VDD supply Connect to VDDA externally 30 VDDLO1 Power Input Modem LO1 VDD su...

Page 38: ...em General Purpose Input Output 2 Internally connected pins When gpio_alt_en Register 9 Bit 7 1 GPIO2 functions as a CRC Valid indicator 44 GPIO1 Test Point MCU Port E Bit 7 Modem General Purpose Inpu...

Page 39: ...CU SPI master SPI clock output drives modem SPICLK slave clock input Normally factory test Do not connect 66 PTE4 MOSI1 MOSI MCU SPI master MOSI output drives modem slave MOSI input Normally factory t...

Page 40: ...MC1321x Pins and Connections MC1321x Reference Manual Rev 1 6 2 6 Freescale Semiconductor...

Page 41: ...em reset and monitoring of some real time status This chapter presents information addressing application and operation of the node from a system level The areas considered here are also covered in gr...

Page 42: ...ided both for bypassing and to supply VDDLO1 and VDDLO2 which are the power rails for the local oscillators Modem output VDDVCO is provided to allow separate bypass of the modem radio VCO regulated su...

Page 43: ...ing of the modem and SPI communication are all concerned with these signals Table 3 2 Internal Functional Interconnects Pin MCU Signal Modem Signal Description 43 PTE6 GPIO2 Modem GPIO2 output acts as...

Page 44: ...internal system the reset pin is driven low for approximately 34 cycles of fSelf_reset which is the approximate 8 MHz startup clock released and sampled again approximately 38 cycles of fSelf_reset l...

Page 45: ...CU the MCU can assume the modem is alive and ready for programming via the SPI bus Modem reset operation and control is detailed in Chapter 9 Modem Miscellaneous Functions 3 4 2 Modem Interrupt Reques...

Page 46: ...an also be used as a general purpose IO as long as there is no conflict with the MCU GPIO PTE7 GPIO2 CRC_Valid output drives PTE6 pin 43 The modem GPIO2 signal can optionally be programmed as an CRC v...

Page 47: ...about 18 pF C1 and C2 are typically values of 6 9 pF Higher values can load the crystal buffer and cause oscillator start up problems As described in Section 9 3 2 Crystal Trim Operation the MC1321x c...

Page 48: ...e a frequency as high as 40 MHz with no minimum frequency The external source must have compatible logic levels and drive input EXTAL Note that no external components are required for the clock oscill...

Page 49: ...ltage This internal reference can also be used with the MCU frequency locked loop FLL to generate higher system clock speeds without need for an external reference This source provides a low power low...

Page 50: ...to lock and then switch MCU clock to external source Additional considerations for this mode of operation include If the modem is forced to an Off condition such as a sleep mode there is a 25 msec wa...

Page 51: ...stal is justified when accurate power down time periods are required The external clock with the 32 768 kHz crystal allows an accurate 1 second time tick for RTI at very low power Although power is no...

Page 52: ...MCU GPIO1 Out_of_Idle output drives PTE7 pin 44 The modem GPIO1 signal can optionally be programmed as an out of idle indicator for monitoring RX TX or CCA operation GPIO2 CRC_Valid output drives PTE6...

Page 53: ...use these pins refer to the appropriate section from Table 3 4 Not all of the pins are available for external use Table 3 4 MC1321x Pin Sharing References Port Pins Alternate Function Reference1 PTA7...

Page 54: ...evice 3 8 2 Modem GPIO Characteristics The modem GPIO hardware consists of seven 7 signals total GPIO1 GPIO7 Immediately after reset all the GPIO pins are configured as high impedance general purpose...

Page 55: ...tion enabled Pull up forced on when IRQ enabled for falling edges pull down forced on when IRQ enabled for rising edges Internal connection PTA0 KBI1P0 I O N SWC SWC PTA1 KBI1P1 I O N SWC SWC PTA2 KBI...

Page 56: ...I1 I O N SWC SWC Internal connection PTE5 SPSCK1 I O N SWC SWC Internal connection PTE6 I O N SWC SWC Internal connection PTE7 I O N SWC SWC Internal connection PTF0 I O Y SWC SWC Not available in thi...

Page 57: ...TAL2 O N N N ATTN I N Internal connection RXTXEN I N Internal connection M_RST I N Internal connection CLKO O N SWC N SPICLK I N MOSI I N MISO O N SWC N Off state is SWC CE I N GPIO1 Out_of_Idle I O N...

Page 58: ...configurations including external LNA and PA for increased range CT_Bias Output The CT_Bias signal provides a switched bias reference for use with the internal T R switch and alternatively can be pro...

Page 59: ...nd receive with the optional CT_Bias pin providing a signal that indicates if the radio is in TX or RX Mode which then can be used to drive an external low noise amplifier or power amplifier In dual p...

Page 60: ...outputs and inductors L4 and L5 provide DC biasing to VDDA but are ac isolated CT_Bias is not required or used Figure 3 6 Dual Port RF Configuration Examples B alun B ypass RFIN_P P A O_P RFIN_M P A...

Page 61: ...ias pin in Single Port Mode is controlled by Bit 14 and operation of the radio ct_bias_en Bit 14 This bit is the enable for the CT_Bias output When Bit 14 0 default the CT_Bias is disabled and stays i...

Page 62: ...rol the sense of the output control i e CT_Bias can be active high or active low for TX and vice versa for RX Table 3 7 defines the CT_Bias output state depending on control bits and operation mode of...

Page 63: ...y Each TPM has an independent 16 bit counter with prescaler and modulo features to control frequency and range of a time reference The time base can be sourced from the bus clock fixed system clock or...

Page 64: ...from low power Doze Mode Latches timestamp value during packet reception With every received frame there is a timestamp generated and stored in a modem SPI register The timestamp is taken from the cou...

Page 65: ...n application parameters Over the air operation uses modes i e RX TX and CCA where power is highest As a result the time between radio operations should be kept at the longest possible period that the...

Page 66: ...There is no potential harm either to the transceiver or its operation the Doze current is simply higher To work around this issue there are three choices 1 Accept higher current in Doze mode 2 Do not...

Page 67: ...etes the transition to low power ATTN can be asserted any time except for the last CLKO clock cycle If ATTN does assert during this period the transition is ignored and the transceiver continues into...

Page 68: ...with the external clock use and external crystal or the modem CLKO and interrupts are serviced not treated as a reset i e the normal interrupt vector is used to generate an interrupt service routine...

Page 69: ...ate Doze Idle 300 1 CLKO s The Doze state can be released via a timer or asserting ATTN low The start up time is considerably less 300 1 CLKO s because the clock oscillator is already running CLKO can...

Page 70: ...Vdc and 80 s VDD 2 Vdc If the user wants the MCU to run from another clock source such as an external crystal with the FLL engaged then the initialization software running under the internal 4 MHz clo...

Page 71: ...e Mode while the MCU is in Stop3 then the CLKO is not available and the external reference cannot be enabled OSCSTEN 0 When starting up from Stop3 the MCU code must release the modem low power mode un...

Page 72: ...Quality Indication This is really a special case of RX so the CCA current is the same as RX There are two versions of CCA where one is called CCA and the second is called Energy Detect ED Figure 3 10...

Page 73: ...ion The return to Idle happens very quickly Figure 3 11 RX Timing Profile 3 12 6 1 3 Modem TX Timing profile The transmit or TX timing profile is more predictable than the RX profile Figure 3 12 shows...

Page 74: ...t Also some I O are interconnected between chips onboard the device see Section 3 4 Internal Functional Interconnects and System Reset and this affects their use during low power There are generally t...

Page 75: ...ansceiver should be programmed to drive low when SPI is disabled CE is high Other interconnected MCU pins PTD1 PTD3 PTE6 and PTE7 should be driven to low Transceiver GPIO2 GPIO7 should be programmed t...

Page 76: ...driven to a low condition early in the routine This is so the modem will start from a known condition and low power Profile the use scenario of both the modem and the MCU when they are active This is...

Page 77: ...l 4 1 SiP Level SPI Pin Connections The SiP level SPI pin connections are all internal to the device Figure 4 1 shows the SiP interconnections with the SPI bus highlighted Figure 4 1 MC1321x Internal...

Page 78: ...agram for the SPI Figure 4 2 shows the SPI modules of the MCU and modem in the master slave arrangement Figure 4 2 SPI System Block Diagram The MCU master initiates all SPI transfers During a transfer...

Page 79: ...and fast configuration of the MC1321x Partial word accesses are not supported All modem SPI accessible registers are configured with 16 bit data width The address range is 6 bits which allows for 64 l...

Page 80: ...iso_drv 1 0 GPIO_Data_Out Register 0C There are 4 levels of drive strength with field value 00 for lowest and value 11 for greatest The default value is 00 NOTE It is suggested the user program MISO f...

Page 81: ...mat the MCU SPI must be programmed for this clock mode i e clock phase control bit CPHA 0 and the clock polarity control bit CPOL 0 In addition the MSB first option must be selected Table 4 2 Modem SP...

Page 82: ...een MCU pins and the SPI module When the SPI is configured as a master the clock output is routed to the SPSCK1 pin the shifter output is routed to MOSI1 and the shifter input is routed from the MISO1...

Page 83: ...ter into the receive data buffer and SPRF is set to indicate the data can be read by reading SPI1D If another byte of data is waiting in the transmit buffer at the end of a transfer it is moved into t...

Page 84: ...veform applies to the MISO output from a slave The SS1 OUT waveform applies to the slave select output from the master provided MODFEN and SSOE 1 The master SS1 output goes to active low at the start...

Page 85: ...abled as a master and SPI pin control zero SPC0 is 0 not Bidirectional Mode this pin is the serial data input desired mode When the SPI is enabled as a slave and SPC0 0 this pin is the serial data out...

Page 86: ...rror is detected when a master s SS1 pin is low indicating that some other SPI device is trying to address this master as if it were a slave This could indicate a harmful output driver conflict so the...

Page 87: ...nsmit buffer empty SPTEF 0 Interrupts from SPTEF inhibited use polling 1 When SPTEF is 1 hardware interrupt requested 4 MSTR Master Slave Mode Select 0 SPI module configured as a slave SPI device 1 SP...

Page 88: ...ose I O not controlled by SPI 1 Mode fault function enabled master SS1 pin acts as the mode fault input or the slave select output 3 BIDIROE Bidirectional Mode Output Enable When Bidirectional Mode is...

Page 89: ...s for the SPI baud rate prescaler as shown in Table 4 7 The input to this prescaler is the bus rate clock BUSCLK The output of this prescaler drives the input of the SPI baud rate divider see Figure 4...

Page 90: ...SPTEF CPU interrupt request if the SPTIE bit in the SPI1C1 is also set SPTEF is automatically set when a data byte transfers from the transmit buffer into the transmit shift register For an idle SPI...

Page 91: ...transactions are used to access the modem SPI registers for reading and writing of data To view the modem SPI register map and descriptions of the modem registers reference Chapter 5 Modem SPI Registe...

Page 92: ...gister address as shown in Figure 4 14 Figure 4 14 SPI Header and Payload Definition The R W bit identifies the transfer as a read R W 1 or write R W 0 The lower 6 bits in the header determines which...

Page 93: ...t directly to the SPI buffer When the symbols are read via the SPI bus 2 SPI bursts per 16 bit word are required and the MSB is presented first such that the symbols appear to the MCU in reverse order...

Page 94: ...address This sequence repeats as long as the CE is held asserted allowing multiple sequential register contents of the SPI to be read starting at the header address As the recursive read progresses t...

Page 95: ...ss The receive Packet RAM is normally accessed when the modem is in Packet Data Mode and a valid frame has been received as indicated by rx_rcvd_irq and crc_valid The number of receive data bytes in t...

Page 96: ...mask bit ram_addr_mask IRQ_Mask Register 5 Bit 12 As with other interrupt requests the status is cleared by reading the IRQ_Status register 2 RAM arbitration busy if the transceiver internal logic att...

Page 97: ...to an even number and an extra dummy byte will be written 3 Do a recursive SPI write transaction where a MCU asserts CE low b MCU sends the MC1321x the first SPI burst with header field of R W bit 0 a...

Page 98: ...figuring MCU Registers for Proper SPI Operation The MCU SPI module must be configured for proper operation to meet the modem SPI transaction format The following conditions must be met MCU is master M...

Page 99: ...et SPI byte transactions For more on control of port E see Section 13 3 5 Port E SCI1 and SPI 4 13 2 SPI Baud Rate Control The software supporting 802 15 4 Standard applications or ZigBee applications...

Page 100: ...MC1321x Serial Peripheral Interface SPI MC1321x Reference Manual Rev 1 6 4 24 Freescale Semiconductor...

Page 101: ...for any single register access is always 16 bits in length This chapter describes all the registers that users should access in the MC1321x Undocumented addresses should not be accessed NOTE Register...

Page 102: ..._Pkt_RAM 02 tx_pkt_ram 15 0 TX_Pkt_Ctl 03 tx_ram2_select tx_pkt_length 6 0 CCA_Thresh 04 cca_vt 7 0 power_comp 7 0 IRQ_Mask 05 attn_mask ram_addr_mask arb_busy_mask strm_data_mask pll_lock_mask acoma_...

Page 103: ...io4_o gpio3_o gpio2_o gpio1_o LO1_Int_Div 0F lo1_idiv 7 0 LO1_Num 10 lo1_num 15 0 PA_Lvl 12 pa_lvl_coarse 1 0 pa_lvl_fine 1 0 pa_drv_coarse 1 0 pa_drv_fine 1 0 Tmr_Cmp1_A 1B tmr_cmp1_dis tmr_cmp1 23 1...

Page 104: ...ca crc_valid RST_Ind 25 reset_ind Current_Time_A 26 et 23 16 Current_Time_B 27 et 15 0 GPIO_Data_In 28 gpio7_i gpio6_i gpio5_i gpio4_i gpio3_i gpio2_i gpio1_i Chip_Id 2C chip_id 8 0 RX_Status 2D cca_f...

Page 105: ...RAM Register 01 is required to access the RX packet payload data In Stream Mode the receive payload data is accessed word by word via repeated read accesses on the SPI bus During Stream Mode when a va...

Page 106: ...02 on a word by word basis via repeated accesses on the SPI bus During Stream Mode when a data word is required for TX_Pkt_RAM a tx_strm_irq status is set and an interrupt is generated it must be ena...

Page 107: ...can compensate the cca_final 7 0 value for external gain in the RX path See Section 7 3 5 Clear Channel Assessment CCA Modes including Link Quality Indication for more detailed information NOTE The de...

Page 108: ...measured value of the CCA operation The result is stored in cca_final 7 0 Default is 0x8D Register 05 0x05 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 attn_mask ram_addr_mask arb_busy_mask strm_data_ma...

Page 109: ...t savings 0 Normal operation Doze is exited by TC2 match or ATTN assertion Bit 4 doze_mask The Doze timer interrupt mask bit controls the doze_irq interrupt on the IRQ pin 1 Allows doze_irq to generat...

Page 110: ...a from transceiver via SPI bus and IRQ on word by word basis 0 RX Packet Mode with data preloaded in RX RAM Bit 10 cca_mask The CCA interrupt mask bit controls the cca_irq interrupt on the IRQ pin 1 A...

Page 111: ...ode hib_en doze_en TYPE r w r w r w r w r w r w r w r w r w r w r w RESET 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0x0C00 Table 5 9 Register 07 Description Name Description Operation Bits 14 12 10 8 4 2 Reserv...

Page 112: ...The CLKO pin stops toggling 128 xtal or reference cycles after the doze_en bit is programmed to 1 Note In Doze Mode only CLKO frequencies of 1 0 MHz or less are available Bit 7 tx_done_mask The Strea...

Page 113: ...lowest power operating mode without a running time base 0 Normal operation Bit 0 doze_en The doze enable bit can set the MC1321x into its lowest power saving mode with a running time base 1 Places the...

Page 114: ...The GPIO alternative MCU interface enable bit controls GPIO1 and GPIO2 1 GPIO1 and GPIO2 are used as status to the MCU GPIO1 indicates when the MC1321x is out of idle GPIO2 indicates a valid CRC or CC...

Page 115: ...its 2 0 Table 5 12 lists each setting and its respective frequency Table 5 12 CLKO Frequency clko_rate CLKO 000 16 MHz 001 8 MHz 010 4 MHz 011 2 MHz 100 1 MHz 101 62 5 kHz 110 default 32 786 kHz 16 MH...

Page 116: ...able 5 14 Register 0B Description Name Description Operation Bits 15 14 gpio1234_drv 1 0 These bits select output drive strength for GPIO1 through GPIO4 00 default lowest drive strength 11 highest dri...

Page 117: ...t configures GPIO1 as an input 1 GPIO1 enabled as input 0 GPIO1 disabled as input Register 0C 0x0C BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpio567_drv 1 0 miso_drv 1 0 clko_drv 1 0 irqb_drv 1 0 irqb...

Page 118: ...t value 1 GPIO5 driven high 0 GPIO5 driven low Bit 3 gpio4_o GPIO4 output value 1 GPIO4 driven high 0 GPIO4 driven low Bit 2 gpio3_o GPIO3 output value 1 GPIO3 driven high 0 GPIO3 driven low Bit 1 gpi...

Page 119: ...onal N synthesizer Default is 20 480dec 0x5000 See Table 5 18 Table 5 18 Channel Operation1 1 See Section 7 4 Frequency of Operation for frequency programming equations 802 15 4 Channel Number Frequen...

Page 120: ...ster in parallel and as a result the load is caused by a write Register 1C Writing of Registers 1B and 1C can be done as a recursive SPI register write transaction or two separate singular transaction...

Page 121: ...0 Register 1B Description Name Description Operation Bits 14 8 Reserved Leave default Bit 15 tmr_cmp1_dis This bit disables the Event Timer Comparator 1 function 1 Disables the Event Timer Compare 1 f...

Page 122: ...rator register in parallel and as a result the load is caused by a write Register 1E Writing of Registers 1D and 1E can be done as a recursive SPI register write transaction or two separate singular t...

Page 123: ...egister 1F will not be loaded in the comparator and the affect of the timer disable bit will not active until Register 20 is written The 24 bit comparator value must be loaded into the comparator regi...

Page 124: ...comparator value must be loaded into the comparator register in parallel and as a result the load is caused by a write Register 22 Writing of Registers 21 and 22 can be done as a recursive SPI regist...

Page 125: ...ister 21 Description Name Description Operation Bits 14 8 Reserved Leave default Bit 15 tmr_cmp4_dis This bit disables the Event Timer Comparator 4 interrupt and status bit 1 Disables Event Timer Comp...

Page 126: ...IRQ Note use of interrupt status Bit 14 Bit 13 Bit 7 and Bit 6 which are multiplexed and have special functionality Register 23 0x23 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc2_prime 15 0 TYPE r w R...

Page 127: ...trm_mode Register 7 Bit 5 1 Register 24 Bit 14 represents tx_done_irq tx_done_irq definition TX Stream Mode reception complete and transceiver has returned to Idle Bit 13 arb_busy_err or rx_done_irq T...

Page 128: ...m_irq rx_strm_irq definition 1 First occurrence RX Packet Length is available to be read 2 Subsequent occurrences next receive Stream data word is ready to be read Bit 6 tx_ sent_irq or tx_strm_irq Th...

Page 129: ...Register 6 Bits 5 4 10 Energy Detect Mode CCA is not calculated and cca is held low Bit 0 crc_valid The RX CRC Result bit denotes if the CRC is correct or not 1 RX CRC correct 0 RX CRC incorrect defa...

Page 130: ...Event Timer Register 26 0x26 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 et 23 16 TYPE r RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 5 31 Register 26 Description Name Description Operation Bits...

Page 131: ...of GPIO6 With gpio6_oen 0 and gpio6_ien 1 GPIO6 is configured as an input whose value can be read from gpio6_i Bit 12 gpio5_i This bit is the input value of GPIO5 With gpio5_oen 0 and gpio5_ien 1 GPI...

Page 132: ...of the CCA algorithm selected by cca_type 1 0 Register 6 Bits 5 4 The second field gives the receive packet length parsed from the packet header the value is latched after an RX Start Frame Delimiter...

Page 133: ...0x0000 Table 5 35 Register 2D Description Name Description Operation Bit 7 Reserved Bits 15 8 cca_final 7 0 Average CCA energy These bits represent the average result of the CCA algorithm selected by...

Page 134: ...abled Register 2F 0x2F BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 timestamp 15 0 TYPE r RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 5 37 Register 2F Description Name Description Operation Bits 1...

Page 135: ...can be observed see application note AN2976 Default is normal modulated operation NOTE The PSM_Mode Register 31 must be over written for proper transceiver operation for devices that read Chip_ID Regi...

Page 136: ...r 34 must be over written for proper transceiver operation for devices that read Chip_ID Register 2C as 0x6800 See Section 5 33 Chip_ID Register 2C Over write value is 0xFEC6 Register 34 0x34 BIT 15 1...

Page 137: ...ned values set in registers via SPI write operations The current time is accessible at any time via a SPI read operation as well as programmable via a SPI write operation The Event Timer provides the...

Page 138: ...clock rate and rolls over to zero after reaching its maximum value Programming current time is accomplished by using three SPI registers 1 Tmr_Cmp1_A Register 1B Bits 7 0 tmr_cmp1 23 16 2 Tmr_Cmp1_B R...

Page 139: ...r corresponds to the beginning of a receive packet where the actual payload data begins after the FLI has been received The timestamp 23 0 Register 2E Bits 7 0 and Register 2F bits 15 0 value is read...

Page 140: ...r 24 Bit 8 2 tmr2_irq IRQ_Status Register 24 Bit 2 3 tmr3_irq IRQ_Status Register 24 Bit 4 4 tmr4_irq IRQ_Status Register 24 Bit 3 The status bit remains set until a read access of the IRQ_Status regi...

Page 141: ...tions exit reset with the timer function enabled but with the interrupts masked off Users should disable all timers and clear the IRQ_Status Register via a read as part of system initialization after...

Page 142: ...is as follows 1 Read the current time value from et 23 0 2 Add an offset to this value to equal desired future time to exit Doze Mode 3 Program field tmr_cmp2 23 0 to value future time 4 Program doze...

Page 143: ...nly load tx_pkt_length 6 0 and payload data into tx_pkt_RAM 15 0 10 Program tmr_trig_en Control_A Register 6 Bit 7 high to enable a timer based operation 11 Program the MC1321x 193 for the desired tra...

Page 144: ...ig_en Control_A Register 6 Bit 7 high to enable a timer based operation 11 Program use_strm_mode bit high for Stream Data Mode 12 Program either rx_strm or tx_strm for desired operation 13 Assert the...

Page 145: ...can also be modified as timer based sequences using Tmr_Cmp2 Figure 7 1 and Figure 7 2 show state diagrams for Packet Mode transceiver operations without and with timer initiated sequences If Stream...

Page 146: ...quences Figure 7 1 State Diagram for Packet Mode Without Timer Enabled States Figure 7 2 State Diagram for Packet Mode With Tmr_Cmp2 Enabled States tmr_trig_en 1 and xcvr_seq 0x2 set doze_en OFF HIBER...

Page 147: ...r_cmp2 et set hib_en RXTXEN 1 and tmr_cmp2 et 23 0 and xcvr_seq 0x1 tx_sent_irq cca_irq rx_strm_irq rx_done_irq and tx_strm 1 and use_strm_mode 1 RXTXEN 1 and rx_strm 1 and use_strm_mode 1 RXTXEN 1 an...

Page 148: ...CLKO cycles after hib_en is set The normal way to exit from Hibernate Mode is to assert ATTN which will cause the MC1321x to go to Idle Mode The MC1321x then moves to Idle Mode within 20 milliseconds...

Page 149: ...mer wake up is the Acoma state that has the advantage of lowest power with data retention while allowing CLKO to run This mode disables the Event Timer and prescaler but allows the clock to run and ha...

Page 150: ...initiated Writing to the xcvr_seq 1 0 field arms the transition to the desired mode use_strm_mode 0 tx_strm 0 and rx_strm 0 However the RXTXEN signal must also be high for the transition to occur and...

Page 151: ...us reported by crc_valid IRQ_Status Register 24 Bit 0 3 Payload data length reported by rx_pkt_latch 6 0 RX_Pkt_Latch Register 2D Bits 6 0 4 Link quality indicator LQI this is a measure of the receive...

Page 152: ...rmines a valid length for the frame by reading rx_pkt_latch 6 0 b Reads the payload data from RX Packet RAM using a recursive read from rx_pkt_ram 15 0 RX_Pkt_RAM Register 01 7 3 3 2 Aborting a Packet...

Page 153: ...ver the RXTXEN signal must also be high for the transition to occur and if the Event Timer is enabled the transition will be synchronized to the TC2_Prime compare event Once Receive or Transmit is ent...

Page 154: ...ng the data from RX_Pkt_RAM Register 01 The data must be read within the 64 microsecond period and no interrupt will be generated for the received CRC data An interrupt will also be generated for the...

Page 155: ...programmed to 1 to enable the stream RX sequence 8 RXTXEN must be asserted and held high 9 The receiver will await preamble followed by a SFD After receiving these the next byte is the FLI and gets s...

Page 156: ...rrupt if enabled Because of the Streaming Data Mode it is possible for a strm_data_err status interrupt to occur up to 64 sec after the transceiver returns to Idle Driver software must deal with this...

Page 157: ...iting the TX data to tx_pkt_ram 15 0 TX_Pkt_RAM Register 02 NOTE Steps 11 and 12 get repeated as required for the payload data A word must be transferred within 64 s to keep the packet contiguous No d...

Page 158: ...7 For CCA Mode it is preferred that tx_strm rx_strm and use_strm_mode control bits should be cleared to zero 7 3 5 1 Clear Channel Assessment Function use_strm is zero The CCA function measures the av...

Page 159: ...into power_comp 7 0 for best accuracy Since the AGC is set to a fixed gain during the CCA procedure input signals above 65 dBm will not be reflected correctly due to saturation This is not a problem...

Page 160: ...er 24 Bit 1 is set to 1 when a busy channel is detected c cca_irq IRQ_Status Register 24 Bit 5 is set to 1 to indicate complete status Also an interrupt is generated due to the valid status 9 In respo...

Page 161: ...CCA operation is complete 4 cca_type 1 0 Control_A Register 06 Bits 5 4 is programmed to 10 to select the ED algorithm 5 Transceiver sequence is programmed to xcvr_seq 1 0 0x1 for CCA Mode 6 RXTXEN mu...

Page 162: ...ed 802 15 4 Standard accuracy and range limits are shown A 3 5 dBm offset has been programmed into the LQI reporting level to center the level over temperature Typical values of LQI returned from an R...

Page 163: ...n be controlled via programming of the PA_Lvl Register 12 7 0 whose fields include pa_lvl_course 1 0 pa_lvl_fine 1 0 pa_dr_coarse 1 0 and pa_dr_fine 1 0 The programmable range of differential power is...

Page 164: ...5 Bit 9 is set NOTE Freescale recommends that software enable the pll_lock_mask during CCA RX and TX operations The pll_lock_irq status bit is set by an out of lock condition and MUST be cleared by an...

Page 165: ...ld be troublesome is in Packet Mode RX or a CCA operation If the RX or CCA is aborted due to an out of lock condition no rx_done_irq status or cca_irq status is set and a corresponding IRQ signal is n...

Page 166: ...Modem Modes of Operation MC1321x Reference Manual Rev 1 6 7 22 Freescale Semiconductor...

Page 167: ...urred the MCU must use the IRQ_Status register contents to determine all the present events that caused an interrupt prioritize them and respond to all of the them This is done through the interrupt s...

Page 168: ...has reached a Power up complete condition after a reset Read IRQ_Status Reg 6 doze_irq doze_mask While in Doze Mode a tmr_cmp2 match has occurred and the MC1321x will return to Idle Mode Read IRQ_Sta...

Page 169: ...Bit and Operation As described in Section 5 28 IRQ_Status Register 24 pll_lock_irq status bit indicates the LO1 PLL has come out of lock during a TX RX or CCA ED transceiver operation If the LO1 unlo...

Page 170: ...has achieved Idle status full power up after the release of the RST signal The default condition out of reset leaves the attn_irq interrupt request enabled and upon the transceiver reaching Idle the...

Page 171: ...ze to be exited even if the timer option is enabled If an interrupt is desired set attn_mask before entering Doze which will cause the interrupt when the attn_irq status is set upon exiting Doze due t...

Page 172: ...Modem Interrupt Description MC1321x Reference Manual Rev 1 6 8 6 Freescale Semiconductor...

Page 173: ...is released when CE is negated high 9 1 3 Reset Indicator Bit RST_Ind Register 25 Bit 7 It is useful to determine if the transceiver has powered up from a reset condition or from a low power state th...

Page 174: ...n are cleared NOTE If any bit is programmed to be an input and output simultaneously the input condition overrides 9 2 2 Setting GPIO Output Drive Strength If any GPIO are programmed as outputs their...

Page 175: ...om high to low latches the CCA result on GPIO2 and that status will not change until the next transceiver sequence GPIO2 will not be valid if an error condition such as a PLL out of lock condition occ...

Page 176: ...he 16 MHz crystal oscillator with warp capability as the reference oscillator for the system The warp capability is done by the MC1321x and is controlled by programming CLKO_Ctl Register 0A Bits 15 8...

Page 177: ...control fields 9 4 1 Enable CLKO clko_en Control_C Register 09 Bit 5 Setting clko_en Contro_C Register 9 Bit 5 to 1 enables the CLKO signal The default condition out of reset is that the clock out is...

Page 178: ...10 The CLKO output drive strength can be programmed to 4 different levels by writing to clko_drv 1 0 GPIO_Data_Out Register 0C Bits 11 10 The default value is the lowest drive value of 00 Note that f...

Page 179: ...p3 All internal circuits powered for fast recovery 10 3 Run Mode This is the normal operating mode for the HCS08 This mode is selected when the BKGD MS pin is high at the rising edge of reset In this...

Page 180: ...s operated in run mode for the first time When the HCS08 is shipped from the Freescale Semiconductor factory the FLASH program memory is erased by default unless specifically noted so there is no prog...

Page 181: ...not set When the MCU is in Stop1 Mode all internal circuits that are powered from the voltage regulator are turned off The voltage regulator is in a low power standby state as is the ATD Exit from Sto...

Page 182: ...must be initialized After waking up from Stop2 the PPDF bit in SPMSC2 is set This flag may be used to direct user code to go to a Stop2 recovery routine PPDF remains set and the I O pin states remain...

Page 183: ...ttempts to enter either Stop1 or Stop2 with ENBDM set the MCU will instead enter Stop3 Most background commands are not available in Stop Mode The memory access with status commands do not allow memor...

Page 184: ...Stop2 All registers will be reset upon wake up from Stop1 and the contents of RAM are not preserved The MCU must be initialized as upon reset The contents of the FLASH memory are non volatile and are...

Page 185: ...ules will be reset upon wake up from stop and must be re initialized SPI When the MCU enters Stop Mode the clocks to the SPI module stop The module halts operation If the MCU is configured to go into...

Page 186: ...MCU Modes of Operation MC1321x Reference Manual Rev 1 6 10 8 Freescale Semiconductor...

Page 187: ...le registers FFB0 through FFBF Figure 11 1 MC1321X Memory Maps DIRECT PAGE REGISTERS RAM FLASH HIGH PAGE REGISTERS FLASH 4096 BYTES 1920 BYTES 59348 BYTES 0000 007F 0080 107F 1800 17FF 182B 182C FFFF...

Page 188: ...11 1 Reset and Interrupt Vectors Address High Low Vector Vector Name 0xFFC0 FFC1 0xFFCA FFCB Unused Vector Space available for user program 0xFFCC FFCD RTI Vrti 0xFFCE FFCF IIC Viic1 0xFFD0 FFD1 ATD C...

Page 189: ...ed and programmed like other FLASH memory locations Direct page registers can be accessed with efficient direct addressing mode instructions Bit manipulation instructions can be used to access any bit...

Page 190: ...DSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 0x000F PTDDD PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0 0x0010 PTED PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0 0x0011 PTEPE PTEP...

Page 191: ...Bit 7 6 5 4 3 2 1 Bit 0 0x003B TPM1C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0 0x003C TPM1C2VH Bit 15 14 13 12 11 10 9 Bit 8 0x003D TPM1C2VL Bit 7 6 5 4 3 2 1 Bit 0 0x003E 0x003F Reserved 0x0040 PTFD PT...

Page 192: ...4 13 12 11 10 9 Bit 8 0x0062 TPM2CNTL Bit 7 6 5 4 3 2 1 Bit 0 0x0063 TPM2MODH Bit 15 14 13 12 11 10 9 Bit 8 0x0064 TPM2MODL Bit 7 6 5 4 3 2 1 Bit 0 0x0065 TPM2C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0...

Page 193: ...ID9 ID8 0x1807 SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0x1808 SRTISC RTIF RTIACK RTICLKS RTIE 0 RTIS2 RTIS1 RTIS0 0x1809 SPMSC1 LVDF LVDACK LVDIE LVDRE LVDSE LVDE 0 0 0x180A SPMSC2 LVWF LVWACK LVDV LVWV...

Page 194: ...low power wait Stop2 or Stop3 Mode At power on or after wake up from Stop1 the contents of RAM are uninitialized RAM data is unaffected by any reset provided that the supply voltage does not drop belo...

Page 195: ...r fast program and erase operation Up to 100 000 program erase cycles at typical voltage and temperature Flexible block protection Security feature for FLASH and RAM Auto power down for low frequency...

Page 196: ...already programmed is not allowed without first erasing the page in which the byte resides or mass erasing the entire FLASH memory Programming without first erasing may disturb data stored in the FLA...

Page 197: ...pon completion of the command the charge pump is turned off When a burst program command is issued the charge pump is enabled and then remains enabled after completion of the burst program operation i...

Page 198: ...he high voltage to the array must be disabled and then enabled again If a new burst command has not been queued before the current command completes then the charge pump will be disabled and high volt...

Page 199: ...mands when the MCU is secure Writing 0 to FCBEF to cancel a partial command 11 4 6 FLASH Block Protection Block protection prevents program or erase changes for FLASH memory locations in a designated...

Page 200: ...e memory have normal access to any MCU memory locations and resources Attempts to access a secure memory location with a program executing from an unsecured memory space or through the background debu...

Page 201: ...user application programs so if the vector space is block protected the backdoor security key mechanism cannot permanently change the block protect security settings or the backdoor key Security can...

Page 202: ...the bus rate clock 1 Clock input to the FLASH clock divider is the bus rate clock divided by 8 5 DIV 5 0 Divisor for FLASH Clock Divider The FLASH clock divider divides the bus rate clock or the bus...

Page 203: ...ssible only from user secured firmware BDM commands cannot be used to write key comparison values that would unlock the backdoor key For more detailed information about the backdoor key mechanism refe...

Page 204: ...Unimplemented or Reserved Figure 11 6 FLASH Configuration Register FCNFG Table 11 9 FCNFG Field Descriptions Field Description 5 KEYACC Enable Writing of Access Key This bit enables writing of the bac...

Page 205: ...rmines the size of a protected block of FLASH locations at the high address end of the FLASH see Table 11 11 Protected FLASH locations cannot be erased or programmed Table 11 11 High Address Protected...

Page 206: ...register a command that attempts to erase or program a location in a protected block the erroneous command is ignored FPVIOL is cleared by writing a 1 to FPVIOL 0 No protection violation 1 An attempt...

Page 207: ...on Only blank check is required as part of the security unlocking mechanism Table 11 13 FCMD Field Descriptions Field Description 7 0 FCMD 7 0 See Table 11 14 for a description of FCMD 7 0 Table 11 14...

Page 208: ...MCU Memory MC1321x Reference Manual Rev 1 6 11 22 Freescale Semiconductor...

Page 209: ...interrupt features include Multiple sources of reset for flexible system configuration and reliable operation Power on detection POR Low voltage detection LVD with enable External RESET pin with enabl...

Page 210: ...be pulled up by the internal pullup resistor unless it is held low externally After the pin is released it is sampled after another 38 cycles to determine whether the reset pin is the cause of the MC...

Page 211: ...the current instruction before responding to the interrupt The interrupt sequence follows the same cycle by cycle sequence as the SWI instruction and consists of Saving the CPU registers on the stack...

Page 212: ...he stack in reverse order As part of the RTI sequence the CPU fills the instruction pipeline by reading three bytes of program information starting from the PC address just recovered from the stack Th...

Page 213: ...sured on the pulled up IRQ pin may be as low as VDD 0 7 V The internal gates connected to this pin are pulled all the way to VDD All other pins with enabled pullup resistors will have an unloaded meas...

Page 214: ...SPIE SPTIE SPI 14 FFE2 FFE3 Vtpm2ovf TPM2 TOF TOIE TPM2 overflow 13 FFE4 FFE5 Vtpm2ch4 TPM2 CH4F CH4IE TPM2 channel 4 12 FFE6 FFE7 Vtpm2ch3 TPM2 CH3F CH3IE TPM2 channel 3 11 FFE8 FFE9 Vtpm2ch2 TPM2 CH...

Page 215: ...upt associated with it There are two user selectable trip voltages for the LVW one high VLVWH and one low VLVWL The trip voltage is selected by LVWV in SPMSC2 12 7 Real Time Interrupt RTI The real tim...

Page 216: ...on report status and acknowledge IRQ events Figure 12 2 Interrupt Request Status and Control Register IRQSC IRQEDG Interrupt Request IRQ Edge Select This read write control bit is used to select the p...

Page 217: ...12 7 2 System Reset Status Register SRS This register includes six read only status flags to indicate the source of the most recent reset When a debug host forces reset by writing 1 to BDFR in the SBD...

Page 218: ...al opcode 0 Reset not caused by an illegal opcode ICG ILAD Illegal Address Access Reset was caused by an attempt to access a designated illegal address 1 Reset caused by an illegal address access 0 Re...

Page 219: ...any time Bits 3 and 2 are unimplemented and always read 0 This is a write once register so only the first write after reset is honored Any subsequent attempt to write to SOPT intentionally or unintent...

Page 220: ...scillator start up does not apply in HCS08 0 Short stop recovery assumes oscillator is running as MCU recovers from stop BKGDPE Background Debug Mode Pin Enable The BKGDPE bit enables the PTG0 BKGD MS...

Page 221: ...Real Time Interrupt Flag This read only status bit indicates the periodic wakeup timer has timed out 1 Periodic wakeup timer timed out 0 Periodic wakeup timer not timed out RTIACK Real Time Interrupt...

Page 222: ...read only status bit indicates a low voltage detect event LVDACK Low Voltage Detect Acknowledge This write only bit is used to acknowledge low voltage detection errors write 1 to clear LVDF Reads alw...

Page 223: ...ng Stop Mode 0 Low voltage detect disabled during Stop Mode LVDE Low Voltage Detect Enable This read write bit enables low voltage detect logic and qualifies the operation of other bits in this regist...

Page 224: ...d VLVD VLVDL LVWV Low Voltage Warning Voltage Select The LVWV bit selects the LVW trip point voltage VLVW 1 High trip point selected VLVW VLVWH 0 Low trip point selected VLVW VLVWL PPDF Partial Power...

Page 225: ...tems external interrupts or keyboard interrupts When these other modules are not controlling the port pins they revert to general purpose I O control For each I O pin a port data bit provides access t...

Page 226: ...does not have a clamp diode to VDD IRQ should not be driven above VDD 4 Pin contains integrated pullup device 5 High current drive 6 Pins PTA 7 4 contain both pullup and pulldown devices Pulldown avai...

Page 227: ...l of these pins are available for general purpose I O when they are not used by other on chip peripheral systems After reset BKGD MS is enabled and therefore is not usable as an output pin until BKGDP...

Page 228: ...re 13 4 Port C Pin Names Port C is an 8 bit port which is shared among the SCI2 and IIC1 modules and general purpose I O When SCI2 or IIC1 modules are enabled the pin direction will be controlled by t...

Page 229: ...ort E SCI1 and SPI Figure 13 6 Port E Pin Names Port E is an 8 bit port shared with the SCI1 module SPI1 module and general purpose I O When the SCI or SPI modules are enabled the pin direction will b...

Page 230: ...ed by the port G data PTGD data direction PTGDD pullup enable PTGPE and slew rate control PTGSE registers Refer to Section 13 4 Parallel I O Controls for more information about general purpose I O con...

Page 231: ...egister When a peripheral module or system function is in control of a port pin the data direction control still controls what is returned for reads of the port data register even though the periphera...

Page 232: ...hese values can be stored in RAM before entering Stop2 because the RAM is maintained during Stop2 In Stop3 Mode all I O is maintained because internal logic circuitry stays powered up Upon recovery no...

Page 233: ...A pins that are inputs these read write control bits determine whether internal pullup devices are enabled provided the corresponding PTADDn is 0 For port A pins that are configured as outputs these b...

Page 234: ...PTBPE PTBSE and PTBDD Port B includes eight general purpose I O pins that share with the ATD function Port B pins used as general purpose I O pins are controlled by the port B data PTBD data direction...

Page 235: ...re configured as inputs these bits are ignored 1 Slew rate control enabled 0 Slew rate control disabled PTBDDn Data Direction for Port B Bit n n 0 7 These read write bits control the direction of port...

Page 236: ...control bits determine whether internal pullup devices are enabled For port C pins that are configured as outputs these bits are ignored and the internal pullup devices are disabled 1 Internal pullup...

Page 237: ...put compare mode the corresponding PTDSE can be used to provide slew rate on the pin When the TPM is in input capture mode the corresponding PTDPE can be used provided the corresponding PTDDD bit is 0...

Page 238: ...se read write bits control the direction of port D pins and what is read for PTDD reads 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn 0 Input output driver disab...

Page 239: ...control bits determine whether internal pullup devices are enabled For port E pins that are configured as outputs these bits are ignored and the internal pullup devices are disabled 1 Internal pullup...

Page 240: ...TF Data Register Bit n n 0 7 For port F pins that are inputs reads return the logic level on the pin For port F pins that are configured as outputs reads return the last value written to this register...

Page 241: ...s and what is read for PTFD reads 1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn 0 Input output driver disabled and reads return the pin value 13 6 7 Port G Regis...

Page 242: ...all port pins as high impedance inputs with pullups disabled PTGPEn Pullup Enable for Port G Bit n n 0 7 For port G pins that are inputs these read write control bits determine whether internal pullup...

Page 243: ...controlled outputs are enabled For port G pins that are configured as inputs these bits are ignored 1 Slew rate control enabled 0 Slew rate control disabled PTGDDn Data Direction for Port G Bit n n 0...

Page 244: ...MCU Parallel Input Output MC1321x Reference Manual Rev 1 6 13 20 Freescale Semiconductor...

Page 245: ...nal sources can provide a very precise clock source The oscillator is capable of being configured for low power mode or high amplitude mode as selected by HGO Internal reference generator The internal...

Page 246: ...igure the module go to Section 14 4 Initialization Application Information and pick an example that best suits the application needs 14 1 1 Features Features of the ICG and clock distribution system S...

Page 247: ...e which occurs when the FLL detects that the DCO is locked to a multiple of the internal reference Mode 4 FLL Bypassed External FBE In this mode the ICG is configured to bypass the FLL and use an exte...

Page 248: ...f being configured to provide a higher amplitude output for improved noise immunity This Mode of operation is selected by HGO 1 14 2 3 External Clock Connections If an external clock is used then the...

Page 249: ...d to the rest of the MCU is turned off This option is provided to avoid long oscillator start up times if necessary or to run the RTI from the oscillator during Stop3 14 3 1 3 Stop Off Mode Recovery U...

Page 250: ...the previous frequency but ICGOUT will double if the FLL was unlocked If this mode is entered from Off Mode fICGDCLK will be equal to the frequency of ICGDCLK before entering Off Mode If CLKS bits ar...

Page 251: ...FLL Engaged Internal Locked FLL engaged internal locked is entered from FEI unlocked when the count error n which comes from the subtractor is less than nlock max and greater than nlock min for a giv...

Page 252: ...t according to their operational descriptions later in this section Upon entering this state and until the FLL becomes locked the output clock signal ICGOUT frequency is given by fICGDCLK 2 R This ext...

Page 253: ...clock s are being monitored if either one falls below a certain frequency fLOR and fLOD respectively the LOCS status bit will be set to indicate the error LOCS will remain set until it is cleared by...

Page 254: ...E CLKST 10 10 0 Forced High No No 10 1 Real Time Yes No FEE CLKST 11 11 X Real Time Yes Yes 1 If ENABLE is high waiting for external crystal start up after exiting stop 2 DCO clock will not be monitor...

Page 255: ...EFS 1 in the ICGC1 register When HGO 0 the standard low power oscillator is selected If the high gain option is to be switched after the initial write to the ICGC1 register then the ICG should first b...

Page 256: ...FEE if oscillator range high Medium clock accuracy After IRG is trimmed Lowest system cost no external components required IRG is on DCO is on 1 1 The IRG typically consumes 100 A The FLL and DCO typi...

Page 257: ...fext 32 kHz Eqn 14 1 Solving for N R gives N R 8 38 MHz 32 kHz 64 4 we can choose N 4 and R 1 Eqn 14 2 The values needed in each register to set up the desired operation are ICGC1 38 00111000 Bit 7 H...

Page 258: ...ag ICGS2 xx This is read only should read DCOS 1 before performing any time critical tasks ICGFLTLU L xx Only needed in Self clocked Mode FLT will be adjusted by loop to give 8 38 MHz DCO clock Bits 1...

Page 259: ...r to set up the desired operation are ICGC1 78 01111000 Bit 7 HGO 0 Configures oscillator for low power operation Bit 6 RANGE 1 Configures oscillator for high frequency range FLL prescale factor is 1...

Page 260: ...P 64 fIRG 243 kHz Eqn 14 5 Solving for N R gives N R 10 8 MHz 243 7 kHz 64 4 86 We can choose N 10 and R 2 Eqn 14 6 A trim procedure will be required to hone the frequency to exactly 5 4 MHz An exampl...

Page 261: ...s is read only except for clearing interrupt flag ICGS2 xx This is read only good idea to read this before performing time critical operations ICGFLTLU L xx Not used in this example ICGTRM xx Bit 7 0...

Page 262: ...perating under user provided software control The MCU initiates a trim procedure as outlined in Figure 14 9 while the tester supplies a precision reference signal If the intended bus frequency is near...

Page 263: ...prescaler multiplication factor P It selects one of two reference frequency ranges for the The RANGE bit is write once after a reset The RANGE bit only has an effect in FLL engaged external and FLL b...

Page 264: ...E MFD LOCRE RFD Write Reset 0 0 0 0 0 0 0 0 Figure 14 11 Control Register 2 C2 Table 14 7 C2 Field Descriptions Field Description 7 LOLRE Loss of Lock Reset Enable The LOLRE bit determines what type o...

Page 265: ...LKST REFST LOLS LOCK LOCS ERCS IF Write 1 Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 14 12 Status Register 1 S1 Table 14 8 S1 Field Descriptions Field Description 7 6 CLKST Clock Mode Stat...

Page 266: ...t when an interrupt request is pending It is cleared by a reset or by reading the ICG status register when ICGIF is set and then writing a 1 to ICGIF If another ICG interrupt occurs before the clearin...

Page 267: ...nt filter value which controls the DCO frequency The FLT bits are read only except when the CLKS bits are programmed to Self clocked Mode CLKS 00 In Self clocked Mode any write to ICGFLTU updates the...

Page 268: ...reset Figure 14 16 ICG Trim Register TRM Table 14 12 TRM Field Descriptions Field Description 7 0 TRIM ICG Trim Setting The TRIM bits control the internal reference generator frequency They allow a 25...

Page 269: ...single 64 Kbyte address space 16 bit stack pointer any size stack anywhere in 64 Kbyte address space 16 bit index register H X with powerful indexed addressing modes 8 bit accumulator A Many instruct...

Page 270: ...registers H and X which often work together as a 16 bit address pointer where H holds the upper byte of an address and X holds the lower byte of the address All indexed addressing mode instructions us...

Page 271: ...e low order half of the stack pointer 15 3 4 Program Counter PC The program counter is a 16 bit register that contains the address of the next instruction or operand to be fetched During normal progra...

Page 272: ...s to correct the result to a valid BCD value 0 No carry between bits 3 and 4 1 Carry between bits 3 and 4 3 I Interrupt Mask Bit When the interrupt mask is set all maskable CPU interrupts are disabled...

Page 273: ...nue at the branch destination address 15 4 3 Immediate Addressing Mode IMM In Immediate Addressing Mode the operand needed to complete the instruction is included in the object code immediately follow...

Page 274: ...ded in the instruction as the address of the operand needed to complete the instruction The index register pair is then incremented H X H X 0x0001 after the operand has been fetched This addressing mo...

Page 275: ...terrupt that is pending when the interrupt sequence started The CPU sequence for an interrupt is 1 Store the contents of PCL PCH X A and CCR on the stack in that order 2 Set the I bit in the CCR 3 Fet...

Page 276: ...ignal to wake the target MCU from Stop Mode When a host debug system is connected to the background debug pin BKGD and the ENBDM control bit has been set by a serial command through the background int...

Page 277: ...r order least significant 8 bits PC Program counter PCH Program counter higher order most significant 8 bits PCL Program counter lower order least significant 8 bits SP Stack pointer Memory and addres...

Page 278: ...single integer in the range 0 7 opr8i Any label or expression that evaluates to an 8 bit immediate value opr16i Any label or expression that evaluates to a 16 bit immediate value opr8a Any label or ex...

Page 279: ...D opr16a ADD oprx16 X ADD oprx8 X ADD X ADD oprx16 SP ADD oprx8 SP Add without Carry A A M IMM DIR EXT IX2 IX1 IX SP2 SP1 AB BB CB DB EB FB 9EDB 9EEB ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 AIS...

Page 280: ...h if IRQ Pin High Branch if IRQ pin 1 REL 2F rr 3 BIL rel Branch if IRQ Pin Low Branch if IRQ pin 0 REL 2E rr 3 BIT opr8i BIT opr8a BIT opr16a BIT oprx16 X BIT oprx8 X BIT X BIT oprx16 SP BIT oprx8 SP...

Page 281: ...if A M Branch if A M DIR IMM IMM IX1 IX SP1 31 41 51 61 71 9E61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 5 6 CLC Clear Carry Bit C 0 0 INH 98 1 CLI Clear Interrupt Mask Bit I 0 0 INH 9A 1 CLR opr8a C...

Page 282: ...IMM DIR EXT IX2 IX1 IX SP2 SP1 A8 B8 C8 D8 E8 F8 9ED8 9EE8 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 INC opr8a INCA INCX INC oprx8 X INC X INC oprx8 SP Increment M M 0x01 A A 0x01 X X 0x01 M M 0x0...

Page 283: ...M M 0x00 M M M 0x00 M M M 0x00 M DIR INH INH IX1 IX SP1 30 40 50 60 70 9E60 dd ff ff 5 1 1 5 4 6 NOP No Operation Uses 1 Bus Cycle INH 9D 1 NSA Nibble Swap Accumulator A A 3 0 A 7 4 INH 62 1 ORA opr8i...

Page 284: ...0 DIR EXT IX2 IX1 IX SP2 SP1 B7 C7 D7 E7 F7 9ED7 9EE7 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 STHX opr8a STHX opr16a STHX oprx8 SP Store H X Index Reg M M 0x0001 H X 0 DIR EXT SP1 35 96 9EFF dd hh l...

Page 285: ...BIT 2 IMM B5 3 BIT 2 DIR C5 4 BIT 3 EXT D5 4 BIT 3 IX2 E5 3 BIT 2 IX1 F5 3 BIT 1 IX 06 5 BRSET3 3 DIR 16 5 BSET3 2 DIR 26 3 BNE 2 REL 36 5 ROR 2 DIR 46 1 RORA 1 INH 56 1 RORX 1 INH 66 5 ROR 2 IX1 76 4...

Page 286: ...EF 3 STX 2 IX1 FF 2 STX 1 IX INH Inherent REL Relative SP1 Stack Pointer 8 Bit Offset IMM Immediate IX Indexed No Offset SP2 Stack Pointer 16 Bit Offset DIR Direct IX1 Indexed 8 Bit Offset IX Indexed...

Page 287: ...C 3 SP1 9EDA 5 ORA 4 SP2 9EEA 4 ORA 3 SP1 9E6B 8 DBNZ 4 SP1 9EDB 5 ADD 4 SP2 9EEB 4 ADD 3 SP1 9E6C 6 INC 3 SP1 9E6D 5 TST 3 SP1 9EAE 5 LDHX 2 IX 9EBE 6 LDHX 4 IX2 9ECE 5 LDHX 3 IX1 9EDE 5 LDX 4 SP2 9E...

Page 288: ...MCU Central Processor Unit CPU MC1321x Reference Manual Rev 1 6 15 20 Freescale Semiconductor...

Page 289: ...also useful as extra external interrupt inputs and as an external means of waking up the MCU from stop or wait low power modes 16 1 1 KBI Block Diagram Figure 16 1 shows the block diagram for a KBI mo...

Page 290: ...n remains at the asserted level KBF can be used as a software pollable flag KBIE 0 or it can generate a hardware interrupt request to the CPU KBIE 1 0 No KBI interrupt pending 1 KBI interrupt pending...

Page 291: ...etection logic so that it detects edges and levels In KBIMOD 1 mode the KBF status flag becomes set when an edge is detected when one or more enabled pins change from the de asserted to the asserted l...

Page 292: ...ny KBI input pin If KBIE 1 in the KBISC register a hardware interrupt will be requested whenever KBF 1 The KBF flag is cleared by writing a 1 to the keyboard acknowledge KBACK bit When KBIMOD 0 select...

Page 293: ...ic for a 3 channel TPM1 and a separate 5 channel TPM2 However in the package TPM1 only has Channel 2 pinned out and TPM2 only has Channels1 2 3 and 4 pinned out The use of the fixed system clock XCLK...

Page 294: ...ware can read the counter value at any time without affecting the counting sequence Any write to either byte of the TPM1CNT counter resets the counter regardless of the data value written PRESCALE AND...

Page 295: ...fects When the TPM is using the channel 0 pin for an external clock the corresponding ELS0B ELS0A control bits should be set to 0 0 so channel 0 is not trying to use the same pin 17 3 2 TPM1CHn TPM1 C...

Page 296: ...1MODL When center aligned PWM operation is specified the counter counts upward from 0000 through its terminal count and then counts downward to 0000 where it returns to up counting Both 0000 and the t...

Page 297: ...optionally generate a CPU interrupt request 17 4 2 2 Output Compare Mode With the output compare function the TPM can generate timed pulses with programmable position polarity duration and frequency W...

Page 298: ...s the Up down counting Mode of the timer counter CPWMS 1 The output compare value in TPM1CnVH TPM1CnVL determines the pulse width duty cycle of the PWM signal and the period is determined by the value...

Page 299: ...e corresponding timer channel registers only after both 8 bit bytes of a 16 bit register have been written and the timer counter overflows reverses direction from up counting to down counting at the e...

Page 300: ...0000 on the next counting clock TOF becomes set at the transition from FFFF to 0000 When a modulus limit is set TOF becomes set at the transition from the value set in the modulus register to 0000 Whe...

Page 301: ...to the direct page register summary in Chapter 11 MCU Memory for the absolute address assignments for all TPM registers This section refers to registers and control bits only by their names A Freescal...

Page 302: ...etting CPWMS reconfigures the TPM to operate in Up down counting Mode for CPWM functions Reset clears CPWMS 0 All TPM1 channels operate as input capture output compare or Edge aligned PWM Mode as sele...

Page 303: ...tus control register TPM1SC Reset clears the TPM counter registers When Background Mode is active the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the st...

Page 304: ...pt so both bytes of the modulo register can be written well before a new overflow An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion abou...

Page 305: ...vent occurred on channel n 6 CHnIE Channel n Interrupt Enable This read write bit enables interrupts from channel n Reset clears CHnIE 0 Channel n interrupt requests disabled use software polling 1 Ch...

Page 306: ...reset Table 17 5 Mode Edge and Level Selection CPWMS MSnB MSnA ELSnB ELSnA Mode Configuration X XX 00 Pin not used for TPM channel use as an external clock for the TPM or revert to general purpose I...

Page 307: ...becomes unlatched when the TPM1CnSC register is written In output compare or PWM Modes writing to either byte TPM1CnVH or TPM1CnVL latches the value into a buffer When both bytes have been written th...

Page 308: ...MCU Timer PWM TPM Module MC1321x Reference Manual Rev 1 6 17 16 Freescale Semiconductor...

Page 309: ...y idle line or address mark 18 2 SCI System Description The SCI allows full duplex asynchronous NRZ serial communication among the MCU and remote devices including other MCUs The SCI comprises a baud...

Page 310: ...ercent for 8 bit data format and about 4 percent for 9 bit data format Although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates it is normally poss...

Page 311: ...originally used to gain the attention of old teletype receivers Break characters are a full character time of logic 0 including a 0 where the stop bit would be normally Normally a program would wait f...

Page 312: ...t bit of logic 0 eight or nine data bits LSB first and a stop bit of logic 1 For information about 9 bit data Mode refer H 8 7 6 5 4 3 2 1 0 L SCID Rx BUFFER READ ONLY INTERNAL BUS STOP 11 BIT RECEIVE...

Page 313: ...gh RT16 When a falling edge is located three more samples are taken at RT3 RT5 and RT7 to make sure this was a real start bit and not merely noise If at least two of these three samples are 0 the rece...

Page 314: ...is not affected by the data in the last character of the previous message 18 5 3 2 Address Mark Wakeup When WAKE 1 the receiver is configured for address mark wakeup In this mode RWU is cleared autom...

Page 315: ...RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer the overrun OR flag gets set instead and the data and any associated NF FE or...

Page 316: ...same register chooses between Loop Mode RSRC 0 or Single wire Mode RSRC 1 Single wire Mode is used to implement a half duplex serial connection The receiver is internally connected to the transmitter...

Page 317: ...mains disabled until the first time the receiver or transmitter is enabled RE or TE bits in SCIxC2 are written to 1 Figure 18 4 SCI1 Baud Rate Register SCIxBDH Figure 18 5 SCI1 Baud Rate Register SCIx...

Page 318: ...so the SCI can be the source of an interrupt that wakes up the CPU RSRC Receiver Source Select This bit has no meaning or effect unless the LOOPS bit is set to 1 When LOOPS 1 the receiver input is in...

Page 319: ...eans the total number of 1s in the data character including the parity bit is odd Even parity means the total number of 1s in the data character including the parity bit is even 1 Odd parity 0 Even pa...

Page 320: ...D1 pin reverts to being a general purpose port I O pin 1 Receiver on 0 Receiver off RWU Receiver Wakeup Control This bit can be written to 1 to place the SCI receiver in a standby state where it waits...

Page 321: ...cally by reading SCIxS1 with TC 1 and then doing one of the following Write to the SCI data register SCIxD to transmit new data Queue a preamble by changing TE from 0 to 1 Queue a break character by w...

Page 322: ...use there is no room to move it into SCIxD To clear OR read SCIxS1 with OR 1 and then read the SCI data register SCIxD 1 Receive overrun new SCI data lost 0 No overrun NF Noise Flag The advanced sampl...

Page 323: ...M 1 R8 can be thought of as a ninth receive data bit to the left of the MSB of the buffered data in the SCIxD register When reading 9 bit data both R8 and SCIxD must be read to complete the automatic...

Page 324: ...hen NF 1 0 NF interrupts disabled use polling FEIE Framing Error Interrupt Enable This bit enables the framing error flag FE to generate hardware interrupt requests 1 Hardware interrupt requested when...

Page 325: ...h IIC bus standard Multi master operation Software programmable for one of 64 different serial clock frequencies Software selectable acknowledge bit Interrupt driven byte by byte data transfer Arbitra...

Page 326: ...lock Diagram 19 2 Signal Description Table 19 1 shows the user accessible signals for the IIC Table 19 1 Signal Properties Name Function SCL Serial clock line SDA Serial data line INPUT SYNC IN OUT DA...

Page 327: ...isters accessible to the end user 19 4 1 Module Memory Map The IIC has five 8 bit registers The base address of the module is hardware programmable The IIC register map is fixed and begins at the modu...

Page 328: ...ile is used to translate these names into the appropriate absolute addresses 19 4 3 IIC Address Register IIC1A 19 4 4 IIC Frequency Divider Register IIC1F Offset 7 6 5 4 3 2 1 0 R ADDR 0 W Reset 0 0 0...

Page 329: ...rate bus speed Hz mul SCL divider SDA hold time is the delay from the falling edge of the SCL IIC clock to the changing of SDA IIC data The ICR is used to determine the SDA hold value SDA hold time bu...

Page 330: ...9 06 34 10 26 384 65 07 40 10 27 480 65 08 28 7 28 320 33 09 32 7 29 384 33 0A 36 9 2A 448 65 0B 40 9 2B 512 65 0C 44 11 2C 576 97 0D 48 11 2D 640 97 0E 56 13 2E 768 129 0F 68 13 2F 960 129 10 48 9 30...

Page 331: ...to a 0 a STOP signal is generated and the mode of operation changes from Master to Slave 0 Slave Mode 1 Master Mode 4 TX Transmit Mode Select The TX bit selects the direction of master and slave trans...

Page 332: ...BUSY bit is set when a START signal is detected and cleared when a STOP signal is detected 0 Bus is idle 1 Bus is busy 4 ARBL Arbitration Lost This bit is set by hardware when the arbitration procedu...

Page 333: ...D correctly by reading it back In Master Transmit Mode the first byte of data written to IIC1D following assertion of MST is used for the address transfer and should comprise of the calling address in...

Page 334: ...Address Transmission The first byte of data transferred immediately after the START signal is the slave address transmitted by the master This is a seven bit calling address followed by a R W bit The...

Page 335: ...ust be left high by the slave The master interprets the failed acknowledge as an unsuccessful data transfer If the master receiver does not acknowledge the slave transmitter after a data byte transmis...

Page 336: ...still within its low period Therefore synchronized clock SCL is held low by the device with the longest low period Devices with shorter low periods enter a high wait state during this time see Figure...

Page 337: ...ded the IICIE is set The CPU must check the SRW bit and set its Tx Mode accordingly 19 7 3 Arbitration Lost Interrupt The IIC is a true multi master bus that allows more than one master to be connecte...

Page 338: ...Inter Integrated Circuit IIC MC1321x Reference Manual Rev 1 6 19 14 Freescale Semiconductor...

Page 339: ...e MCU stops the clocks and the ATD analog circuitry is turned off placing the module into a low power state Once in Stop Mode the ATD module aborts any single or continuous conversion in progress Upon...

Page 340: ...TL DATA JUSTIFICATION INTERRUPT CONVERSION REGISTER SAR_REG 9 0 CONVERSION CLOCK PRESCALER BUSCLK CLOCK PRESCALER CTL STATUS STATE MACHINE CONVERSION MODE CONTROL BLOCK CONTROL AND REGISTERS CTL RESUL...

Page 341: ...wer is required to isolate the sensitive analog circuitry from the normal levels of noise present on digital power supplies NOTE VDDAD1 and VDD must be at the same potential Likewise VSSAD1 and VSS mu...

Page 342: ...le the module data bus reads data out of the register through the other port 20 3 2 Sample and Hold The S H machine accepts analog signals and stores them as capacitor charge on a storage node located...

Page 343: ...Continuous Convert Mode 5 LSB should be added to the known difference to account for leakage and other losses Delta analog input voltage VAIN This is the difference between the current input voltage...

Page 344: ...ATD is the step size of the ideal transfer function This is also referred to as the ideal code width or the difference between the transition voltages to a given code and to the next code This unit kn...

Page 345: ...due to the ATD Input leakage error EIL This is the error between the transition voltage to the current code and the ideal transition to that code that is the result of input leakage across the real po...

Page 346: ...4 5 6 7 8 9 A B C TOTAL UNADJUSTED IDEAL STRAIGHT LINE IDEAL TRANSFER 3 2 1 LSB D CODE TRANSFER FUNCTION FUNCTION TOTAL UNADJUSTED INL ASSUMES EZS EFS 0 ERROR BOUNDARY NEGATIVE DNL CODE WIDTH 1LSB POS...

Page 347: ...nterrupt requests and the MCU handles or services these requests Details on how the ATD interrupt requests are handled can be found in Chapter 12 MCU Resets Interrupts and System Configuration The ATD...

Page 348: ...bits 7 0 of ATD1RH result data bits 1 and 0 map onto ATD1RL bits 7 and 6 where bit 7 of ATD1RH is the most significant bit MSB Figure 20 5 Left Justified Mode For Right justified Mode result data bits...

Page 349: ...data is unsigned PRS Prescaler Rate Select This field of bits determines the prescaled factor for the ATD conversion clock Table 20 4 illustrates the divide by operation and the appropriate range of...

Page 350: ...ax bus clock frequency is computed from the max ATD conversion clock frequency times the indicated prescaler setting i e for a PRS of 0 max bus clock 2 max ATD conversion clock frequency 2 Factor 4 MH...

Page 351: ...lt registers at the end of each conversion When this bit is cleared only one conversion is completed between writes to the ATD1SC register 1 Continuous Conversion Mode 0 Single Conversion Mode ATDCH A...

Page 352: ...always located in ATD1RH bits 7 0 and the ATD1RL bits read 0 For 10 bit conversions the six unused bits always read 0 The ATD1RH and ATD1RL registers are read only 20 6 4 ATD Pin Enable ATD1PE Figure...

Page 353: ...modes One hardware address breakpoint built into BDC Oscillator runs in Stop Mode if BDC enabled COP watchdog disabled while in Active Background Mode Features of the debug module DBG include Two tri...

Page 354: ...slate commands from a host computer into commands for the custom serial interface to the single wire background debug system Depending on the development tool vendor this interface pod may use a stand...

Page 355: ...external capacitance plays almost no role in signal rise time The custom protocol provides for brief actively driven speed up pulses to force rapid rise times on this pin without risking harmful drive...

Page 356: ...cycle delay from the host generated falling edge on BKGD to the perceived start of the bit time in the target MCU The host holds the BKGD pin low long enough for the target to recognize it at least tw...

Page 357: ...kground mode commands require that the target MCU is currently in the Active Background Mode while non intrusive commands may be issued at any time whether the target MCU is in Active Background Mode...

Page 358: ...ITE_CONTROL Non intrusive C4 CC Write BDC controls in BDCSCR READ_BYTE Non intrusive E0 AAAA d RD Read a byte from target memory READ_BYTE_WS Non intrusive E1 AAAA d SS RD Read a byte and report statu...

Page 359: ...Drives a 1 cycle high speedup pulse to force a fast rise time on BKGD Removes all drive to the BKGD pin so it reverts to high impedance The host measures the low time of this 128 cycle sync response...

Page 360: ...t onto the chip with the MCU The debug system consists of an 8 stage FIFO that can store address or data bus information and a flexible trigger system to decide when to capture bus information and wha...

Page 361: ...BGFH then DBGFL to get one coherent word of information out of the FIFO Reading DBGFL the low order byte of the FIFO data port causes the FIFO to shift so the next word of information is available at...

Page 362: ...orce type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request The usual action in response to a breakpoint is to go to Active Background Mode rather than c...

Page 363: ...omparator A or the value in comparator B A Then B Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A There can be...

Page 364: ...oing to Active Background Mode 21 4 Register Definition This section contains the descriptions of the BDC and DBG registers and control bits Refer to the high page register summary in Chapter 11 MCU M...

Page 365: ...ode commands 6 BDMACT Background Mode Active Status This is a read only status bit 0 BDM not active user application program running 1 BDM active and waiting for serial commands 5 BKPTEN BDC Breakpoin...

Page 366: ...hould issue a READ_STATUS command to check that BDMACT 1 before attempting other BDC commands 0 Target CPU is running user application code or in Active Background Mode was not in wait or Stop Mode wh...

Page 367: ...High Register DBGCAH This register contains compare value bits for the high order eight bits of comparator A This register is forced to 0x00 at reset and can be read at any time or written at any time...

Page 368: ...igh order half of each FIFO word is unused When reading 8 bit words out of the FIFO simply read DBGFL repeatedly to get successive bytes of data from the FIFO It is not necessary to read DBGFH in this...

Page 369: ...an cause information to be stored in the FIFO without generating a break request to the CPU For an end trace CPU break requests are issued to the CPU when the comparator s and R W meet the trigger req...

Page 370: ...igger event is only signalled to the FIFO logic if the opcode at the match address is actually executed 0 Trigger on access to compare address force 1 Trigger if opcode at compare address is executed...

Page 371: ...s bit is set by writing 1 to the ARM control bit in DBGC while DBGEN 1 and is automatically cleared at the end of a debug run A debug run is completed when the FIFO is full begin trace or when a trigg...

Page 372: ...Development Support MC1321x Reference Manual Rev 1 6 21 20 Freescale Semiconductor...

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