Inter-Integrated Circuit (IIC)
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor
19-9
19.4.7
IIC Data I/O Register (IIC1D)
NOTE
When transitioning out of Master Receive Mode, the IIC Mode should be
switched before reading the IIC1D register to prevent an inadvertent
initiation of a master receive data transfer.
In Slave Mode, the same functions are available after an address match has occurred.
Note that the TX bit in IIC1C must correctly reflect the desired direction of transfer in Master and Slave
Modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master
receive is desired, then reading the IIC1D will not initiate the receive.
Reading the IIC1D will return the last byte received while the IIC is configured in either Master Receive
or Slave Receive Modes. The IIC1D does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IIC1D correctly by reading it back.
In Master Transmit Mode, the first byte of data written to IIC1D following assertion of MST is used for
the address transfer and should comprise of the calling address (in bit 7–bit 1) concatenated with the
required R/W bit (in position bit 0).
19.5
Functional Description
This section provides a complete functional description of the IIC module.
19.5.1
IIC Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
•
START signal
Offset
7
6
5
4
3
2
1
0
R
DATA
W
Reset
0
0
0
0
0
0
0
0
Figure 19-6. IIC Data I/O Register (IIC1D)
Table 19-8. IIC1D Register Field Descriptions
Field
Description
7:0
DATA
Data
— In Master Transmit Mode, when data is written to the IIC1D, a data transfer is initiated. The most
significant bit is sent first. In Master Receive Mode, reading this register initiates receiving of the next byte of data.
Summary of Contents for freescale semiconductor MC13211
Page 40: ...MC1321x Pins and Connections MC1321x Reference Manual Rev 1 6 2 6 Freescale Semiconductor...
Page 166: ...Modem Modes of Operation MC1321x Reference Manual Rev 1 6 7 22 Freescale Semiconductor...
Page 172: ...Modem Interrupt Description MC1321x Reference Manual Rev 1 6 8 6 Freescale Semiconductor...
Page 186: ...MCU Modes of Operation MC1321x Reference Manual Rev 1 6 10 8 Freescale Semiconductor...
Page 208: ...MCU Memory MC1321x Reference Manual Rev 1 6 11 22 Freescale Semiconductor...
Page 244: ...MCU Parallel Input Output MC1321x Reference Manual Rev 1 6 13 20 Freescale Semiconductor...
Page 288: ...MCU Central Processor Unit CPU MC1321x Reference Manual Rev 1 6 15 20 Freescale Semiconductor...
Page 308: ...MCU Timer PWM TPM Module MC1321x Reference Manual Rev 1 6 17 16 Freescale Semiconductor...
Page 338: ...Inter Integrated Circuit IIC MC1321x Reference Manual Rev 1 6 19 14 Freescale Semiconductor...
Page 372: ...Development Support MC1321x Reference Manual Rev 1 6 21 20 Freescale Semiconductor...
