NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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Inter-Integrated Circuit (IIC)
MC1321x Reference Manual, Rev. 1.6
19-10 Freescale Semiconductor
• Slave address transmission
• Data transfer
• STOP signal
The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system
communication is described briefly in the following sections and illustrated in
Figure 19-7 .
Figure 19-7. IIC Bus Transmission Signals
19.5.1.1 START Signal
When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal. As shown in
Figure 19-7 , a
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
19.5.1.2 Slave Address Transmission
The first byte of data transferred immediately after the START signal is the slave address transmitted by
the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Only the slave with a calling address that matches the one transmitted by the master will respond by
sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see
Figure 19-7 ).
SCL
SDA
START
SIGNAL
ACK
BIT
1 2 3 4 5 6 7 8
MSB LSB
1 2 3 4 5 6 7 8
MSB LSB
STOP
SIGNAL
NO
SCL
SDA
1 2 3 4 5 6 7 8
MSB LSB
1 2 5 6 7 8
MSB LSB
REPEATED
3 4
9 9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0
CALLING ADDRESS READ/ DATA BYTE
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
NEW CALLING ADDRESS
9 9
XX
ACK
BIT
WRITE
START
SIGNAL
START
SIGNAL
ACK
BIT
CALLING ADDRESS READ/
WRITE
STOP
SIGNAL
NO
ACK
BIT
READ/
WRITE