NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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Modem SPI Register Descriptions
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 5-11
5.10 Control_B - Register 07
The Control_B Register 07 is one of several registers that provide control fields for the MC1321x.
Bits 5-4 cca_type[1:0] — The clear channel assessment type bits
selects one of two possible CCA functions. Algorithm results
are reported in field cca_final[7:0], RX_Status Register 2D,
Bits 15 - 8.
01 = clear channel assessment
10 = energy detection
Bits 1-0 xcvr_seq[1:0] — The transceiver operation bits select one
of four possible transceiver modes.
00 = Idle (default)
01 = CCA /energy detection
10 = Packet Mode RX
11 = Packet Mode TX
Register 07
0x07
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tmr_load
ct_bias_en
ct_bia
s
_inv
RF_switch_
m
o
d
e
miso
_hiz_
en
cl
ko_do
ze_e
n
tx_d
one
_mask
rx_
done
_mask
use_
strm_mode
hib
_en
d
o
ze_e
n
TYPE r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
RESET
0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
0x0C00
Table 5-9. Register 07 Description
Name Description Operation
Bits 14-12,
10, 8, 4-2 Reserved Leave default
Bit 15 tmr_load — The load Event Timer bit, when programmed from low to
high, causes the value of the SPI field tmr_cmp1[23:0] to be loaded
into the Event Timer.
Write from 0 to 1 to affect load. Rewrite to
0, before writing another 1 to affect
another load.
Bit 14 ct_bias_en — The CT_Bias enable bit controls when the signal
CT_Bias is active.
1 = CT_Bias enabled. Output state is
defined by
Table 3-5 .
0 = CT_Bias disabled. Output state is
tristated.
Bit 13 ct_bias_inv — The CT_Bias Invert bit inverts the sense of the
CT_Bias output signal when the CT_Bias is used as a control signal
for dual port operation
The output state of CT_Bias under varying
conditions is defined in
Table 3-5 .
1 = CT_Bias inverted.
0 = CT_Bias not inverted
Table 5-8. Register 06 Description (continued)
Name Description Operation