NXP Semiconductors freescale semiconductor MC13211, Reference Manual

Page: 122 / 372

Modem SPI Register Descriptions
MC1321x Reference Manual, Rev. 1.6
5-22 Freescale Semiconductor
5.21 Tmr_Cmp2_A - Register 1D
The Tmr_Cmp2_A Register 1B contains the disable bit for Timer Comparator 2 and stores the most
significant 8 bits of the 24-bit compare value (the lower 16 bits of the compare value are stored in
Tmr_CMP2_B Register 1E). With regard to using the timer comparator:
• It is suggested that the timer be disabled (writing tmr_cmp2_dis to 1) during system initialization
as the default mode out of reset is timer enabled.
• The value in Register 1D will not be loaded in the comparator and the affect of the timer disable
bit will not active until Register 1E is written. The 24-bit comparator value must be loaded into the
comparator register in parallel, and as a result, the load is caused by a write Register 1E.
Writing of Registers 1D and 1E can be done as a recursive SPI register write transaction or two separate
singular transactions. Writing to Register 1E as a separate operation will always use the present value of
Register 1D to load the comparator value and set the state of the disable bit.
Register 1D
0x1D
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tmr_
cmp
2_d
is
tmr_cmp2[23:16]
TYPE r/w r/w
RESET
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0x00FF
Table 5-22. Register 1D Description
Name Description Operation
Bits 14-8 Reserved Leave default
Bit 15 tmr_cmp2_dis — This bit disables the Event Timer Comparator 2. 1 = Disables the Event Timer Compare 2
function.
0 = Enables the Event Timer Compare 2
function (default).
Bits 7-0 tmr_cmp2[23:16] — These bits represent the 8 most significant bits
of 24-bit Event Timer 2 absolute time compare value,
tmr_cmp2[23:0].
Default is 0xFF.