NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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MCU Parallel Input/Output
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 13-15
Figure 13-13. Port E Registers
PTEDn — Port E Data Register Bit n (n = 0–7)
For port E pins that are inputs, reads return the logic level on the pin. For port E pins that are configured
as outputs, reads return the last value written to this register.
Writes are latched into all bits in this register. For port E pins that are configured as outputs, the logic
level is driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
PTEPEn — Pullup Enable for Port E Bit n (n = 0–7)
For port E pins that are inputs, these read/write control bits determine whether internal pullup devices
are enabled. For port E pins that are configured as outputs, these bits are ignored and the internal pullup
devices are disabled.
1 = Internal pullup device enabled.
0 = Internal pullup device disabled.
PTESEn — Slew Rate Control Enable for Port E Bit n (n = 0–7)
For port E pins that are outputs, these read/write control bits determine whether the slew rate controlled
outputs are enabled. For port E pins that are configured as inputs, these bits are ignored.
1 = Slew rate control enabled.
0 = Slew rate control disabled.
PTED
Bit 7 6 5 4 3 2 1 Bit 0
Read: PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0
Write:
Reset: 0 0 0 0 0 0 0 0
PTEPE
Read: PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
Write:
Reset: 0 0 0 0 0 0 0 0
PTESE
Read: PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0
Write:
Reset: 0 0 0 0 0 0 0 0
PTEDD
Read: PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0
Write:
Reset: 0 0 0 0 0 0 0 0