NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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MCU Timer/PWM (TPM Module)
MC1321x Reference Manual, Rev. 1.6
17-10 Freescale Semiconductor
Table 17-1. TPM1SC Register Field Descriptions
Field Description
7
TOF
Timer Overflow Flag — This flag is set when the TPM counter changes to $0000 after reaching the modulo
value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set
after the counter has reached the value in the modulo register, at the transition to the next lower count value.
Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If another
TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set
after the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow
1 TPM counter has overflowed
6
TOIE
Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an
interrupt is generated when TOF equals 1. Reset clears TOIE.
0 TOF interrupts inhibited (use software polling)
1 TOF interrupts enabled
5
CPWMS
Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the
TPM operates in Up-counting Mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconfigures the TPM to operate in Up-/down-counting Mode for CPWM functions. Reset clears
CPWMS.
0 All TPM1 channels operate as input capture, output compare, or Edge-aligned PWM Mode as selected by the
MSnB:MSnA control bits in each channel’s status and control register
1 All TPM1 channels operate in Center-aligned PWM Mode
4:3
CLKS[B:A]
Clock Source Select — As shown in Table 17-2 , this 2-bit field is used to disable the TPM system or select one
of three clock sources to drive the counter prescaler. The external source and the XCLK are synchronized to the
bus clock by an on-chip synchronization circuit.
2:0
PS[2:0]
Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in
Table 17-3 . This prescaler is located after any clock source synchronization or clock source selection, so it affects
whatever clock source is selected to drive the TPM system.
Table 17-2. TPM Clock Source Selection
CLKSB:CLKSA TPM Clock Source to Prescaler Input
0:0 No clock selected (TPM disabled)
0:1 Bus rate clock (BUSCLK)
1:0 Fixed system clock (XCLK)
1:1 External source (TPM1 Ext Clk)
1
,
2
1
The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency.
2
When the TPM1CH0 pin is selected as the TPM clock source, the corresponding ELS0B:ELS0A control bits should be set to
0:0 so channel 0 does not try to use the same pin for a conflicting function.
Table 17-3. Prescale Divisor Selection
PS2:PS1:PS0 TPM Clock Source Divided-By
0:0:0 1
0:0:1 2
0:1:0 4
0:1:1 8
1:0:0 16