NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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Modem Miscellaneous Functions
MC1321x Reference Manual, Rev. 1.6
9-6 Freescale Semiconductor
9.4.3 Enable CLKO During Doze Mode (clko_doze_en, Control_B Register
07, Bit 9)
Bit clko_doze_en, Control_B register 07, Bit 9, is used to control CLKO during Doze Mode. If
clko_doze_en is set to 1 before entering Doze Mode, CLKO will continue to toggle while the MC1321x
is in Doze Mode. The CLKO frequency must be set for 1 MHz or lower. Default out of reset is
clko_doze_en = 0 as a power-saving measure.
If clko_doze_en = 0 and CLKO was enabled, CLKO will stop toggling 128 reference clock (16 MHz)
cycles after the doze_en bit is programmed to 1. CLKO will automatically re-start after exiting Doze.
9.4.4 Setting CLKO Output Drive Strength (clko_drv[1:0], GPIO_Data_Out
Register 0C, Bits 11-10)
The CLKO output drive strength can be programmed to 4 different levels by writing to clko_drv[1:0],
GPIO_Data_Out Register 0C, Bits 11-10. The default value is the lowest drive value of 00. Note that for
higher frequencies such as 16 MHz, the CLKO must be programmed for highest drive.
Table 9-1 shows
output drive strength for maximum frequency and maximum load capacitance.
9.5 Input Pin ATTN
The attention or ATTN signal is used to exit either Doze Mode or Hibernate Mode.
NOTE
Doze Mode may also be exited via a tmr_cmp2 compare event. A transition
event from high to low (assertion) on ATTN will always exit either mode.
The ATTN assertion low event can also generate an interrupt. The interrupt status bit is attn_irq,
IRQ_Status Register 24, Bit 10, and the interrupt mask bit is attn_mask, IRQ_Mask Register 05, Bit 15.
Table 9-1. CLKO Drive Strength Versus clko_drv[1:0] Value
Drive Strength
(clko_drv[1:0]) Max Freq
(MHz)
Max C
load
(pF)
00 1 20
01 8 20
10 16 20
11 16 20<C
load