NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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Inter-Integrated Circuit (IIC)
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 19-5
Table 19-4. IIC1F Register Field Descriptions
Field Description
7:6
MULT
IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL
divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
00 mul = 01
01 mul = 02
10 mul = 04
11 Reserved
5:0
ICR
IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection. These bits are used to
define the SCL divider and the SDA hold value. The SCL divider multiplied by the value provided by the MULT
register (multiplier factor mul) is used to generate IIC baud rate.
IIC baud rate = bus speed (Hz)/(mul * SCL divider)
SDA hold time is the delay from the falling edge of the SCL (IIC clock) to the changing of SDA (IIC data). The
ICR is used to determine the SDA hold value.
SDA hold time = bus period (s) * SDA hold value
Table 19-5 provides the SCL divider and SDA hold values for corresponding values of the ICR. These values can
be used to set IIC baud rate and SDA hold time. For example:
Bus speed = 8 MHz
MULT is set to 01 (mul = 2)
Desired IIC baud rate = 100 kbps
IIC baud rate = bus speed (Hz)/(mul * SCL divider)
100000 = 8000000/(2*SCL divider)
SCL divider = 40
Table 19-5 shows that ICR must be set to 0B to provide an SCL divider of 40 and that this will result in an SDA
hold value of 9.
SDA hold time = bus period (s) * SDA hold value
SDA hold time = 1/8000000 * 9 = 1.125
μ
s
If the generated SDA hold value is not acceptable, the MULT bits can be used to change the ICR. This will result
in a different SDA hold value.
ICR — IIC Clock Rate Bits