NXP Semiconductors freescale semiconductor MC13211, Reference Manual

Page: 363 / 372

Development Support
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 21-11
A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF flag and
clears the AF and BF flags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets
full. An end-trace run ends when the selected trigger event occurs. Any debug run can be stopped manually
by writing a 0 to ARM or DBGEN in DBGC.
In all Trigger Modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only
trigger modes, the FIFO stores data in the low-order eight bits of the FIFO.
The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type
traces. When TRGSEL = 1 to select opcode fetch triggers, it is not necessary to use R/W in comparisons
because opcode tags would only apply to opcode fetches that are always read cycles. It would also be
unusual to specify TRGSEL = 1 while using a full mode trigger because the opcode value is normally
known at a particular address.
The following Trigger Mode descriptions only state the primary comparator conditions that lead to a
trigger. Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and
the corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with
optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1 and TAG determines
whether the CPU request will be a tag request or a force request.
• A-Only — Trigger when the address matches the value in comparator A
• A OR B — Trigger when the address matches either the value in comparator A or the value in
comparator B
• A Then B — Trigger when the address matches the value in comparator B but only after the
address for another cycle matched the value in comparator A. There can be any number of cycles
after the A match and before the B match.
• A AND B Data (Full Mode) — This is called a Full Mode because address, data, and R/W
(optionally) must match within the same bus cycle to cause a trigger event. Comparator A checks
address, the low byte of comparator B checks data, and R/W is checked against RWA if
RWAEN = 1. The high-order half of comparator B is not used.
• In Full Trigger Mode it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1),
but if users do, the comparator B data match is ignored for the purpose of issuing the tag request
to the CPU and the CPU breakpoint is issued when the comparator A address matches.
• A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the
low half of comparator B, and R/W must match RWA if RWAEN = 1. All three conditions must be
met within the same bus cycle to cause a trigger.
• In Full Trigger Mode it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1),
but if users do, the comparator B data match is ignored for the purpose of issuing the tag request
to the CPU and the CPU breakpoint is issued when the comparator A address matches.
• Event-Only B (Store Data) — Trigger events occur each time the address matches the value in
comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when
the FIFO becomes full.
• A Then Event-Only B (Store Data) — After the address has matched the value in comparator A,
a trigger event occurs each time the address matches the value in comparator B. Trigger events
cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full.