MC1321x Serial Peripheral Interface (SPI)
MC1321x Reference Manual, Rev. 1.6
4-22
Freescale Semiconductor
4.12
Modem Program Reset (Writing Address 0x00)
A special access is a modem software reset capability known as a “Software Reset”. When R/W Register
Address 0x00 is written, an internal chip reset of the digital core is generated. All synchronous logic in the
MC1321x digital core is reset and the SPI register fields are returned to their default values. This Software
Reset has the same effect on the MC1321x digital core as asserting the external RST pin except RAM
contents are retained.
The Software Reset asserts internally as soon as the 8-bit header field containing Address 0 is shifted into
the MOSI pin and a write operation is specified. The Software Reset remains asserted internally until the
CE pin is negated. Reading from Register 00 does not generate a reset.
4.13
Configuring MCU Registers for Proper SPI Operation
The MCU SPI module must be configured for proper operation to meet the modem SPI transaction format.
The following conditions must be met:
•
MCU is master
•
Maximum baud rate is 8 MHz
•
Proper clock format must be selected, i.e., CPHA = 0 and CPOL = 0
•
SPI data must be transferred MSB first
•
Slave select is required but cannot be toggled as a normal SPI transfer (active one byte at-a-time).
SS1 must be controlled as a GPIO pin, i.e., PTE2 to meet the protocol
4.13.1
Set SPI Module Mode
4.13.1.1
SPI1CI Register Settings
The following register settings apply:
•
SPIE (Bit 7)- Used to control SPI interrupt as required
•
SPE (Bit 6)- Used to enable SPI system as required
•
SPTIE (Bit 5)- Used to control transmit interrupt as required
•
MSTR (Bit 4) = 1 - Master Mode selected
•
CPOL (Bit 3) = 0 - Active high SPI clock polarity (default); idles low
•
CPHA (Bit 2) = 0 - First edge on SPSCK occurs at middle of 1st cycle of an 8-cycle data transfer
•
SSOE (Bit 1) = 0 - SS1 pin will be controlled as a GPIO (PTE2) (default), and MODFEN bit must
be “0”
•
LBBFE (Bit 0) = 0 - Serial data is starts with MSB (default)
Summary of Contents for freescale semiconductor MC13211
Page 40: ...MC1321x Pins and Connections MC1321x Reference Manual Rev 1 6 2 6 Freescale Semiconductor...
Page 166: ...Modem Modes of Operation MC1321x Reference Manual Rev 1 6 7 22 Freescale Semiconductor...
Page 172: ...Modem Interrupt Description MC1321x Reference Manual Rev 1 6 8 6 Freescale Semiconductor...
Page 186: ...MCU Modes of Operation MC1321x Reference Manual Rev 1 6 10 8 Freescale Semiconductor...
Page 208: ...MCU Memory MC1321x Reference Manual Rev 1 6 11 22 Freescale Semiconductor...
Page 244: ...MCU Parallel Input Output MC1321x Reference Manual Rev 1 6 13 20 Freescale Semiconductor...
Page 288: ...MCU Central Processor Unit CPU MC1321x Reference Manual Rev 1 6 15 20 Freescale Semiconductor...
Page 308: ...MCU Timer PWM TPM Module MC1321x Reference Manual Rev 1 6 17 16 Freescale Semiconductor...
Page 338: ...Inter Integrated Circuit IIC MC1321x Reference Manual Rev 1 6 19 14 Freescale Semiconductor...
Page 372: ...Development Support MC1321x Reference Manual Rev 1 6 21 20 Freescale Semiconductor...
