NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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MCU Internal Clock Generator (ICG)
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 14-13
Figure 14-5. Register Set
14.4.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz
In this example, the FLL will be used (in FEE Mode) to multiply the external 32 kHz oscillator up to
8.38 MHz to achieve 4.19 MHz bus frequency.
After the MCU is released from reset, the ICG is in Self-clocked Mode (SCM) and supplies approximately
8 MHz on ICGOUT, which corresponds to a 4 MHz bus frequency (f
Bus
).
The clock scheme will be FLL engaged, external (FEE). So
f
ICGOUT
= f
ext
* P * N / R ; P = 64, f
ext
= 32 kHz Eqn. 14-1
Solving for N / R gives:
N / R = 8.38 MHz /(32 kHz * 64) = 4 ; we can choose N = 4 and R =1 Eqn. 14-2
The values needed in each register to set up the desired operation are:
ICGC1 = $38 (%00111000)
Bit 7 HGO 0 Configures oscillator for low-power operation
1
Ensure that
f
ICGDCLK
, which is equal to
f
ICGOUT
* R, does not exceed f
ICGDCLKmax.
Table 14-5. MFD and RFD Decode Table
MFD Value Multiplication Factor (N) RFD Division Factor (R)
000 4 000
÷
1
001 6 001
÷
2
010 8 010
÷
4
011 10 011
÷
8
100 12 100
÷
16
101 14 101
÷
32
110 16 110
÷
64
111 18 111
÷
128
Register Bit 7 6 5 4 3 2 1 Bit 0
ICGC1 HGO RANGE REFS CLKS OSCSTEN LOCD 0
ICGC2 LOLRE MFD LOCRE RFD
ICGS1 CLKST REFST LOLS LOCK LOCS ERCS ICGIF
ICGS2 0 0 0 0 0 0 0 DCOS
ICGFLTU 0 0 0 0 FLT
ICGFLTL FLT
ICGTRM TRIM
= Unimplemented or Reserved