NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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MC1321x Serial Peripheral Interface (SPI)
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 4-21
4.11.3.2.1 Transmit Packet RAM Write Access Flow
Before data is actually written to the Tx Packet RAM, the Tx payload length must be written into field
tx_pkt_length[6:0], TX_Pkt_Ctl Register 03, Bit 6 - 0. The maximum length is 127 bytes and is the number
of actual payload bytes transmitted which includes 2 CRC bytes. The CRC bytes transmitted are generated
by the transceiver hardware and are not loaded into the Packet RAM.
The following is a typical flow to write data to the Packet RAM:
1. Determine which of the two Transmit Packet RAMs are to be used - If Transmit Packet RAM2 is
to be used, set status bit tx_ram2_select, TX_Pkt_Ctl Register 03, Bit 15. The default is Transmit
Packet RAM1 selected. Note that the tx_ram2_select status determines which transmit Packet
RAM is accessed by an SPI transaction as well as which RAM is used during Transmit Mode.
2. Calculate the number of SPI bursts that are required to write the Tx packet data, noting the
following:
a) The CRC bytes are not written to Transmit Packet RAM.
b) The maximum number of Tx packet data bytes is 125.
c) All data written during an access must be done on 16-bit or 2-byte boundaries. Therefore, for
an odd number of bytes, the byte count must be rounded up to an even number and an extra
dummy byte will be written.
3. Do a recursive SPI write transaction where:
a) MCU asserts CE low.
b) MCU sends the MC1321x the first SPI burst with header field of R/W bit = 0 and address field
Addr[5:0] = 0x02 for the TX_Pkt_RAM register address.
c) MCU writes the MC1321x data with the number of SPI byte bursts as calculated in Step 2. The
number of SPI write bursts must be an even number.
d) MCU negates CE high.
4.11.3.2.2 Transmit Packet RAM Write Access Error Conditions
Two types of errors can occur during a Packet RAM write:
1. RAM address error - This can occur during software development and debug. If the recursive write
access exceeds 64 words (128 SPI data bursts), the internal read address counter will exceed the
RAM address and generate an error indication via status bit ram_addr_err, IRQ_Status Register 24,
Bit 14. An interrupt request can be generated with the error status by setting mask bit
ram_addr_mask, IRQ_Mask Register 5, Bit 12. As with other interrupt requests, the status is
cleared by reading the IRQ_Status register.
2. RAM arbitration busy - if the transceiver internal logic attempts to access the RAM during an SPI
write access (an SPI access during an active Tx sequence), an error indication will be generated via
status bit arb_busy_err, IRQ_Status Register 24, Bit 13. An interrupt request can be generated with
the error status by setting mask bit arb_busy_mask, IRQ_Mask Register 5, Bit 11. As with other
interrupt requests, the status is cleared by reading the IRQ_Status register.