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MICRF405

290MHz – 980MHz ISM Band

ASK / FSK Transmitter

MicroLead Frame and MLF are registered trademarks of Amkor Technologies
RadioWire is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

April 2006

M9999-041906

(408) 955-1690

General Description

The MICRF405 is a 290MHz-980MHz RF transmitter
IC designed for unlicensed ISM band operations. It's
designed to work in the North American 315MHz
and 915MHz bands as well as the European
433MHz and 868MHz bands. The device is fully
FCC Part 15.247 and EN300-220-compliant.
The transmitter consists of a FSK/ASK modulator,
PLL frequency synthesizer and a power amplifier.
The frequency synthesizer consists of a voltage-
controlled oscillator (VCO), a crystal oscillator, dual
modulus prescaler, programmable frequency
dividers and a phase-detector. The loop-filter can be
internal or external. The output power of the power
amplifier can be programmed to eight levels. A lock
detect circuit detects when the PLL is in lock.
In FSK mode, the user can select between three
different modulation types allowing a data rate up to
200kbps. When selecting FSK modulation applied
with dividers, the MICRF405 is switching between to
sets of register values (M0,N0,A0:"0" and M1,N1
and A1:"1"). The second modulation type is closed
loop VCO modulation using the internal modulator
that applies the modulated data to the VCO. The
third FSK modulation type is Open loop VCO
modulation.
In ASK modulation, the user can select between two
modulation types, with or without spreading. In both
modes the modulation depth is programmable.

RadioWire

®

Features

•

FSK/ASK transmitter

•

Frequency programmable

•

ASK modulation depth programmable

•

High efficiency power amplifier

•

Programmable output power

•

Power down function

•

MCU reference clock

•

Base band package engine

•

TX buffer

•

No external tuning circuitry

Applications

•

Meter reading

•

Automotive

•

Smart Home

•

Remote control systems

•

Residential Automation

•

Wireless security system

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Summary of Contents for MICRF405

Page 1: ...ernal or external The output power of the power amplifier can be programmed to eight levels A lock detect circuit detects when the PLL is in lock In FSK mode the user can select between three different modulation types allowing a data rate up to 200kbps When selecting FSK modulation applied with dividers the MICRF405 is switching between to sets of register values M0 N0 A0 0 and M1 N1 and A1 1 The...

Page 2: ...ers 10 What to write 10 How to write 10 Writing to n Registers Having Incremental Addresses 10 What to write 11 Writing to n Registers Having Non Incremental Addresses 12 Reading from the Control Registers in MICRF405 12 Reading from the Interrupt Register 12 Data Interface and Data Transfer 13 Packet Engine Overview 14 How to transmit a Packet with the Packet Engine 15 Programming Summary 17 Main...

Page 3: ...1906 408 955 1690 Ordering Information Part Number Junction Temp Range 1 Package MICRF405YML 40 to 125 C PB Free 24 Pin MLF ____________________________________________________________________________________________________ Block Diagram ...

Page 4: ...ator input 9 DVDD Digital VDD 10 DGND Digital ground 11 VDD VDD 12 LD O Lock Detect output 13 CLKOUT O Programmable Clock output 14 RDY DATACLK O Transmit buffer Ready Alternative Data clock 15 DATAIN I Alternative Data input 16 SCK I SPI clock 17 SIO I O Serial input output 18 SEN I Serial programming interface enable 19 SRV O Service interrupt pin 20 CPOUT O Charge pump output 21 VARIN I VCO var...

Page 5: ... 2 3 6 V Power Down Current 0 3 µA Standby Current ClkOut_en 0 200 µA PLL mode current PA2 0 000 PA off 5 6 mA VCO and PLL Section Reference Frequency 4 40 MHz 1kHz loop filter bandwidth Fphd 200kHz 7 0 ms 3kHz loop filter bandwidth Fphd 500kHz 1 8 ms PLL startup 30kHz loop filter bandwidth Fphd 1000kHz 140 µs Standby TX PA on 30kHz bandwidth 200 µs Crystal Oscillator Start Up Time 16MHz 9pF load ...

Page 6: ...kbps bandwidth for 99 of total power RBW 10kHz 120 kHz 2 nd Harmonic 36 dBm 3 rd Harmonic 54 dBm Spurious Emission 1GHz 54 dBm Spurious Emission 1GHz 41 dBm LO Leakage Measured with matching network 80 dBm Notes 1 Exceeding the absolute maximum rating may damage the device 2 The device is not guaranteed to function outside its operating rating 3 On the pins RFVDD 3 PTATBIAS 6 DVDD 9 CPOUT 20 VARIN...

Page 7: ...0 1 0000110 A1_5 0 A1_4 1 A1_3 1 A1_2 1 A1_1 1 A1_0 1 0000111 N1_11 0 N1_10 0 N1_9 0 N1_8 0 0001000 N1_7 0 N1_6 1 N1_5 1 N1_4 0 N1_3 1 N1_2 1 N1_1 1 N1_0 1 0001001 M1_11 0 M1_10 0 M1_9 0 M1_8 0 0001010 M1_7 0 M1_6 0 M1_5 1 M1_4 0 M1_3 0 M1_2 0 M1_1 0 M1_0 0 0001011 LowBatt_en 1 Freq_Band1 0 Freq_Band0 1 VCO_freq2 0 VCO_freq1 1 VCO_freq0 1 Modulation1 1 Modulation0 0 0001100 LowBatt_level 0 LDO_by ...

Page 8: ...f Min time of falling edge of SEN to falling edge of SCK 0 ns Tsenr Min delay from rising edge of SEN to rising edge of SCK 5 ns Twrite Min delay from valid SIO to falling edge of SCK during a write operation 0 ns Tread Min delay from rising edge of SCK to valid SIO during a read operation assuming load capacitance of SIO is 25pF 75 ns Trdy Min delay from falling edge of SCK last bit of byte into ...

Page 9: ...g to the Control Registers How to write Bring SEN low to start a write sequence The active state of the SEN line is low Use the SCK SIO serial interface to clock in Address and R W bit and Values into the MICRF405 MICRF405 will sample the SIO line at negative edges of SCK Make sure to change the state of the SIO line before the negative edge for instance on positive edge Refer to Figure 2 Bring SE...

Page 10: ... is transferred through SPI write address 0 28 Address 29 is only written to during data transfer not during configuration What to write Field Comments Address 0000000 address of the first register to write to which is 0 R W bit 0 for writing Values 1 st Octet wanted values for ControlRegister0 2 nd Octet wanted values for ControlRegister1 and so on for all of the octets Table 5 When writing to Al...

Page 11: ... D6 D0 D7 MSB D0 LSB written to control reg with address I n 1 Table 6 When writing to Registers having Incremental Addresses totally 1 n octets are clocked into the MICRF405 How to write Bring SEN low Use SCK and SIO to clock in the 1 n octets Bring SEN high SEN SIO SCK Register i address Data to write into register i Internal load pulse generated here A6 A5 A0 R W D7 D6 D0 D7 D6 D0 D7 D6 D0 Data...

Page 12: ... i e values are not changed The SIO line is output from the MICRF405 input to user for a part of the read sequence Refer to procedure description below A read sequence is described for reading n registers where n is number 1 30 SEN SIO SCK Register address Data read from register Internal load pulse generated here A6 A5A4 A3 A2 A1 A0R W D7 D6D5D4D3D2D1 D0 SIO INPUT SIO OUTPUT SAMPLE TIME Figure 4 ...

Page 13: ...ly valid and do not need any load pulse This also applies to the SyncID registers address 25 28 When writing to address 29 the address counter will not increment which means several bytes can be written into the buffer without raising SEN and setting up a new write session The RDY DATACLK pin will provide byte synchronization The data byte buffer is ready for refill on falling edges on RDY In this...

Page 14: ...ual Wire Packet Structure SyncID field Packet Engine Overview Preamble generated by packet engine 1 4 bytes equal 10101010 Length set by Pream_Len 1 0 SyncID field added by packet engine 1 4 bytes of user defined content Length set by SyncID_Len 1 0 Content set in registers SyncID0 SyncID1 SyncID2 and SyncID3 address 28 25 The frame length is entered by user for each packet Specify the length of t...

Page 15: ...D and Frame length PROG INIT WRITE SEQUENCE SET SEN 0 WRITE CONTROL WORD ADDRESS R W CONTROL WORD LOAD CONTROL WORD SET SEN 1 RETURN Control word e g TX mode Mode1 0 3 TX PA_LDc 1 Turns on PA stage when PLL is in lock MOD_LDc_en 1 Modulation starts once frame length is written into data byte and PA is turned on and LD is high PA_FEc_en 1 The PA is turned off immediately after last bit in packet is...

Page 16: ... of RDY and before the next falling edge of RDY 5 In this step all user data is received in the 405 and it transmits the last part of the packet This means that the SEN now can be pulled high at any time closing the write session If PA_LDc_en 1 and load_en 1 it is then necessary to leave SEN low until the end of packet This is because raising SEN will generate a load pulse and this in turn causes ...

Page 17: ... MICRF405 writes on positive edges Address field is 7 bits long Enter MSB first R W bit is 1 for read and 0 for write Address and R W bit together make 1 octet Enter read MSB in every octet first Always write 8 bits to read 8 bits from a control register This is the case for registers with less than 8 used bits as well Writing Bring SEN low write address and R W bit followed by the new values to f...

Page 18: ...ly 10dBm For maximum output power the load seen by the PA must be resistive and around 150Ω at 900MHz and 250Ω at 434MHz and 315Hz The output power can be programmed with bits PA 2 0 to eight different levels if bit PA_LDc_en 1 or seven levels if PA_LDc_en 0 with approximately 3dB between each step If PA_LDc_en 0 the PA is turned of by setting PA 2 0 to 0 For all other PA 2 0 combinations the PA i...

Page 19: ...equency Synthesizer Adr Data A6 A0 D7 D6 D5 D4 D3 D2 D1 D0 0000001 A0_5 0 A0_4 0 A0_3 1 A0_2 1 A0_1 1 A0_0 0 0000010 N0_11 0 N0_10 0 N0_9 0 N0_8 0 0000011 N0_7 0 N0_6 1 N0_5 1 N0_4 1 N0_3 0 N0_2 0 N0_1 1 N0_0 1 0000100 M0_11 0 M0_10 0 M0_9 0 M0_8 0 0000101 M0_7 0 M0_6 0 M0_5 1 M0_4 0 M0_3 0 M0_2 0 M0_1 0 M0_0 1 0000110 A1_5 0 A1_4 1 A1_3 1 A1_2 1 A1_1 1 A1_0 1 0000111 N1_11 0 N1_10 0 N1_9 0 N1_8 0...

Page 20: ...he M N and A values can be calculated from the formula Phase select prescaler Prescaler_Sel 0 31 A N k M f f XCO RF Pulse swallow prescaler Prescaler_Sel 1 2 32 A N k M f f XCO RF where fXCO Crystal oscillator frequency fRF RF frequency 0 A N k 6 RF frequency 290 325 MHz Freq_Band 1 0 0 4 RF frequency 430 490 MHz Freq_Band 1 0 1 2 RF frequency 860 980 MHz Freq_Band 1 0 2 3 There are two sets of ea...

Page 21: ...rnal capacitors are connected and XCOtune 4 0 16 If a crystal requires higher load capacitance additional capacitors must be added off chip C1 and C2 in Figure 9 If XCOtune 4 0 0 the loading capacitors can be calculated by the following formula parasitic L C C C C 2 1 1 1 1 The parasitic capacitance is the pin input capacitance and PCB stray capacitance Typically the total parasitic capacitance is...

Page 22: ...lock this circuit will control the varactor voltage This will be performed if either the VCO_Fr_Chk or VCO_Fr_Auto bit is set VCO_Fr_Chk set will set the interrupts VC_HI in case of a too high VCO_freq setting creating a too high varactor voltage and VC_LO in case of a too low VCO_freq setting creating a too low varactor voltage If the VCO_Fr_Auto bit is set then the transmitter will if the varact...

Page 23: ...be read out bits VCO_Freq_O 2 0 in interrupt register If PLL for some reason cannot obtain lock i e if frequency is set wrongly an interrupt will be given even if VCO_Fr_Chk 0 Table 14 Automatic VCO Range Calibration VCO Tuning Range for Various VCO_Freq Settings 800 0 850 0 900 0 950 0 1000 0 1050 0 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 2 2 2 4 Varactor Voltage V RF frequency MHz 7 6 5 4 3 2 1 0 ...

Page 24: ...or pin capacitance of 10 12pF does not influence on the component values for the two filters with lowest bandwidth For the 12kHz bandwidth filter a third order loop filter is calculated The third pole is set by R2 and C3 Here C3 is chosen to be 12pF the same as the varactor input pin capacitance C3 can therefore be skipped A schematic for a third order loop filter is shown in Figure 11a For a seco...

Page 25: ...ion and c Internal Dual Path Filter Mod Type Freq MHz Baud Rate kbaud sec Coding PLL BW kHz Phase margin Phase detector Freq kHz C1 nF C2 nF R1 kΩ R2 kΩ C3 pF VCO All 30 Manchester 0 8 56 100 10 100 6 2 VCO All 100 Manchester 3 0 56 100 0 68 68 27 Divider 315 20 DC free 17 60 500 0 068 6 8 30 75 12 Divider 433 20 DC free 18 60 500 0 068 6 8 30 75 12 Divider 868 15 DC free 20 51 700 0 082 4 7 27 75...

Page 26: ... 62 5 2 32 4 10 8 3 34 1 20 2 ASK 9 6kbps 2000 220 12 5 125 3 5 4 1 8 0 76 5 5 0 Table 18 Internal Dual Path Filter Settings The design of the PLL filter will strongly affect the performance of the frequency synthesizer Input parameters when designing the loop filter for the MICRF405 are mainly the modulation method and the bit rate Internal loop filter which have relative high bandwidths is recom...

Page 27: ...ulation 1 0 1 modulation is applied directly to the VCO The VCO is now left free running The varactor voltage will now be stored on a large external capacitor connected to the VARIN pin and the PLL is disabled during the modulation With the PLL disabled the modulation will not be canceled and the modulated data signal may include DC components The switching between PLL active and disabled is done ...

Page 28: ...tor frequency ASK Modulation is selected when ASK_en 1 and Modulation 2 0 3 The ASK modulation depth is controlled by the ASK 2 0 bits and is equal to PA 2 0 ASK 2 0 3dB If PA 2 0 ASK 2 0 the ASK modulation will be On Off Keying OOK For example PA 2 0 7 and ASK 2 0 7 is OOK but if ASK 2 0 4 the modulation depth is 9dB output power for 1 is 10dBm and 0 is 1dBm The modulation depth is a tradeoff bet...

Page 29: ...ASK is a combination of traditional ASK combined with FSK dithering This modulation type goes under FCC part 15 247 digital modulation allowing higher output power without FHSS The FSK dithering frequency applied to the ASK signal is greater than the ASK data rate and therefore a traditional ASK OOK receiver with 500kHz noise bandwidth can be used FSK is applied using divider modulation Modulation...

Page 30: ...ction Modulator for details When Manchester encoding is enabled Manchester_en 1 FSKn needs to bigger than zero for the modulator to operate properly When sending ASK with FSK spreading FSKClk_K and FSKn set the speed of the FSK spreading The bit rate of the ASK is set similar with the two parameters ASKClk_K and ASKn The relationship is now ASKn XTAL K ASKClk f BR 5 2 _ 2 where the new parameters ...

Page 31: ...e parameter that controls the signal generation while MOD_A controls attenuation of this signal The reason for using an attenuator is to be able to generate small deviations at high values of FSKClk_K The relationship is shown in equation 4 A MOD DEV I MOD f _ 2 _ 4 Finally the VCO gain is given by equation 5 FreqBand FreqBand f Const Const K C VCO 3 3 2 1 5 where Const1 9 10 6324 30 Const2 7 54 f...

Page 32: ...e frequency This function is enabled when the PA_LDc_en bit is set From power down or stand by simply program the MICRF405 to TX with the wanted PA output setting The MICRF405 will then automatically turn on the PA once the PLL has locked The PA will remain on until PA 2 0 PA_LDc_en 0 or the transmitter leaves transmit mode Mode 1 0 3 However the PA is temporary turned off for every internal load ...

Page 33: ...ver in this mode it is of vital importance that the input power is below 2 5V as the pass devices in the LDOs are fully on and not regulated It is recommended that this option is used in combination with the low battery detector When LDO_en 1 0 0 the power supply range is 2 2 2 5 volt Power must be applied to pin 1 3 9 11 and 23 Capacitors are now only needed for normal noise decoupling Alternativ...

Page 34: ...0001 ASK_PN_en 0 ASK_EN 0 ASKshape2 1 ASKshape1 1 ASKshape0 1 ASK2 1 ASK1 1 ASK0 1 0010010 ASKn1 1 ASKn0 0 ASKClk_K5 1 ASKClk_K4 1 ASKClk_K3 0 ASKClk_K2 1 ASKClk_K1 0 ASKClk_K0 0 0010011 INT_LF_EN 1 CP_CUR1 0 CP_CUR0 1 LF_RES1_4 0 LF_RES1_3 1 LF_RES1_2 0 LF_RES1_1 0 LF_RES1_0 1 0010100 LF_High_PM 1 LF_CAP1 1 LF_CAP0 1 LF_RES3_4 0 LF_RES3_3 0 LF_RES3_2 1 LF_RES3_1 0 LF_RES3_0 1 0010101 ClkOut_1 0 C...

Page 35: ...k Bit_IO_en Sync_en State Comments 0 X DCLK pin on RDY Byte ready RDY signal from databyte 1 0 DCLK pin off Transparent transmission of data 1 1 DCLK pin on DATACLK Bit clock is generated by transmitter Table 23 Synchronizer Mode ASK_EN Modulation1 Modulation0 State Comments 0 0 0 Closed loop VCO modulation VCO is phase locked 0 0 1 Open loop VCO modulation VCO is free running 0 1 0 Modulation by ...

Page 36: ...O load capacitor Table 27 XCO Capacitor Setting XCO_Fast Comments 0 The XCO is running on a constant bias current 1 When going from PD to TX mode the XCO is running on a high current during start up Table 28 XCO Fast Startup Low_Batt_en LowBatt_level LDO_by Comments 0 X X Low battery detect circuit off 1 0 0 Low battery detect circuit active Interrupt is flagged if VDD falls below 2V 1 1 0 Low bat...

Page 37: ...lse or when using openloop modulation and setting the DATAIN pin in tri state PA will be turned on again once LD goes high again LD_en must be set to 1 Table 31 Lock Detect Controlled PA MOD_LDc_en Comments 0 Modulation starts once frame length is written into data byte 1 Modulation starts once frame length is written into data byte and PA is turned on and LD is high Table 32 Lock Detect Controlle...

Page 38: ...ength Table 37 CRC Select Manchester_en Comments 0 Manchester encoding disabled 1 Manchester encoding enabled Data will be encoded before transmitted FSKn 0 when using modulator Table 38 Manchester Encoding only when BIT_IO_en 0 VCO_freq2 VCO_freq1 VCO_freq0 Comments 0 0 0 Not used 0 0 1 0 1 0 868 MHz 433MHz 0 1 1 1 0 0 915 MHz 1 0 1 1 1 0 950MHz 315MHz 1 1 1 Table 39 VCO Frequency MOD_I Comments ...

Page 39: ...y by ASKClk_K 2 5 ASKn Table 45 Bit Rate Setting ASKClk_K Comments 1 63 The crystal oscillator is divided by this number and is divided further down by 2 5 ASKn to produce the ASK bitrate clock Table 46 Modulator and Bit Rate Clock Setting ASK_PN_en Comments 0 01010101 pattern is used in the FSK spreader during ASK 1 111101011001000 repeated pattern is used in the FSK spreader during ASK Table 47 ...

Page 40: ...A bias current setting 1 1 PA bias current setting highest bias current PAB_IB3 PAB_IB2 State 0 0 PAbuffer uses bias current from PTAT bias source external resistor Pin 6 0 1 PAbuffer uses bias current from CI bias source external resistor Pin 24 1 0 PAbuffer uses bias current from internal bias source PTAT 1 1 PAbuffer uses bias current from internal bias source PTAT CI PAB_IB1 PAB_IB0 State 0 0 ...

Page 41: ... 8 105 7 57 1 9 115 9 63 5 10 126 1 69 9 11 136 3 76 3 12 146 5 82 7 13 156 7 89 1 14 166 9 95 5 15 177 1 101 9 16 187 3 108 3 17 197 5 114 7 18 207 7 121 1 19 217 9 127 5 20 228 1 133 9 21 238 3 140 3 22 248 5 146 7 23 258 7 153 0 24 268 9 159 4 25 279 1 165 8 26 289 3 172 2 27 299 5 178 6 28 309 7 185 0 29 319 9 191 4 30 330 1 197 8 31 340 4 204 2 Table 53 Loop Filter Resistor Values ...

Page 42: ...pacitor 0603 10 X7R 16V 55 125 C Kyocera CM105X7R104K16A 7 C12 10nF Capacitor 0603 10 X7R 50V 55 125 C Kyocera CM105X7R103K50A 8 C13 100nF Capacitor 0603 10 X7R 16V 55 125 C Kyocera CM105X7R104K16A 9 C14 100nF Capacitor 0603 10 X7R 16V 55 125 C Kyocera CM105X7R104K16A 10 C16 100nF Capacitor 0603 10 X7R 16V 55 125 C Kyocera CM105X7R104K16A 11 C17 10nF Capacitor 0603 10 X7R 50V 55 125 C Kyocera CM10...

Page 43: ...10NXJB 15 L2 12nH Inductor 0603 5 40 125 C Coilcraft 0603CS 12NXJB 16 Y1 16MHz Crystal TSX 10A 10ppm 20 75 Cl Toyocom TN4 26011 FSK ASK 433MHz Item Part Value Description Manufacturer Part Number 1 C1 See Table 17 2 C2 See Table 17 3 C4 5p6 Capacitor 0603 0 5pF COG 50V 55 125 C Kyocera CM105CG5R6D50A 4 C5 6p8 Capacitor 0603 0 5pF COG 50V 55 85 C Kyocera CM105CG6R8D50A 5 C6 6p8 Capacitor 0603 0 5pF...

Page 44: ...7R104K16A 7 C12 10nF Capacitor 0603 10 X7R 50V 55 125 C Kyocera CM105X7R103K50A 8 C13 100nF Capacitor 0603 10 X7R 16V 55 125 C Kyocera CM105X7R104K16A 9 C14 100nF Capacitor 0603 10 X7R 16V 55 125 C Kyocera CM105X7R104K16A 10 C16 100nF Capacitor 0603 10 X7R 16V 55 125 C Kyocera CM105X7R104K16A 11 C17 10nF Capacitor 0603 10 X7R 50V 55 125 C Kyocera CM105X7R103K50A 12 R1 See Table 17 13 R5 82k Resist...

Page 45: ...Micrel MICRF405 April 2006 45 M9999 041906 408 955 1690 Package Information 24 Lead MLF ML MLF 4 4x4mm Land pattern E X1 Y1 C1 C2 X2 Y2 Min 0 50 0 30 0 70 3 90 3 90 2 55 2 55 ...

Page 46: ...designed or authorized for use as components in life support appliances devices or systems where malfunction of a product can reasonably be expected to result in personal injury Life support devices or systems are devices or systems that a are intended for surgical implant into the body or b support or sustain life and whose failure to perform can be reasonably expected to result in a significant ...

Page 47: ...RF112YMM TR SI4063 C2A GM ADF5901WCCPZ ADF5901ACPZ ADF5902WCCPZ HMC6300BG46 HMC8200LP5ME SX1243IULTRT TDA7100HTMA1 MICRF114T I OT MAX1479ATE MAX2902ETI MAX2903ETI MAX41464GUB MAX7044AKA T MAX1472AKA T MICRF113YM6 TR MAQRF112YMM MICRF102YM MICRF112YMM CMX998Q1 SI4063 B1B FM TDA7110FHTMA1 CC1150RGVR TL851CDR ATA8402C 6AQY 66 MAX7057ASE SQUIDBOARD 868 HORNETPRO 8S1 HORNETPRO 8S3 ATA5757C 6DQY 66 AFE7...

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