NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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Modem SPI Register Descriptions
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 5-29
5.29 RST_Ind - Register 25
The RST_Ind Register 25 contains the reset indicator bit. Bit reset_ind is cleared during a reset and gets
set if Register 25 is read after a reset and remains set. This bit is useful for the MCU to determine if the
transceiver has returned from a Hibernate condition via an ATTN signal or recovered from a reset
condition.
Bit 1 cca — The Clear Channel Assessment bit indicates channel
busy or channel idle.
1 = channel busy detected
0 = channel idle detected
Note: For cca_type[1:0], Register 6, Bits 5:4 =
10, Energy Detect Mode, CCA is not
calculated and cca is held low.
Bit 0 crc_valid — The RX CRC Result bit denotes if the CRC is
correct or not.
1 = RX CRC correct
0 = RX CRC incorrect (default)
Register 25
0x25
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reset_ind
TYPE r r r
RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0000
Table 5-30. Register 25 Description
Name Description Operation
Bits 15-8,
6-0
Reserved
Bit 7 reset_ind — The reset indicator bit shows whether Register 25
was read since the last RST assertion or program reset.
1 = Register 25 has been read since the last RST
or Program Reset event.
0 = Register 25 has not been read since the last
RST or Program Reset event.
Note: Reading Register 25 will set Bit 7.
Table 5-29. Register 24 Description (continued)
Name Description Operation