NXP Semiconductors freescale semiconductor MC13211, Reference Manual

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Modem Timer Information
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 6-3
6.4 Reading Current Time
The current value of the Event Timer can be read via the SPI using et[23:16], Current_Time_A Register
26, Bits 7-0, and et[15:0], Current_Time_B Register 27, Bits 15-0. The “current time” may be obtained
using two single SPI reads, or one recursive 2-word SPI read (or as part of a longer recursive read operation
as well). It is important to realize that the Event Timer may increment during these recursive SPI read
operations, or between successive SPI reads if single SPI reads are used. During such an access, the
MC1321x latches the “current time” to protect the host from obtaining an incorrect value. The “current
time” least significant 16 bits (LSB) are latched when the most significant 8 bits (MSB) SPI location is
read. The LSB is unlatched after the “current time” LSB location is read. This guarantees a stable value
until the host completes a read of both words constituting the “current time” before it is allowed to update.
The preferred procedure to obtain the “current time” value from the MC1321x is to perform a 2-word
recursive read of the “current time” starting at the MSB address.
6.5 Latching the Timestamp
The MC1321x has the ability create a Timestamp or to latch a copy of the “current time” while continuing
to increment its internal counter. This timestamp value latched within the Event Timer corresponds to the
beginning of a receive packet where the actual payload data begins after the FLI has been received. The
timestamp[23:0] (Register 2E, Bits 7-0 and Register 2F, bits 15-0) value is read from the MC1321x by the
host. When timestamp[23:0] is latched, its value corresponds to the “current time” value coincident with
the reception of rx_pkt_latch[6:0], RX_Pkt_Latch Register 2D, Bits 6-0. The timestamp remains latched
until another packet is received, at which point the timestamp[23:0] value is updated and re-latched.
6.6 Event Timer Comparators
The MC1321x incorporates four full 24-bit programmable fields that compare to the Event Timer’s
“current time”. The intent of these compares is to enable the host to schedule events relative to the “current
time”. When a match between the “current time” and any one of the four timer compare values occurs, a
corresponding flag is sent to internal interrupt logic. This causes the appropriate bit in the IRQ_Status
Register 24 to be set, and depending on the interrupt mask control bit, generate an interrupt event on the
IRQ pin.
6.6.1 Timer Compare Fields
There are four 24-bit timer compare fields:
1. tmr_cmp1[23:0], Tmr_Cmp1_A Register 1B, Bits 7-0, and Tmr_Cmp1_B Register 1C, Bits 15-0.
2. tmr_cmp2[23:0], Tmr_Cmp2_A Register 1D, Bits 7-0, and Tmr_Cmp2_B Register 1E, Bits 15-0.
3. tmr_cmp3[23:0], Tmr_Cmp3_A Register 1F, Bits 7-0, and Tmr_Cmp3_B Register 20, Bits 15-0.
4. tmr_cmp4[23:0], Tmr_Cmp4_A Register 21, Bits 7-0, and Tmr_Cmp4_B Register 22, Bits 15-0.
And a special case 16-bit timer compare field for Stream Data Mode:
1. tc2_prime[15:0], TC2_Prime Register 23, Bits 15-0.