NXP Semiconductors freescale semiconductor MC13211, Reference Manual

Page: 296 / 372

MCU Timer/PWM (TPM Module)
MC1321x Reference Manual, Rev. 1.6
17-4 Freescale Semiconductor
and interrupt activity depend on the operating mode, these topics are covered in the associated mode
sections.
17.4.1 Counter
All timer functions are based on the main 16-bit counter (TPM1CNTH:TPM1CNTL). This section
discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overflow, and
manual counter reset.
After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive.
Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the timer counter. The clock source
for each of the TPM can be independently selected to be off, the bus clock (BUSCLK), the fixed system
clock (XCLK), or an external input through the TPM1CH0 pin. The maximum frequency allowed for the
external clock option is one-fourth the bus rate. Refer to
Section 17.6.1, “Timer x Status and Control
Register (TPM1SC)” , and Table 17-2 for more information about clock source selection.
When the microcontroller is in active Background Mode, the TPM temporarily suspends all counting until
the microcontroller returns to normal user operating mode. During Stop Mode, all TPM clocks are stopped;
therefore, the TPM is effectively disabled until clocks resume. During Wait Mode, the TPM continues to
operate normally.
The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1),
the counter operates in Up-/down-counting Mode. Otherwise, the counter operates as a simple up-counter.
As an up-counter, the main 16-bit counter counts from $0000 through its terminal count and then continues
with $0000. The terminal count is $FFFF or a modulus value in TPM1MODH:TPM1MODL.
When center-aligned PWM operation is specified, the counter counts upward from $0000 through its
terminal count and then counts downward to $0000 where it returns to up-counting. Both $0000 and the
terminal count value (value in TPM1MODH:TPM1MODL) are normal length counts (one timer clock
period long).
An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is
a software-accessible indication that the timer counter has overflowed. The enable signal selects between
software polling (TOIE = 0) where no hardware interrupt is generated, or interrupt-driven operation
(TOIE = 1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1.
The conditions that cause TOF to become set depend on the Counting Mode (up or up/down). In
Up-counting Mode, the main 16-bit counter counts from $0000 through $FFFF and overflows to $0000 on
the next counting clock. TOF becomes set at the transition from $FFFF to $0000. When a modulus limit
is set, TOF becomes set at the transition from the value set in the modulus register to $0000. When the
main 16-bit counter is operating in Up-/down-counting Mode, the TOF flag gets set as the counter changes
direction at the transition from the value set in the modulus register and the next lower count value. This
corresponds to the end of a PWM period. (The $0000 count value corresponds to the center of a period.)
Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter
for read operations. Whenever either byte of the counter is read (TPM1CNTH or TPM1CNTL), both bytes
are captured into a buffer so when the other byte is read, the value will represent the other byte of the count
at the time the first byte was read. The counter continues to count normally, but no new value can be read
from either byte until both bytes of the old count have been read.