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Nuvoton NUC126LE4AE, Technical Reference Manual

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Nuvoton NUC126LE4AE Technical Reference Manual Download Page 344

NUC126 

Aug. 08, 2018 

Page 

344

 of 943 

Rev 1.03 

NUC12

6 S

E

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NCE 

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NUA

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6.11  I

2

C Serial Interface Controller (I

2

C) 

6.11.1 

Overview 

I

2

C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange 

between  devices.  The  I

2

C  standard  is  a  true  multi-master  bus  including  collision  detection  and 

arbitration  that  prevents  data  corruption  if  two  or  more  masters  attempt  to  control  the  bus 
simultaneously.  

There are two sets of I

2

C controllers which support Power-down wake-up function.  

6.11.2 

Features 

The I

2

C bus uses two wires (SDA and SCL) to transfer information between devices connected to the 

bus. The main features of the I

2

C bus include: 

 

Supports up to two I

2

C ports 

 

Master/Slave mode 

 

Bidirectional data transfer between masters and slaves 

 

Multi-master bus (no central master) 

 

Arbitration between simultaneously transmitting masters without corruption of serial data 
on the bus 

 

Serial clock synchronization allow devices with different bit rates to communicate via one 
serial bus 

 

Serial clock synchronization used as a handshake mechanism to suspend and resume 
serial transfer

 

 

Built-in 14-bit time-out counter requesting the I

2

C interrupt if the I

2

C bus hangs up and 

timer-out counter overflows 

 

Programmable clocks allow for versatile rate control 

 

Supports 7-bit addressing mode 

 

Supports multiple address recognition ( four slave address with mask option) 

 

Supports Power-down wake-up function 

 

Supports PDMA with one buffer capability 

 

Supports two-level buffer function 

 

Supports setup/hold time programmable 

 

 

Summary of Contents for NUC126LE4AE

Page 1: ...ctual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design Nuvoton assumes no responsibility for errors or omissions All data and specifications are subject to change without notice For additional information or questions please contact Nuv...

Page 2: ...4 2 3 NuMicro NUC126 USB Series LQFP64 Pin Diagram 34 4 2 4 NuMicro NUC126 USB Series LQFP100 Pin Diagram 35 4 3 Pin Description 36 4 3 1 NUC126 USB Series Pin Description 36 4 3 2 GPIO Multi function Pin Summary 53 5 BLOCK DIAGRAM 69 5 1 NuMicro NUC126 Block Diagram 69 6 FUNCTIONAL DESCRIPTION 70 6 1 ARM Cortex M0 Core 70 6 2 System Manager 72 6 2 1 Overview 72 6 2 2 System Reset 72 6 2 3 Power M...

Page 3: ...er Description 230 6 5 Analog Comparator Controller ACMP 247 6 5 1 Overview 247 6 5 2 Features 247 6 5 3 Block Diagram 248 6 5 4 Basic Configuration 249 6 5 5 Functional Description 249 6 5 6 Register Map 254 6 5 7 Register Description 255 6 6 Analog to Digital Converter ADC 262 6 6 1 Overview 262 6 6 2 Features 262 6 6 3 Block Diagram 263 6 6 4 Basic Configuration 263 6 6 5 Functional Description...

Page 4: ...vider HDIV 336 6 10 1Overview 336 6 10 2Features 336 6 10 3Blcok Diagram 336 6 10 4Basic Configuration 336 6 10 5Functional Description 336 6 10 6Register Map 338 6 10 7Register Description 339 6 11 I2 C Serial Interface Controller I2 C 344 6 11 1Overview 344 6 11 2Features 344 6 11 3Block Diagram 345 6 11 4Basic Configuration 345 6 11 5Functional Description 346 6 11 6Register Map 362 6 11 7Regis...

Page 5: ...eatures 546 6 15 3Block Diagram 546 6 15 4Basic Configuration 548 6 15 5Functional Description 549 6 15 6Register Map 559 6 15 7Register Description 560 6 16 Serial Peripheral Interface SPI 586 6 16 1Overview 586 6 16 2Features 586 6 16 3Block Diagram 587 6 16 4Basic Configuration 587 6 16 5Functional Description 589 6 16 6Timing Diagram 602 6 16 7Programming Examples 604 6 16 8Register Map 606 6 ...

Page 6: ...2 6 20 3Block Diagram 742 6 20 4Basic Configuration 743 6 20 5Functional Description 744 6 20 6Register Map 753 6 20 7Register Description 754 6 21 USCI SPI Mode 775 6 21 1Overview 775 6 21 2Features 775 6 21 3Block Diagram 776 6 21 4Basic Configuration 776 6 21 5Functional Description 778 6 21 6Register Map 792 6 21 7Register Description 793 6 22 USCI I2 C Mode 815 6 22 1Overview 815 6 22 2Featur...

Page 7: ...tion 920 6 24 6Register Map 922 6 24 7Register Description 923 6 25 Window Watchdog Timer WWDT 927 6 25 1Overview 927 6 25 2Features 927 6 25 3Block Diagram 927 6 25 4Basic Configuration 928 6 25 5Functional Description 928 6 25 6Register Map 931 6 25 7Register Description 932 7 APPLICATION CIRCUIT 937 8 PACKAGE DIMENSIONS 938 8 1 LQFP 100L 14x14x1 4 mm footprint 2 0 mm 938 8 2 LQFP 64L 7x7x1 4 mm...

Page 8: ...9 SRAM Memory Organization 87 Figure 6 2 10 UART1_TXD Modulated with PWM Channel 88 Figure 6 2 11 VDET Block Diagram 89 Figure 6 3 1 Clock Generator Block Diagram 170 Figure 6 3 2 Clock Generator Global View Diagram 171 Figure 6 3 3 System Clock Block Diagram 172 Figure 6 3 4 HXT Stop Protect Procedure 173 Figure 6 3 5 SysTick Clock Control Block Diagram 173 Figure 6 3 6 Clock Source of Clock Outp...

Page 9: ...n Mode on Enabled Channels Timing Diagram 268 Figure 6 6 6 Continuous Scan Mode on Enabled Channels Timing Diagram 269 Figure 6 6 7 A D Conversion Result Monitor Logic Diagram 270 Figure 6 6 8 A D Controller Interrupt 271 Figure 6 6 9 Conversion Result Mapping Diagram of ADC Single end Input 275 Figure 6 6 10 Conversion Result Mapping Diagram of ADC Differential Input 276 Figure 6 7 1 CRC Generato...

Page 10: ...ng Adjustment 356 Figure 6 11 19 I 2 C Data Shifting Direction 357 Figure 6 11 20 I 2 C Time out Count Block Diagram 359 Figure 6 11 21 I 2 C Wake Up Related Signals Waveform 360 Figure 6 11 22 EEPROM Random Read 361 Figure 6 11 23 Protocol of EEPROM Random Read 361 Figure 6 12 1 PDMA Controller Block Diagram 376 Figure 6 12 2 Descriptor Table Entry Structure 377 Figure 6 12 3 Descriptor Table Ope...

Page 11: ...e 434 Figure 6 13 26 PWMx_CH0 and PWMx_CH1 Output Control in Complementary Mode 435 Figure 6 13 27 Dead Time Insertion 435 Figure 6 13 28 Illustration of Mask Control Waveform 436 Figure 6 13 29 Brake Noise Filter Block Diagram 437 Figure 6 13 30 Brake Block Diagram for PWMx_CH0 and PWMx_CH1 Pair 438 Figure 6 13 31 Edge Detector Waveform for PWMx_CH0 and PWMx_CH1 Pair 439 Figure 6 13 32 Level Dete...

Page 12: ... 6 Automatic Slave Selection SSACTPOL 0 SUSPITV 0x2 592 Figure 6 16 7 Automatic Slave Selection SSACTPOL 0 SUSPITV 0x3 592 Figure 6 16 8 Byte Reorder Function 593 Figure 6 16 9 Timing Waveform for Byte Suspend 593 Figure 6 16 10 SPI Half Duplex Master Mode Application Block Diagram 594 Figure 6 16 11 SPI Half Duplex Slave Mode Application Block Diagram 594 Figure 6 16 12 FIFO Threshold Comparator ...

Page 13: ... Up Count Type 642 Figure 6 17 19 Immediately Loading Mode with Up Count Type 643 Figure 6 17 20 PWM Pulse Generation in Up Down Count Type 643 Figure 6 17 21 PWM 0 to 100 Duty Cycle in Up Count Type and Up Down Count Type 644 Figure 6 17 22 PWM Independent Mode Output Waveform 645 Figure 6 17 23 PWM Complementary Mode Output Waveform 645 Figure 6 17 24 PWMx_CH0 Output Control in Independent Mode ...

Page 14: ...ure 6 20 3 UART Standard Frame Format 746 Figure 6 20 4 UART Bit Timing data sample time 748 Figure 6 20 5 UART Auto Baud Rate Control 749 Figure 6 20 6 Incoming Data Wake Up 750 Figure 6 20 7 nCTS Wake Up Case 1 750 Figure 6 20 8 nCTS Wake Up Case 2 751 Figure 6 21 1 SPI Master Mode Application Block Diagram 775 Figure 6 21 2 SPI Slave Mode Application Block Diagram 775 Figure 6 21 3 USCI SPI Mod...

Page 15: ...ave with a 7 bit address 825 Figure 6 22 11 Master Transmits Data to Slave by 10 bit address 825 Figure 6 22 12 Master Reads Data from Slave by 10 bit address 826 Figure 6 22 13 Master Transmitter Mode Control Flow with 7 bit Address 826 Figure 6 22 14 Master Receiver Mode Control Flow with 7 bit Address 827 Figure 6 22 15 Save Mode Control Flow with 7 bit address 828 Figure 6 22 16 GC Mode with 7...

Page 16: ...nd Parity Format 876 Figure 6 23 21 LIN Sync Field Measurement 878 Figure 6 23 22 UART_BAUD Update Sequence in AR Mode if SLVDUEN is 1 879 Figure 6 23 23 UART_BAUD Update Sequence in AR mode if SLVDUEN is 0 879 Figure 6 23 24 RS 485 nRTS Driving Level in Auto Direction Mode 881 Figure 6 23 25 RS 485 nRTS Driving Level with Software Control 882 Figure 6 23 26 Structure of RS 485 Frame 883 Figure 6 ...

Page 17: ... 1 Relationship between I 2 C Baud Rate and PCLK 356 Table 6 11 2 I 2 C Status Code Description 358 Table 6 12 1 Channel Priority Table 377 Table 6 13 1 PWM System Clock Source Control Registers Setting Table 416 Table 6 13 2 PWM Pulse Generation Event Priority for Up Counter 429 Table 6 13 3 PWM Pulse Generation Event Priority for Down Counter 430 Table 6 13 4 PWM Pulse Generation Event Priority ...

Page 18: ...UART Interface Controller Pin 858 Table 6 23 3 UART Controller Baud Rate Equation Table 860 Table 6 23 4 UART Controller Baud Rate Parameter Setting Example Table 861 Table 6 23 5 UART Controller Baud Rate Register Setting Example Table 861 Table 6 23 6 Baud Rate Compensation Example Table 1 862 Table 6 23 7 Baud Rate Compensation Example Table 2 862 Table 6 23 8 UART Controller Interrupt Source a...

Page 19: ...rom 2 5V to 5 5V and temperature ranging from 40 to 105 up to 256 Kbytes of Flash memory 20 Kbytes of SRAM 4 Kbytes of ISP In System Programming ROM as well as ICP In Circuit Programming ROM and IAP In Application Programming ROM in 48 64 or 100 pin packages It also supports high immunity of 8KV ESD HBM 4KV EFT It is also equipped with plenty of peripherals such as USB interface Timers Watchdog Ti...

Page 20: ...nction Hardware external read protection of whole flash memory by Security Lock Bit Supports 2 wired ICP update through SWD ICE interface SRAM Memory 20 KB embedded SRAM Supports byte half word and word access Supports PDMA mode Hardware Divider Signed two s complement integer calculation 32 bit dividend with 16 bit divisor calculation capacity 32 bit quotient and 32 bit remainder outputs 16 bit r...

Page 21: ...ut selectable I O pin configured as interrupt source with edge level trigger setting Supports high driver and high sink current I O up to 20 mA at 5V Supports software selectable slew rate control Supports up to 81 49 35 GPIOs for LQFP100 64 48 respectively Timer PWM Supports 4 sets of Timers PWM Timer Mode PWM Mode TM_CNT_OUT PWM_CH0 TM_EXT PWM_CH1 Complementary Timer Mode Supports 4 sets of 32 b...

Page 22: ...nute hour and calendar counter day month year Supports Alarm registers second minute hour day month year Supports Alarm mask registers Selectable 12 hour or 24 hour mode Automatic leap year recognition Supports periodic time tick interrupt with 8 period options 1 128 1 64 1 32 1 16 1 8 1 4 1 2 and 1 second Supports wake up function PWM Supports maximum clock frequency up to144MHz Supports up to tw...

Page 23: ... word from 4 to 16 bit Supports MSB first or LSB first transfer sequence Supports Word Suspend function Supports 3 wire no slave select signal bi direction interface Supports wake up function by slave select signal in Slave mode Supports one data channel half duplex transfer I 2 C Mode Full master and slave device capability Supports of 7 bit addressing as well as 10 bit addressing Communication i...

Page 24: ...nd RS 485 Address Match AAD mode wake up function Supports PDMA transfer Smart Card Host SC Supports up to two Smart Card Hosts SC Mode UART Mode SC_DATA Rx SC_CLK Tx SC_CD SC_PWR SC_RST SC Mode Supports up to two ISO 7816 3 ports Compliant to ISO 7816 3 T 0 T 1 Separate receive transmit 4 bytes entry FIFO for data payloads Programmable transmission clock frequency Programmable receiver buffer tri...

Page 25: ...tween masters and slaves Supports multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer Supports 14 bit time ou...

Page 26: ...ure Supports internal reference voltage 2 048V 2 560V 3 072V and 4 096V Supports PDMA transfer Analog Comparator Supports up to 2 rail to rail analog comparators Supports 4 multiplexed I O pins at positive node Supports I O pin and internal voltages at negative node Support selectable internal voltage reference from Band gap VBG Voltage divider source from AVDD and internal reference voltage Suppo...

Page 27: ...V 2 2V Supports Brown out Interrupt and Reset option Low Voltage Reset Threshold voltage levels 2 0 V Power consumption Chip power down current 10 uA with RAM data retention VBAT power domain operating current 1 5 uA Operating Temperature 40 105 Packages All Green package RoHS LQFP 100 pin LQFP 64 pin 7mmx7mm LQFP 48 pin QFN 48 pin ...

Page 28: ...ash Memory Controller FPU Floating point Unit GPIO General Purpose Input Output HCLK The Clock of Advanced High Performance Bus HIRC 22 1184 MHz Internal High Speed RC Oscillator HXT 4 24 MHz External High Speed Crystal Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIN Local Interconnect Network LIRC 10 kHz internal low spe...

Page 29: ...I Serial Peripheral Interface SPS Samples per Second TDES Triple Data Encryption Standard TMR Timer Controller UART Universal Asynchronous Receiver Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 3 1 1 List of Abbreviations ...

Page 30: ...ON 4 1 NuMicro NUC126 Selection Guide 4 1 1 NuMicro NUC126 Naming Rule NUC126X X 4 X E ARM Based 32 bit Microcontroller CPU core Corte M0 Product Line Function 2X USB Line Flash ROM E 128K G 256K Temperature Version A B SRAM Size 4 20K Package type L LQFP 48 7x7mm S LQFP 64 7x7mm V LQFP 100 14x14mm E 40o C 105o C N QFN 48 7x7mm ...

Page 31: ...kage USBD USCI UART SC UART SPI I 2 S I 2 C NUC126NE4AE 128 20 Conf 2 4 35 4 10 1 3 3 2 2 2 9 ch 2 5 QFN 48 NUC126LE4AE 128 20 Conf 2 4 35 4 10 1 3 3 2 2 2 9 ch 2 5 LQFP 48 NUC126LG4AE 256 20 Conf 2 4 35 4 10 1 3 3 2 2 2 9 ch 2 5 LQFP 48 NUC126SE4AE 128 20 Conf 2 4 49 4 12 1 3 3 2 2 2 15 ch 2 5 LQFP 64 NUC126SG4AE 256 20 Conf 2 4 49 4 12 1 3 3 2 2 2 15 ch 2 5 LQFP 64 NUC126VG4AE 256 20 Conf 2 4 81...

Page 32: ... 33 32 31 30 29 28 27 26 25 QFN 48 37 38 39 40 41 42 43 44 45 46 47 48 PB 5 PB 6 PB 7 nRESET PD 0 AV SS PD 1 PD 2 PD 3 V BAT PF 0 PF 1 PE 0 PC 4 PC 3 PC 2 PC 1 PC 0 LDO_CAP VSS PF 4 PF 3 PD 7 PF 2 USB_VDD33_CAP PF 7 USB_D USB_D USB_VBUS V DDIO PE 13 PE 12 PE 11 PE 10 PE 7 ICE_DAT PE 6 ICE_CLK PA 3 PA 2 PA 1 PA 0 VDD AVDD VREF PB 0 PB 1 PB 2 PB 3 PB 4 VDDIO power domain VBAT power domain Top Transp...

Page 33: ... 13 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 PB 5 PB 6 PB 7 nRESET PD 0 AV SS PD 1 PD 2 PD 3 V BAT PF 0 PF 1 PE 0 PC 4 PC 3 PC 2 PC 1 PC 0 LDO_CAP VSS PF 4 PF 3 PD 7 PF 2 USB_VDD33_CAP PF 7 USB_D USB_D USB_VBUS V DDIO PE 13 PE 12 PE 11 PE 10 PE 7 ICE_DAT PE 6 ICE_CLK PA 3 PA 2 PA 1 PA 0 VDD AVDD VREF PB 0 PB 1 PB 2 PB 3 PB 4 VDDIO power domain VBAT power domain Figur...

Page 34: ... 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PB 15 PB 5 PB 6 PB 7 nRESET PD 0 AV SS PD 8 PD 9 PD 1 PD 2 PD 3 V BAT PF 0 PF 1 PF 2 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 LDO_CAP VDD VSS PF 4 PF 3 PD 7 PD 15 PD 14 PD 13 PD 12 USB_VDD33_CAP PF 7 USB_D USB_D USB_VBUS V DDIO PE 13 PE 12 PE 11 PE 10 PE 9 PE 8 PE 7 ICE_DAT PE 6 ICE_CLK PC 7 PC 6 PA 3 PA 2 PA 1 PA 0 VSS VDD AVDD VREF PB 0 PB 1 PB 2 PB...

Page 35: ...8 99 100 PB 13 PB 14 PB 15 PB 5 PB 6 PB 7 nRESET PD 0 AV SS V DD V SS PC 8 PD 8 PD 9 PD 1 PD 2 PD 3 PD 4 PD 5 PE 3 PD 6 V BAT PF 0 PF 1 PF 2 PC 5 PE 0 PC 4 PC 3 PC 2 PC 1 PC 0 PC 14 PC 13 PC 12 PC 11 PC 10 PC 9 LDO_CAP VDD VSS PF 4 PF 3 PD 7 PD 15 PD 14 PD 13 PD 12 PD 11 PD 10 USB_D USB_D USB_VBUS V DDIO PE 13 PE 12 PE 11 PE 10 PE 9 PE 8 PE 1 V DD V SS PA 4 PA 5 PA 6 PA 7 PA 9 PA 8 PE 7 ICE_DAT PE...

Page 36: ... EBI chip select 1 output pin 1 2 4 PB 5 I O MFP0 General purpose digital I O pin ADC0_CH13 A MFP1 ADC0 channel 13 analog input SPI0_MOSI I O MFP2 SPI0 MOSI Master Out Slave In pin SPI1_MOSI I O MFP3 SPI1 MOSI Master Out Slave In pin ACMP0_P2 A MFP5 Analog comparator 0 positive input 2 pin SC1_RST O MFP6 Smart Card 1 reset pin EBI_AD6 I O MFP7 EBI address data bus bit 6 UART2_RXD I MFP9 UART2 data...

Page 37: ... A MFP5 Analog comparator 1 negative input pin SC1_CLK O MFP6 Smart Card 1 clock pin INT3 I MFP8 External interrupt 3 input pin 6 7 9 AVSS P MFP0 Ground pin for analog circuit 10 VDD P MFP0 Power supply for I O ports and LDO source for internal PLL and digital circuit 11 VSS P MFP0 Ground pin for digital circuit 12 PC 8 I O MFP0 General purpose digital I O pin ADC0_CH16 A MFP1 ADC0 channel 16 anal...

Page 38: ...ose digital I O pin ADC0_ST I MFP1 ADC0 external trigger input pin TM0_EXT I O MFP3 Timer0 external capture input toggle output pin USCI2_DAT0 I O MFP4 USCI2 data 0 pin ACMP1_P1 A MFP5 Analog comparator 1 positive input 1 pin PWM0_BRAKE0 I MFP6 PWM0 Brake 0 input pin EBI_nWR O MFP7 EBI write enable output pin INT0 I MFP8 External interrupt 0 input pin 9 12 17 PD 3 I O MFP0 General purpose digital ...

Page 39: ...pin UART2_RXD I MFP4 UART2 data receiver input pin PWM0_CH3 I O MFP6 PWM0 channel 3 output capture input 21 PD 6 I O MFP0 General purpose digital I O pin CLKO O MFP1 Clock Out SPI1_SS I O MFP2 SPI1 slave select pin UART0_RXD I MFP3 UART0 data receiver input pin UART2_TXD O MFP4 UART2 data transmitter output pin ACMP0_O O MFP5 Analog comparator 0 output pin PWM0_CH5 I O MFP6 PWM0 channel 5 output c...

Page 40: ...UART0_TXD O MFP3 UART0 data transmitter output pin PWM1_CH0 I O MFP6 PWM1 channel 0 output capture input EBI_ADR16 O MFP7 EBI address bus bit 16 18 29 PD 13 I O MFP0 General purpose digital I O pin USCI1_DAT1 I O MFP1 USCI1 data 1 pin SPI1_MOSI I O MFP2 SPI1 MOSI Master Out Slave In pin UART0_RXD I MFP3 UART0 data receiver input pin PWM1_CH1 I O MFP6 PWM1 channel 1 output capture input EBI_ADR17 O...

Page 41: ... pin I2C1_SCL I O MFP3 I2C1 clock pin 16 23 34 PF 4 I O MFP0 General purpose digital I O pin XT1_IN I MFP1 External 4 24 MHz high speed crystal input pin I2C1_SDA I O MFP3 I2C1 data input output pin 17 24 35 VSS P MFP0 Ground pin for digital circuit 25 36 VDD P MFP0 Power supply for I O ports and LDO source for internal PLL and digital circuit 18 26 37 LDO_CAP A MFP0 LDO output pin 38 PC 9 I O MFP...

Page 42: ...ure input 19 27 44 PC 0 I O MFP0 General purpose digital I O pin SC0_DAT I O MFP1 Smart Card 0 data pin SPI0_CLK I O MFP2 SPI0 serial clock pin UART2_nCTS I MFP3 UART2 clear to Send input pin USCI0_DAT0 I O MFP4 USCI0 data 0 pin ACMP0_WLAT I MFP5 Analog comparator 0 window latch input pin PWM0_CH0 I O MFP6 PWM0 channel 0 output capture input EBI_AD8 I O MFP7 EBI address data bus bit 8 INT2 I MFP8 ...

Page 43: ...I_AD11 I O MFP7 EBI address data bus bit 11 23 31 48 PC 4 I O MFP0 General purpose digital I O pin SC0_nCD I MFP1 Smart Card 0 card detect pin SPI0_MISO I O MFP2 SPI0 MISO Master In Slave Out pin I2C1_SCL I O MFP3 I2C1 clock pin USCI0_CLK I O MFP5 USCI0 clock pin PWM0_CH4 I O MFP6 PWM0 channel 4 output capture input EBI_AD12 I O MFP7 EBI address data bus bit 12 24 49 PE 0 I O MFP0 General purpose ...

Page 44: ...t EBI_AD15 I O MFP7 EBI address data bus bit 15 53 PE 4 I O MFP0 General purpose digital I O pin I2C0_SCL I O MFP2 I2C0 clock pin I2C1_SCL I O MFP3 I2C1 clock pin USCI0_CTL0 I O MFP4 USCI0 control 0 pin SC0_PWR O MFP5 Smart Card 0 power pin PWM1_BRAKE0 I MFP6 PWM1 Brake 0 input pin EBI_nCS0 O MFP7 EBI chip select 0 output pin INT0 I MFP8 External interrupt 0 input pin 54 PE 5 I O MFP0 General purp...

Page 45: ... pin TM1 I O MFP8 Timer1 event counter input toggle output pin 58 PA 9 I O MFP0 General purpose digital I O pin SPI1_I2SMCLK I O MFP1 SPI1 I2S master clock output pin I2C1_SDA I O MFP2 I2C1 data input output pin UART1_RXD I MFP3 UART1 data receiver input pin SC0_RST O MFP4 Smart Card 0 reset pin SC1_PWR O MFP5 Smart Card 1 power pin TM_BRAKE1 I MFP6 TM_BRAKE1 I Timer Brake input pin PWM1_BRAKE1 I ...

Page 46: ...y for I O ports and LDO source for internal PLL and digital circuit 65 PE 1 I O MFP0 General purpose digital I O pin TM3_EXT I O MFP3 Timer3 external capture input toggle output pin SC0_nCD I MFP5 Smart Card 0 card detect pin PWM0_CH1 I O MFP6 PWM0 channel 1 output capture input 37 66 PE 8 I O MFP0 General purpose digital I O pin UART1_TXD O MFP1 UART1 data transmitter output pin TM0 I O MFP3 Time...

Page 47: ...output pin 29 41 70 PE 12 I O MFP0 General purpose digital I O pin SPI1_SS I O MFP1 SPI1 slave select pin SPI0_SS I O MFP2 SPI0 slave select pin UART1_TXD O MFP3 UART1 data transmitter output pin I2C0_SCL I O MFP4 I2C0 clock pin SPI1_MOSI I O MFP6 SPI1 MOSI Master Out Slave In pin EBI_AD5 I O MFP7 EBI address data bus bit 5 TM2_EXT I O MFP8 Timer2 external capture input toggle output pin 30 42 71 ...

Page 48: ... EBI address data bus bit 3 USCI1_CLK I O MFP8 USCI1 clock pin 38 50 80 PA 2 I O MFP0 General purpose digital I O pin UART0_TXD O MFP2 UART0 data transmitter output pin UART0_nCTS I MFP3 UART0 clear to Send input pin I2C0_SDA I O MFP4 I2C0 data input output pin SC0_RST O MFP5 Smart Card 0 reset pin PWM1_CH3 I O MFP6 PWM1 channel 3 output capture input EBI_AD2 I O MFP7 EBI address data bus bit 2 US...

Page 49: ...ta transmitter output pin TM_BRAKE3 I MFP6 TM_BRAKE3 I Timer Brake input pin 85 PA 14 I O MFP0 General purpose digital I O pin UART2_nCTS I MFP3 UART2 clear to Send input pin USCI1_CTL1 I O MFP4 USCI1 control 1 pin TM2 I O MFP6 Timer2 event counter input toggle output pin 86 PA 15 I O MFP0 General purpose digital I O pin UART2_nRTS O MFP3 UART2 request to Send output pin USCI1_CLK I O MFP4 USCI1 c...

Page 50: ... pin PWM0_SYNC_OUT O MFP6 PWM0 counter synchronous trigger output pin EBI_nWRH O MFP7 EBI high byte write enable output pin USCI1_DAT1 I O MFP8 USCI1 data 1 pin 46 59 93 PB 2 I O MFP0 General purpose digital I O pin ADC0_CH2 A MFP1 ADC0 channel 2 analog input SPI0_CLK I O MFP2 SPI0 serial clock pin SPI1_CLK I O MFP3 SPI1 serial clock pin UART1_RXD I MFP4 UART1 data receiver input pin SC0_nCD I MFP...

Page 51: ...MFP9 UART2 data receiver input pin TM1_EXT I O MFP10 Timer1 external capture input toggle output pin 62 96 PB 8 I O MFP0 General purpose digital I O pin ADC0_CH5 A MFP1 ADC0 channel 5 analog input UART1_nRTS O MFP4 UART1 request to Send output pin TM_BRAKE2 I MFP5 TM_BRAKE2 I Timer Brake input pin PWM0_CH2 I O MFP6 PWM0 channel 2 output capture input USCI0_CTL0 I O MFP8 USCI0 control 0 pin 97 PB 9...

Page 52: ...2018 Page 52 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 48 Pin 64 Pin 100 Pin Pin Name Type MFP Description PWM0_CH2 I O MFP6 PWM0 channel 2 output capture input USCI0_CTL0 I O MFP8 USCI0 control 0 pin ...

Page 53: ...purpose digital I O pin UART1_nRTS O MFP1 UART1 request to Send output pin UART1_RXD I MFP3 UART1 data receiver input pin USCI1_CTL1 I O MFP4 USCI1 control 1 pin SC0_DAT I O MFP5 Smart Card 0 data pin PWM1_CH4 I O MFP6 PWM1 channel 4 output capture input EBI_AD1 I O MFP7 EBI address data bus bit 1 PA 2 PA 2 I O MFP0 General purpose digital I O pin UART0_TXD O MFP2 UART0 data transmitter output pin...

Page 54: ...eneral purpose digital I O pin SPI1_MISO I O MFP2 SPI1 MISO Master In Slave Out pin TM1_EXT I O MFP3 Timer1 external capture input toggle output pin TM_BRAKE2 I MFP6 TM_BRAKE2 I Timer Brake input pin EBI_AD6 I O MFP7 EBI address data bus bit 6 PA 7 PA 7 I O MFP0 General purpose digital I O pin SPI1_CLK I O MFP2 SPI1 serial clock pin TM0_EXT I O MFP3 Timer0 external capture input toggle output pin ...

Page 55: ...CLK O MFP5 Smart Card 1 clock pin PA 12 PA 12 I O MFP0 General purpose digital I O pin SPI1_I2SMCLK I O MFP2 SPI1 I 2 S master clock output pin UART2_RXD I MFP3 UART2 data receiver input pin UART1_RXD I MFP4 UART1 data receiver input pin TM_BRAKE2 I MFP6 TM_BRAKE2 I Timer Brake input pin PA 13 PA 13 I O MFP0 General purpose digital I O pin UART2_TXD O MFP3 UART2 data transmitter output pin UART1_T...

Page 56: ...counter input toggle output pin SC0_RST O MFP5 Smart Card 0 reset pin PWM0_SYNC_OUT O MFP6 PWM0 counter synchronous trigger output pin EBI_nWRH O MFP7 EBI high byte write enable output pin USCI1_DAT1 I O MFP8 USCI1 data 1 pin PB 2 PB 2 I O MFP0 General purpose digital I O pin ADC0_CH2 A MFP1 ADC0 channel 2 analog input SPI0_CLK I O MFP2 SPI0 serial clock pin SPI1_CLK I O MFP3 SPI1 serial clock pin...

Page 57: ...D I MFP9 UART2 data receiver input pin TM1_EXT I O MFP10 Timer1 external capture input toggle output pin PB 5 PB 5 I O MFP0 General purpose digital I O pin ADC0_CH13 A MFP1 ADC0 channel 13 analog input SPI0_MOSI I O MFP2 SPI0 MOSI Master Out Slave In pin SPI1_MOSI I O MFP3 SPI1 MOSI Master Out Slave In pin ACMP0_P2 A MFP5 Analog comparator 0 positive input 2 pin SC1_RST O MFP6 Smart Card 1 reset p...

Page 58: ... pin ADC0_CH6 A MFP1 ADC0 channel 6 analog input USCI0_CLK I O MFP8 USCI0 clock pin PB 10 PB 10 I O MFP0 General purpose digital I O pin ADC0_CH7 A MFP1 ADC0 channel 7 analog input PB 11 PB 11 I O MFP0 General purpose digital I O pin ADC0_CH8 A MFP1 ADC0 channel 8 analog input PB 12 PB 12 I O MFP0 General purpose digital I O pin PWM1_CH1 I O MFP6 PWM1 channel 1 output capture input PB 13 PB 13 I O...

Page 59: ...t capture input EBI_AD9 I O MFP7 EBI address data bus bit 9 PC 2 PC 2 I O MFP0 General purpose digital I O pin SC0_RST O MFP1 Smart Card 0 reset pin SPI0_SS I O MFP2 SPI0 slave select pin UART2_TXD O MFP3 UART2 data transmitter output pin USCI0_CTL1 I O MFP4 USCI0 control 1 pin ACMP1_O O MFP5 Analog comparator 1 output pin PWM0_CH2 I O MFP6 PWM0 channel 2 output capture input EBI_AD10 I O MFP7 EBI...

Page 60: ..._CH0 I O MFP6 PWM1 channel 0 output capture input EBI_AD14 I O MFP7 EBI address data bus bit 14 PC 7 PC 7 I O MFP0 General purpose digital I O pin USCI0_CTL1 I O MFP4 USCI0 control 1 pin PWM1_CH1 I O MFP6 PWM1 channel 1 output capture input EBI_AD15 I O MFP7 EBI address data bus bit 15 PC 8 PC 8 I O MFP0 General purpose digital I O pin ADC0_CH16 A MFP1 ADC0 channel 16 analog input UART0_nRTS O MFP...

Page 61: ... I O MFP6 PWM1 channel 5 output capture input PC 15 PC 15 I O MFP0 General purpose digital I O pin PWM1_CH0 I O MFP6 PWM1 channel 0 output capture input PD 0 PD 0 I O MFP0 General purpose digital I O pin SPI0_I2SMCLK I O MFP1 SPI0 I 2 S master clock output pin SPI1_I2SMCLK I O MFP2 SPI1 I 2 S master clock output pin UART0_RXD I MFP3 UART0 data receiver input pin USCI2_CTL0 I O MFP4 USCI2 control 0...

Page 62: ...toggle output pin USCI2_DAT1 I O MFP4 USCI2 data 1 pin ACMP1_P0 A MFP5 Analog comparator 1 positive input 0 pin PWM0_BRAKE1 I MFP6 PWM0 Brake 1 input pin EBI_MCLK O MFP7 EBI external clock output pin INT1 I MFP8 External interrupt 1 input pin PD 4 PD 4 I O MFP0 General purpose digital I O pin SPI1_CLK I O MFP2 SPI1 serial clock pin I2C0_SDA I O MFP3 I 2 C0 data input output pin UART2_nRTS O MFP4 U...

Page 63: ...apture input EBI_nRD O MFP7 EBI read enable output pin PD 8 PD 8 I O MFP0 General purpose digital I O pin ADC0_CH17 A MFP1 ADC0 channel 17 analog input UART0_nCTS I MFP3 UART0 clear to Send input pin USCI2_CTL1 I O MFP4 USCI2 control 1 pin TM2 I O MFP6 Timer2 event counter input toggle output pin EBI_nCS0 O MFP7 EBI chip select 0 output pin PD 9 PD 9 I O MFP0 General purpose digital I O pin ADC0_C...

Page 64: ...t 17 PD 14 PD 14 I O MFP0 General purpose digital I O pin USCI1_DAT0 I O MFP1 USCI1 data 0 pin SPI1_MISO I O MFP2 SPI1 MISO Master In Slave Out pin UART0_nCTS I MFP3 UART0 clear to Send input pin PWM1_CH2 I O MFP6 PWM1 channel 2 output capture input EBI_ADR18 O MFP7 EBI address bus bit 18 PD 15 PD 15 I O MFP0 General purpose digital I O pin USCI1_CLK I O MFP1 USCI1 clock pin SPI1_CLK I O MFP2 SPI1...

Page 65: ...gital I O pin SPI1_MOSI I O MFP2 SPI1 MOSI Master Out Slave In pin UART2_RXD I MFP4 UART2 data receiver input pin PWM0_CH3 I O MFP6 PWM0 channel 3 output capture input PE 4 PE 4 I O MFP0 General purpose digital I O pin I2C0_SCL I O MFP2 I 2 C0 clock pin I2C1_SCL I O MFP3 I 2 C1 clock pin USCI0_CTL0 I O MFP4 USCI0 control 0 pin SC0_PWR O MFP5 Smart Card 0 power pin PWM1_BRAKE0 I MFP6 PWM1 Brake 0 i...

Page 66: ...T1_RXD I MFP1 UART1 data receiver input pin TM1 I O MFP3 Timer1 event counter input toggle output pin I2C1_SDA I O MFP4 I 2 C1 data input output pin SC0_RST O MFP5 Smart Card 0 reset pin PE 10 PE 10 I O MFP0 General purpose digital I O pin SPI1_MISO I O MFP1 SPI1 MISO Master In Slave Out pin SPI0_MISO I O MFP2 SPI0 MISO Master In Slave Out pin UART1_nCTS I MFP3 UART1 clear to Send input pin SC0_DA...

Page 67: ...ta receiver input pin I2C0_SDA I O MFP4 I 2 C0 data input output pin SPI1_SS I O MFP6 SPI1 slave select pin EBI_AD4 I O MFP7 EBI address data bus bit 4 TM3_EXT I O MFP8 Timer3 external capture input toggle output pin PF 0 PF 0 I O MFP0 General purpose digital I O pin X32_OUT O MFP1 External 32 768 kHz crystal output pin USCI2_CTL1 I O MFP5 USCI2 control 1 pin INT5 I MFP8 External interrupt 5 input...

Page 68: ...FP3 I 2 C1 data input output pin PF 5 PF 5 I O MFP0 General purpose digital I O pin TM3_EXT I O MFP3 Timer3 external capture input toggle output pin SC1_nCD I MFP5 Smart Card 1 card detect pin TM_BRAKE0 I MFP6 TM_BRAKE0 I Timer Brake input pin PF 6 PF 6 I O MFP0 General purpose digital I O pin PF 7 PF 7 I O MFP0 General purpose digital I O pin Table 4 3 1 NUC126 GPIO Multi function Table ...

Page 69: ... 768 kHz Low Speed Oscillator LIRC 10 kHz PLL Analog Comparator x 2 AHB Bus APB Bus Bridge High Speed Crystal Osc HXT 4 24 MHz RTC PWM Timer I O Ports General Purpose I O External Bus Interface External Interrupt Connectivity UART x 3 VREF 2 048V 2 56V 3 072V 4 96V High Speed Oscillator 48 MHz RTC VBAT LDROM 4 KB DataFlash Configurable SRAM 20 KB SPROM 2 KB Speed Up PDMA 5ch Hard Divider CRC Watch...

Page 70: ...ce Bus matrix Debug Access Port DAP Debug Cortex M0 Processor Cortex M0 Components Wakeup Interrupt Controller WIC Interrupts Serial Wire or JTAG debug port AHB Lite interface Figure 6 1 1 Functional Block Diagram The implemented device provides A low gate count processor ARMv6 M Thumb instruction set Thumb 2 technology ARMv6 M compliant 24 bit SysTick timer A 32 bit hardware multiplier System int...

Page 71: ...t Controller WIC and providing Ultra low Power Sleep mode Debug support Four hardware breakpoints Two watchpoints Program Counter Sampling Register PCSR for non intrusive code profiling Single step and vector catch capabilities Bus interfaces Single 32 bit AMBA 3 AHB Lite system interface that provides simple integration to all system peripherals and memory Single 32 bit slave port that supports t...

Page 72: ...rol register 6 2 2 System Reset The system reset can be issued by one of the events listed below These reset event flags can be read from SYS_RSTSTS register to determine the reset source Hardware reset sourcces are from peripheral signals Software reset can trigger reset through setting control registers Hardware Reset Sources Power on Reset POR Low level on the nRESET pin Watchdog Time out Reset...

Page 73: ...t 50k ohm 5v Reset Pulse Width 2 system clocks nRESET VDD AVDD CHIP Reset CHIPRST SYS_IPRST0 0 CPU Reset CPURST SYS_IPRST0 1 CPU Lockup Reset MCU Reset SYSRSTREQ AIRCR 2 LVREN SYS_BODCTL 7 BODRSTEN SYS_BODCTL 3 POROFF SYS_PORCTL 15 0 Reset Pulse Width 64 WDT clocks Reset Pulse Width 2 system clocks Glitch Filter 36 us Software Reset Reset Controller Figure 6 2 1 System Reset Sources ...

Page 74: ...om CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 BODVL SYS_BODCTL 2 1 BODRSTEN SYS_BODCTL 3 HXTEN CLK_PWRCTL 0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 LXTEN CLK_PWRCTL 1 0x0 WDTCKEN CLK_APBCLK0 0 0x1 0x1 0x1 HCLKSEL CLK_CLKSEL0 2 0 Reload from CONFIG0 Reload...

Page 75: ...NFIG0 Reload from CONFIG0 Reload from CONFIG0 VECMAP FMC_ISPSTS 23 9 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Other Peripheral Registers Reset Value FMC Registers Reset Value Note means that the value of register keeps original setting Table 6 2 1 Reset Value of Registers 6 2 2 1 nRESET Reset The nRESE...

Page 76: ... the power on reset waveform VDD VPOR Power on Reset 0 1V Figure 6 2 3 Power on Reset POR Waveform 6 2 2 3 Low Voltage Reset LVR If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN SYS_BODCTL 7 to 1 after 200us delay LVR detection circuit will be stable and the LVR function will be active Then LVR function will detect AVDD during system operation When the...

Page 77: ...oltage is lower than VBOD which is decided by BODEN SYS_BODCTL 0 and BODVL SYS_BODCTL 2 1 and the state keeps longer than De glitch time set by BODDGSEL SYS_BODCTL 10 8 chip will be reset The BOD reset will control the chip in reset state until the AVDD voltage rises above VBOD and the state keeps longer than De glitch time set by BODDGSEL SYS_BODCTL 10 8 The default value of BODEN BODVL and BODRS...

Page 78: ...andle the failure of MCU after watchdog time out reset by checking WDTRF SYS_RSTSTS 2 6 2 2 6 CPU Lockup Reset CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate indication of seriously errant kernel software This is the result of the CPU being locked because of an unrecoverable exception following the activation of the processor s built in system s...

Page 79: ...ower Mode Normal Mode Idle Mode Power Down Mode Definition CPU is in active state CPU is in sleep state CPU is in sleep state and all clocks stop except LXT and LIRC SRAM content retended Entry Condition Chip is in normal mode after system reset released CPU executes WFI instruction CPU sets sleep mode enable and power down enable and executes WFI instruction Wake up Sources N A All interrupts RTC...

Page 80: ... OFF depends on SW setting in normal mode 2 LIRC 10 kHz OSC ON or OFF depends on S W setting in normal mode 3 If TIMER clock source is selected as LIRC LXT and LIRC LXT is on 4 If WDT clock source is selected as LIRC and LIRC is on 5 If RTC clock source is selected as LXT and LXT is on 6 If UART clock source is selected as LXT and LXT is on Normal Mode Idle Mode Power Down Mode HXT 4 20 MHz XTL ON...

Page 81: ...errupt After software writes 1 to clear EBODIF SYS_BODCTL 19 GPIO GPIO Interrupt After software write 1 to clear the Px_INTSRC n bit TIMER Timer Interrupt After software writes 1 to clear TWKF TIMERx_INTSTS 1 and TIF TIMERx_INTSTS 0 WDT WDT Interrupt After software writes 1 to clear WKF WDT_CTL 5 Write Protect RTC Alarm Interrupt After software writes 1 to clear ALMIF RTC_INTSTS 0 Time Tick Interr...

Page 82: ...r distribution is divided into four segments Analog power from AVDD and AVSS provides the power for analog components operation The VREF should be connected with an external 1uF capacitor that should be located close to the VREF pin to avoid power noise for analog applications Digital power from VDD and VSS supplies the power to the internal regulator which provides a fixed 1 8 V power for digital...

Page 83: ...RTC Power On Control X32_IN PF 1 X32_OUT PF 0 V REF XT1_OUT XT1_IN 1 8V 3 3V USB_VDD33_CAP 1uF VDDIO IO Cell PE 8 PE 13 VBAT to 1 8V LDO IO Cell Brown out Detector Low Voltage Reset 12 bit ADC Internal Reference Voltage Analog Comparator PF 2 1uF 22 1184 MHz HIRC Oscillator 10 kHz LIRC Oscillator SRAM PLL POR18 Temperature Sensor Digital Logic Flash 1 8V LDO_CAP 1uF 48 MHz HIRC48 Oscillator Figure...

Page 84: ...200 0x5000_02FF CLK_BA Clock Control Registers 0x5000_0300 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers 0x5000_4000 0x5000_7FFF GPIO_BA GPIO Control Registers 0x5000_8000 0x5000_BFFF PDMA_BA Peripheral DMA Control Registers 0x5000_C000 0x5000_FFFF FMC_BA Flash Memory Control Registers 0x5001_0000 0x5001_03FF EBI_BA EBI Control Registers 0x5001_4000 0x5001_7FFF HDIV_BA Hardware Divide...

Page 85: ...A PWM1 Control Registers 0x4014_4000 0x4014_7FFF Reserved Reserved 0x4015_0000 0x4015_3FFF UART1_BA UART1 Control Registers 0x4015_4000 0x4015_7FFF UART2_BA UART2 Control Registers 0x4017_0000 0x4017_3FFF USCI1_BA USCI1 Control Registers 0x4017_4000 0x4017_7FFF Reserved Reserved 0x4019_0000 0x4019_3FFF SC0_BA SC0 Control Registers 0x4019_4000 0x4019_7FFF SC1_BA SC1 Control Registers 0x401A_0000 0x...

Page 86: ...rd write Supports oversize response error AHB Bus SRAM bank SRAM decoder AHB interface controller Figure 6 2 8 SRAM Block Diagram Figure 6 2 9 shows the SRAM organization of NUC126 There is one SRAM bank in the NUC126 and addressed to 20 Kbytes The address space is from 0x2000_0000 to 0x2000_4FFF The address between 0x2000_5000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault i...

Page 87: ...disable sequence needs to be followed by a special programming The register protection disable sequence is writing the data 59h 16h 88h to the register SYS_REGLCTL address at 0x5000_0100 continuously Any different data value different sequence or any other write to other address during these three data writing will abort the whole sequence After the protection is disabled user can check the protec...

Page 88: ...ulation loop and RETRYCNT SYS_IRCTCTL 7 6 trim value update limitation count to 11 Another example is that the system needs an accurate 48 MHz clock for USB application In such case if neither using use PLL as the system clock source nor soldering 32 768 kHz crystal in system user has to set REFCKSEL SYS_IRCTCTL1 10 reference clock selection to 1 set FREQSEL SYS_IRCTCTL1 1 0 trim frequency selecti...

Page 89: ...n control Bandgap active interval and comparator active interval to achieve low power detection purpose There is no debounce function in Power down mode since no HCLK available in Power down mode Bandgap 0 1 1 2V VDETPINSEL SYS_BODCTL 17 VDET_ P0 VDET_ P1 VDETOUT SYS_BODCTL 24 VDETEN SYS_BODCTL 16 De glitch VDETDGSEL SYS_BODCTL 27 25 VDETEN SYS_BODCTL 16 Figure 6 2 11 VDET Block Diagram ...

Page 90: ...0 SYS_GPB_MFPL SYS_BA 0x38 R W GPIOB Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPB_MFPH SYS_BA 0x3C R W GPIOB High Byte Multiple Function Control Register 0x0000_0000 SYS_GPC_MFPL SYS_BA 0x40 R W GPIOC Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPC_MFPH SYS_BA 0x44 R W GPIOC High Byte Multiple Function Control Register 0x0000_0000 SYS_GPD_MFPL SYS_BA 0x48 R W GPI...

Page 91: ... SERIES TECHNICAL REFERENCE MANUAL SYS_IRCTCTL1 SYS_BA 0x90 R W HIRC1 Trim Control Register 0x0000_0400 SYS_REGLCTL SYS_BA 0x100 R W Register Lock Control Register 0x0000_0000 SYS_TSOFFSET SYS_BA 0x114 R Temperature Sensor Offset Register 0x0000_0XXX ...

Page 92: ...umber has a unique default reset value 31 30 29 28 27 26 25 24 PDID 31 24 23 22 21 20 19 18 17 16 PDID 23 16 15 14 13 12 11 10 9 8 PDID 15 8 7 6 5 4 3 2 1 0 PDID 7 0 Bits Description 31 0 PDID Part Device Identification Number Read Only This register reflects device part number code Software can read this register to identify which device is used NUC126 USB Series Part Number PDID NUC126VG4AE 0x00...

Page 93: ...t from CPU lockup happened 1 The Cortex M0 lockup happened and chip is reset Note This bit can be cleared by software writing 1 7 CPURF CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST SYS_IPRST0 1 1 to reset Cortex M0 Core and Flash Memory Controller FMC 0 No reset from CPU 1 The Cortex M0 Core and FMC are reset by software setting CPURST to 1 Note This bit can be cl...

Page 94: ...tchdog timer or window watchdog timer 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system Note1 This bit can be cleared by software writing 1 Note2 Watchdog Timer register RSTF WDT_CTL 2 bit is set if the system has been reset by WDT time out reset Window Watchdog Timer register WWDTRF WWDT_STATUS 1 bit is set if the system has been reset by WWDT time out ...

Page 95: ... HDIVRST HDIV Controller Reset Write Protect Set this bit to 1 will generate a reset signal to the HDIV controller User needs to set this bit to 0 to release from the reset state 0 HDIV controller normal operation 1 HDIV controller reset Note This bit is write protected Refer to the SYS_REGLCTL register 3 EBIRST EBI Controller Reset Write Protect Set this bit to 1 will generate a reset signal to t...

Page 96: ...hot Reset Write Protect Setting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles The CHIPRST is same as the POR reset all the chip controllers is reset and the chip setting from flash are also reload About the difference between CHIPRST and SYSRESETREQ AIRCR 2 please refer to section 6 2 2 0 Chip no...

Page 97: ...I0RST Reserved I2C1RST I2C0RST 7 6 5 4 3 2 1 0 Reserved TMR3RST TMR2RST TMR1RST TMR0RST GPIORST Reserved Bits Description 31 29 Reserved Reserved 28 ADCRST ADC Controller Reset 0 ADC controller normal operation 1 ADC controller reset 27 USBDRST USB Device Controller Reset 0 USB device controller normal operation 1 USB device controller reset 26 23 Reserved Reserved 22 ACMP01RST ACMP01 Controller R...

Page 98: ...0 I2C1 controller normal operation 1 I2C1 controller reset 8 I2C0RST I2C0 Controller Reset 0 I2C0 controller normal operation 1 I2C0 controller reset 7 6 Reserved Reserved 5 TMR3RST Timer3 Controller Reset 0 Timer3 controller normal operation 1 Timer3 controller reset 4 TMR2RST Timer2 Controller Reset 0 Timer2 controller normal operation 1 Timer2 controller reset 3 TMR1RST Timer1 Controller Reset ...

Page 99: ...25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved USCI2RST USCI1RST USCI0RST 7 6 5 4 3 2 1 0 Reserved SC1RST SC0RST Bits Description 31 11 Reserved Reserved 10 USCI2RST USCI2 Controller Reset 0 USCI2 controller normal operation 1 USCI2 controller reset 9 USCI1RST USCI1 Controller Reset 0 USCI1 controller normal operation 1 USCI1 controller reset 8 USCI0RST USCI0 Contro...

Page 100: ... 16 system clock HCLK 010 32 system clock HCLK 011 64 system clock HCLK 100 128 system clock HCLK 101 256 system clock HCLK 110 512 system clock HCLK 111 1024 system clock HCLK Note These bits are write protected Refer to the SYS_REGLCTL register 24 VDETOUT Voltage Detector Output Status 0 VDET output status is 0 It means the detected voltage is higher than Bandgap or VDETEN is 0 1 VDET output sta...

Page 101: ...ip power down mode Note2 This function need use LIRC or LXT as VDET clock source which is selected in VDETCKSEL CLK_BODCLK 0 Note2 The input pin for VDET detect voltage is selectabe by VDETPINSEL SYS_BODCTL 17 15 Reserved Reserved 14 12 LVRDGSEL LVR Output De glitch Time Select Write Protect 000 Without de glitch function 001 4 system clock HCLK 010 8 system clock HCLK 011 16 system clock HCLK 100...

Page 102: ...ing 1 When Brown out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting this bit is set to 1 and the brown out interrupt is requested if brown out interrupt is enabled Note This bit can be cleared by software writing 1 3 BODRSTEN Brown out Reset Enable Bit Write Protect The default value is set by flash control...

Page 103: ...cription 0 BODEN Brown out Detector Enable Bit Write Protect The default value is set by flash controller user configuration register CBODEN CONFIG0 23 0 Brown out Detector function Disabled 1 Brown out Detector function Enabled Note This bit is write protected Refer to the SYS_REGLCTL register ...

Page 104: ... This bit is used to enable disable VBAT unity gain buffer function 0 VBAT unity gain buffer function Disabled default 1 VBAT unity gain buffer function Enabled Note After this bit is set to 1 the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result Please refer to ADC function chapter for details 0 VTEMPEN Temperature Sensor Enable Bit This bit is used to enab...

Page 105: ... Reserved 15 0 POROFF Power on Reset Enable Bit Write Protect When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field The POR function will be active again when this field is set to another val...

Page 106: ...5 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved VREFCTL Bits Description 31 5 Reserved Reserved 4 0 VREFCTL Int_VREF Control Bits Write Protect 00000 From VREF pin 00011 VREF is internal 2 56V 00111 VREF is internal 2 048V 01011 VREF is internal 3 072V 01111 VREF is internal 4 096V 10000 VREF is from AVDD Others Reserved Note These bit are wri...

Page 107: ...4 PA7MFP PA6MFP 23 22 21 20 19 18 17 16 PA5MFP PA4MFP 15 14 13 12 11 10 9 8 PA3MFP PA2MFP 7 6 5 4 3 2 1 0 PA1MFP PA0MFP Bits Description 31 28 PA7MFP PA 7 Multi function Pin Selection 27 24 PA6MFP PA 6 Multi function Pin Selection 23 20 PA5MFP PA 5 Multi function Pin Selection 19 16 PA4MFP PA 4 Multi function Pin Selection 15 12 PA3MFP PA 3 Multi function Pin Selection 11 8 PA2MFP PA 2 Multi funct...

Page 108: ...P PA14MFP 23 22 21 20 19 18 17 16 PA13MFP PA12MFP 15 14 13 12 11 10 9 8 PA11MFP PA10MFP 7 6 5 4 3 2 1 0 PA9MFP PA8MFP Bits Description 31 28 PA15MFP PA 15 Multi function Pin Selection 27 24 PA14MFP PA 14 Multi function Pin Selection 23 20 PA13MFP PA 13 Multi function Pin Selection 19 16 PA12MFP PA 12 Multi function Pin Selection 15 12 PA11MFP PA 11 Multi function Pin Selection 11 8 PA10MFP PA 10 M...

Page 109: ...4 PB7MFP PB6MFP 23 22 21 20 19 18 17 16 PB5MFP PB4MFP 15 14 13 12 11 10 9 8 PB3MFP PB2MFP 7 6 5 4 3 2 1 0 PB1MFP PB0MFP Bits Description 31 28 PB7MFP PB 7 Multi function Pin Selection 27 24 PB6MFP PB 6 Multi function Pin Selection 23 20 PB5MFP PB 5 Multi function Pin Selection 19 16 PB4MFP PB 4 Multi function Pin Selection 15 12 PB3MFP PB 3 Multi function Pin Selection 11 8 PB2MFP PB 2 Multi funct...

Page 110: ...P PB14MFP 23 22 21 20 19 18 17 16 PB13MFP PB12MFP 15 14 13 12 11 10 9 8 PB11MFP PB10MFP 7 6 5 4 3 2 1 0 PB9MFP PB8MFP Bits Description 31 28 PB15MFP PB 15 Multi function Pin Selection 27 24 PB14MFP PB 14 Multi function Pin Selection 23 20 PB13MFP PB 13 Multi function Pin Selection 19 16 PB12MFP PB 12 Multi function Pin Selection 15 12 PB11MFP PB 11 Multi function Pin Selection 11 8 PB10MFP PB 10 M...

Page 111: ...4 PC7MFP PC6MFP 23 22 21 20 19 18 17 16 PC5MFP PC4MFP 15 14 13 12 11 10 9 8 PC3MFP PC2MFP 7 6 5 4 3 2 1 0 PC1MFP PC0MFP Bits Description 31 28 PC7MFP PC 7 Multi function Pin Selection 27 24 PC6MFP PC 6 Multi function Pin Selection 23 20 PC5MFP PC 5 Multi function Pin Selection 19 16 PC4MFP PC 4 Multi function Pin Selection 15 12 PC3MFP PC 3 Multi function Pin Selection 11 8 PC2MFP PC 2 Multi funct...

Page 112: ...15MFP PC14MFP 23 22 21 20 19 18 17 16 PC13MFP PC12MFP 15 14 13 12 11 10 9 8 PC11MFP PC10MFP 7 6 5 4 3 2 1 0 PC9MFP PC8MFP Bits Description 31 28 PC15MFP PC15 Multi function Pin Selection 27 24 PC14MFP PC14 Multi function Pin Selection 23 20 PC13MFP PC13 Multi function Pin Selection 19 16 PC12MFP PC12 Multi function Pin Selection 15 12 PC11MFP PC11 Multi function Pin Selection 11 8 PC10MFP PC10 Mul...

Page 113: ...4 PD7MFP PD6MFP 23 22 21 20 19 18 17 16 PD5MFP PD4MFP 15 14 13 12 11 10 9 8 PD3MFP PD2MFP 7 6 5 4 3 2 1 0 PD1MFP PD0MFP Bits Description 31 28 PD7MFP PD 7 Multi function Pin Selection 27 24 PD6MFP PD 6 Multi function Pin Selection 23 20 PD5MFP PD 5 Multi function Pin Selection 19 16 PD4MFP PD 4 Multi function Pin Selection 15 12 PD3MFP PD 3 Multi function Pin Selection 11 8 PD2MFP PD 2 Multi funct...

Page 114: ...P PD14MFP 23 22 21 20 19 18 17 16 PD13MFP PD12MFP 15 14 13 12 11 10 9 8 PD11MFP PD10MFP 7 6 5 4 3 2 1 0 PD9MFP PD8MFP Bits Description 31 28 PD15MFP PD 15 Multi function Pin Selection 27 24 PD14MFP PD 14 Multi function Pin Selection 23 20 PD13MFP PD 13 Multi function Pin Selection 19 16 PD12MFP PD 12 Multi function Pin Selection 15 12 PD11MFP PD 11 Multi function Pin Selection 11 8 PD10MFP PD 10 M...

Page 115: ...4 PE7MFP PE6MFP 23 22 21 20 19 18 17 16 PE5MFP PE4MFP 15 14 13 12 11 10 9 8 PE3MFP PE2MFP 7 6 5 4 3 2 1 0 PE1MFP PE0MFP Bits Description 31 28 PE7MFP PE 7 Multi function Pin Selection 27 24 PE6MFP PE 6 Multi function Pin Selection 23 20 PE5MFP PE 5 Multi function Pin Selection 19 16 PE4MFP PE 4 Multi function Pin Selection 15 12 PE3MFP PE 3 Multi function Pin Selection 11 8 PE2MFP PE 2 Multi funct...

Page 116: ...0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 PE13MFP PE12MFP 15 14 13 12 11 10 9 8 PE11MFP PE10MFP 7 6 5 4 3 2 1 0 PE9MFP PE8MFP Bits Description 31 24 Reserved Reserved 23 20 PE13MFP PE 13 Multi function Pin Selection 19 16 PE12MFP PE 12 Multi function Pin Selection 15 12 PE11MFP PE 11 Multi function Pin Selection 11 8 PE10MFP PE 10 Multi function Pin Selection 7 4 PE9MFP PE...

Page 117: ...ion 23 20 PF5MFP PF 5 Multi function Pin Selection 19 16 PF4MFP PF 4 Multi function Pin Selection The default value is set by flash controller user configuration register CFGXT1 CONFIG0 27 bit 0 PF 4 pin is configured as GPIO pins 1 PF 4 pin is configured as external 4 24 MHz external high speed crystal oscillator HXT pins 15 12 PF3MFP PF 3 Multi function Pin Selection The default value is set by ...

Page 118: ...ion Select the PWM0 channel to modulate with the UART1_TXD 000 PWM0 channel 0 modulate with UART1_TXD 001 PWM0 channel 1 modulate with UART1_TXD 010 PWM0 channel 2 modulate with UART1_TXD 011 PWM0 channel 3 modulete with UART1_TXD Others Reserved Note This bis is valid while MODEN SYS_MODCTL 0 is set to 1 3 2 Reserved Reserved 1 MODH Modulation at Data High Select modulation pulse PWM at UART1_TXD...

Page 119: ...B BIST Enable Bit Write Protect This bit enables BIST test for USB RAM 0 System USB BIST Disabled 1 System USB BIST Enabled Note This bit is write protected Refer to the SYS_REGLCTL register 3 Reserved Reserved 2 CRBIST CACHE BIST Enable Bit Write Protect This bit enables BIST test for CACHE RAM 0 System CACHE BIST Disabled 1 System CACHE BIST Enabled Note This bit is write protected Refer to the ...

Page 120: ...1 Reserved Reserved 20 USBBEND USB SRAM BIST Test Finish 0 USB SRAM BIST is active 1 USB SRAM BIST test finish 19 Reserved Reserved 18 CRBEND CACHE SRAM BIST Test Finish 0 System CACHE RAM BIST is active 1 System CACHE RAM BIST test finish 17 Reserved Reserved 16 SRBEND SRAM BIST Test Finish 0 System SRAM BIST active 1 System SRAM BIST finish 15 5 Reserved Reserved 4 USBBEF USB SRAM BIST Fail Flag...

Page 121: ...lue before the frequency of HIRC0 locked Once the HIRC0 locked the internal trim value update counter will be reset If the trim value update counter reached this limitation value and frequency of HIRC0 still doesn t lock the auto trim operation will be disabled and FREQSEL SYS_IRCTCTL0 1 0 will be cleared to 00 00 Trim retry count limitation is 64 loops 01 Trim retry count limitation is 128 loops ...

Page 122: ...arget frequency of internal high speed RC oscillator 0 HIRC0 auto trim During auto trim operation if clock error detected with CESTOPEN SYS_IRCTCTL0 8 is set to 1 or trim retry limitation count reached this field will be cleared to 00 automatically 00 Disable HIRC0 auto trim function 01 Enable HIRC0 auto trim function and trim HIRC to 22 1184 MHz 10 Reserved 11 Reserved ...

Page 123: ...lue update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL SYS_IRCTCTL1 1 0 If this bit is high and TFAILIF SYS_IRCTSTS 1 is set during auto trim operation an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached 0 Disable TFAILIF SYS_IRCTSTS 1 status to trigger an interrupt to CPU 1 Enable TFAILIF SYS_IRCTS...

Page 124: ...FERENCE MANUAL interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached 0 Disable TFAILIF SYS_IRCTSTS0 1 status to trigger an interrupt to CPU 1 Enable TFAILIF SYS_IRCTSTS0 1 status to trigger an interrupt to CPU 0 Reserved Reserved ...

Page 125: ...quency is accuracy 1 HIRC1 Clock frequency is inaccuracy 9 TFAILIF1 HIRC1 Trim Failure Interrupt Status This bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn t be locked Once this bit is set the auto trim operation stopped and FREQSEL SYS_IRCTCTL1 1 0 will be cleared to 00 by hardware automatically If this bit is set and TFAILIEN SYS_IRC...

Page 126: ... the HIRC0 clock frequency still doesn t be locked Once this bit is set the auto trim operation stopped and FREQSEL SYS_iRCTCTL0 1 0 will be cleared to 00 by hardware automatically If this bit is set and TFAILIEN SYS_IRCTIEN0 1 is high an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached Write 1 to clear this to 0 0 Trim value update limitation count d...

Page 127: ...trim value before the frequency of HIRC1 locked Once the HIRC1 locked the internal trim value update counter will be reset If the trim value update counter reached this limitation value and frequency of HIRC1 still doesn t lock the auto trim operation will be disabled and FREQSEL SYS_IRCTCTL1 1 0 will be cleared to 00 00 Trim retry count limitation is 64 loops 01 Trim retry count limitation is 128...

Page 128: ... target frequency of internal high speed RC oscillator 1 HIRC 1 auto trim During auto trim operation if clock error detected with CESTOPEN SYS_IRCTCTL1 8 is set to 1 or trim retry limitation count reached this field will be cleared to 00 automatically 00 Disable HIRC1 auto trim function 01 Reserved 10 Enable HIRC1 auto trim function and trim HIRC to 48 MHz 11 Reserved ...

Page 129: ...ed for writing protected registers Any write to the protected register is ignored 1 Write protection Disabled for writing protected registers The Protected registers are SYS_IPRST0 address 0x5000_0008 SYS_BODCTL address 0x5000_0018 SYS_PORCTL address 0x5000_0024 SYS_VREFCTL address 0x5000_0028 SYS_SRAM_BISTCTL address 0x5000_00D0 CLK_PWRCTL 13 address 0x5000_0200 HIRC48 Enable Bit CLK_PWRCTL 12 ad...

Page 130: ... 0x4014_00CC PWM0_BRKCTL4_5 address 0x4004_00D0 PWM1_BRKCTL4_5 address 0x4014_00D0 PWM0_INTEN1 address 0x4004_00E4 PWM1_INTEN1 address 0x4014_00E4 PWM0_INTSTS1 address 0x4004_00EC PWM1_INTSTS1 address 0x4014_00EC TIMER0_PWMCTL address 0x4001_0040 TIMER1_PWMCTL address 0x4001_0140 TIMER2_PWMCTL address 0x4011_0040 TIMER3_PWMCTL address 0x4011_0140 TIMER0_PWMDTCTL address 0x4001_0058 TIMER1_PWMDTCTL...

Page 131: ...NUC126 Aug 08 2018 Page 131 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL TIMER3_PWMINTSTS1 address 0x4011_018C ...

Page 132: ...e SYS_TSOFFSE T SYS_BA 0x114 R Temperature Sensor Offset Register 0x0000_0XXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved VTEMP 11 0 7 6 5 4 3 2 1 0 VTEMP 7 0 Bits Description 31 12 Reserved Reserved 11 0 VTEMP Temperature Sensor Offset Value This field reflects temperature sensor output voltage offset at 25o C from flash ...

Page 133: ...alue Register SYST_RVR on the next clock cycle then decrement on subsequent clocks When the counter transitions to 0 the COUNTFLAG status bit is set The COUNTFLAG bit clears on reads The SYST_CVR value is UNKNOWN on reset Software should write to the register to clear it to 0 before enabling the feature This ensures the timer will count from the SYST_RVR value rather than an arbitrary value when i...

Page 134: ...ad only W write only R W both read and write Register Offset R W Description Reset Value SYST Base Address SCS_BA 0xE000_E000 SYST_CSR SCS_BA 0x10 R W SysTick Control and Status Register 0x0000_0000 SYST_RVR SCS_BA 0x14 R W SysTick Reload Value Register 0xXXXX_XXXX SYST_CVR SCS_BA 0x18 R W SysTick Current Value Register 0xXXXX_XXXX ...

Page 135: ...ast time this register was read COUNTFLAG is set by a count transition from 1 to 0 COUNTFLAG is cleared on read or by a write to the Current Value register 15 3 Reserved Reserved 2 CLKSRC System Tick Clock Source Selection 0 Clock source is the optional external reference clock 1 Core clock used for SysTick 1 TICKINT System Tick Interrupt Enabled 0 Counting down to 0 does not cause the SysTick exc...

Page 136: ...eset Value SYST_RVR SCS_BA 0x14 R W SysTick Reload Value Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 RELOAD 23 16 15 14 13 12 11 10 9 8 RELOAD 15 8 7 6 5 4 3 2 1 0 RELOAD 7 0 Bits Description 31 24 Reserved Reserved 23 0 RELOAD System Tick Reload Value Value to load into the Current Value register when the counter reaches 0 ...

Page 137: ...31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CURRENT 23 16 15 14 13 12 11 10 9 8 CURRENT 15 8 7 6 5 4 3 2 1 0 CURRENT 7 0 Bits Description 31 24 Reserved Reserved 23 0 CURRENT System Tick Current Value Current counter value This is the value of the counter at the time it is sampled The counter does not provide read modify write protection The register is write clear A software write of...

Page 138: ...the mentioned registers from stack and resume the normal execution Thus it will take less and deterministic time to process the interrupt request The NVIC supports Tail Chaining which handles back to back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of current ISR The NVIC also supports Late Arr...

Page 139: ...0 PD 15 0 PE 13 0 PF 7 0 22 6 PWM0_INT PWM0 interrupt 23 7 PWM1_INT PWM1 interrupt 24 8 TMR0_INT Timer 0 interrupt 25 9 TMR1_INT Timer 1 interrupt 26 10 TMR2_INT Timer 2 interrupt 27 11 TMR3_INT Timer 3 interrupt 28 12 UART02_INT UART0 and UART2 interrupt 29 13 UART1_INT UART1 interrupt 30 14 SPI0_INT SPI0 interrupt 31 15 SPI1_INT SPI1 interrupt 32 16 Reserved 33 17 Reserved 34 18 I2C0_INT I2 C0 i...

Page 140: ...n interrupt is Active when it is disabled it remains in its Active state until cleared by reset or an exception return Clearing the enable bit prevents new activations of the associated interrupt NVIC interrupts can be pended un pended using a complementary pair of registers to those used to enable disable the interrupts named the Set Pending Register and Clear Pending Register respectively The re...

Page 141: ...C_ICPR SCS_BA 0x280 R W IRQ0 IRQ31 Clear Pending Control Register 0x0000_0000 NVIC_IPR0 SCS_BA 0x400 R W IRQ0 IRQ3 Priority Control Register 0x0000_0000 NVIC_IPR1 SCS_BA 0x404 R W IRQ4 IRQ7 Priority Control Register 0x0000_0000 NVIC_IPR2 SCS_BA 0x408 R W IRQ8 IRQ11 Priority Control Register 0x0000_0000 NVIC_IPR3 SCS_BA 0x40C R W IRQ12 IRQ15 Priority Control Register 0x0000_0000 NVIC_IPR4 SCS_BA 0x...

Page 142: ... 25 24 SETENA 23 22 21 20 19 18 17 16 SETENA 15 14 13 12 11 10 9 8 SETENA 7 6 5 4 3 2 1 0 SETENA Bits Description 31 0 SETENA Interrupt Enable Register Enable one or more interrupts Each bit represents an interrupt number from IRQ0 IRQ31 Vector number from 16 47 Write Operation 0 No effect 1 Write 1 to enable associated interrupt Read Operation 0 Associated interrupt status Disabled 1 Associated i...

Page 143: ...26 25 24 CLRENA 23 22 21 20 19 18 17 16 CLRENA 15 14 13 12 11 10 9 8 CLRENA 7 6 5 4 3 2 1 0 CLRENA Bits Description 31 0 CLRENA Interrupt Disable Bits Disable one or more interrupts Each bit represents an interrupt number from IRQ0 IRQ31 Vector number from 16 47 Write Operation 0 No effect 1 Write 1 to disable associated interrupt Read Operation 0 Associated interrupt status Disabled 1 Associated ...

Page 144: ...9 28 27 26 25 24 SETPEND 23 22 21 20 19 18 17 16 SETPEN 15 14 13 12 11 10 9 8 SETPEND 7 6 5 4 3 2 1 0 SETPEND Bits Description 31 0 SETPEND Set Interrupt Pending Bits Write Operation 0 No effect 1 Write 1 to set pending state Each bit represents an interrupt number from IRQ0 IRQ31 Vector number from 16 47 Read Operation 0 Associated interrupt in not in pending status 1 Associated interrupt is in p...

Page 145: ...9 28 27 26 25 24 CLRPEND 23 22 21 20 19 18 17 16 CLRPEND 15 14 13 12 11 10 9 8 CLRPEND 7 6 5 4 3 2 1 0 CLRPEND Bits Description 31 0 CLRPEND Clear Interrupt Pending Bits Write Operation 0 No effect 1 Write 1 to clear pending state Each bit represents an interrupt number from IRQ0 IRQ31 Vector number from 16 47 Read Operation 0 Associated interrupt in not in pending status 1 Associated interrupt is...

Page 146: ...10 9 8 PRI_1 Reserved 7 6 5 4 3 2 1 0 PRI_0 Reserved Bits Description 31 30 PRI_3 Priority of IRQ3 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_2 Priority of IRQ2 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_1 Priority of IRQ1 0 denotes the highest priority and 3 denotes the lowest priority ...

Page 147: ...10 9 8 PRI_5 Reserved 7 6 5 4 3 2 1 0 PRI_4 Reserved Bits Description 31 30 PRI_7 Priority of IRQ7 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_6 Priority of IRQ6 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_5 Priority of IRQ5 0 denotes the highest priority and 3 denotes the lowest priority ...

Page 148: ...10 9 8 PRI_9 Reserved 7 6 5 4 3 2 1 0 PRI_8 Reserved Bits Description 31 30 PRI_11 Priority of IRQ11 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_10 Priority of IRQ10 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_9 Priority of IRQ9 0 denotes the highest priority and 3 denotes the lowest prior...

Page 149: ... 9 8 PRI_13 Reserved 7 6 5 4 3 2 1 0 PRI_12 Reserved Bits Description 31 30 PRI_15 Priority of IRQ15 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_14 Priority of IRQ14 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_13 Priority of IRQ13 0 denotes the highest priority and 3 denotes the lowest pri...

Page 150: ... 9 8 PRI_17 Reserved 7 6 5 4 3 2 1 0 PRI_16 Reserved Bits Description 31 30 PRI_19 Priority of IRQ19 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_18 Priority of IRQ18 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_17 Priority of IRQ17 0 denotes the highest priority and 3 denotes the lowest pri...

Page 151: ... 9 8 PRI_21 Reserved 7 6 5 4 3 2 1 0 PRI_20 Reserved Bits Description 31 30 PRI_23 Priority of IRQ23 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_22 Priority of IRQ22 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_21 Priority of IRQ21 0 denotes the highest priority and 3 denotes the lowest pri...

Page 152: ... 9 8 PRI_25 Reserved 7 6 5 4 3 2 1 0 PRI_24 Reserved Bits Description 31 30 PRI_27 Priority of IRQ27 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_26 Priority of IRQ26 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_25 Priority of IRQ25 0 denotes the highest priority and 3 denotes the lowest pri...

Page 153: ... 9 8 PRI_29 Reserved 7 6 5 4 3 2 1 0 PRI_28 Reserved Bits Description 31 30 PRI_31 Priority of IRQ31 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_30 Priority of IRQ30 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_29 Priority of IRQ29 0 denotes the highest priority and 3 denotes the lowest pri...

Page 154: ...dentity 0xXXXX_XXXX IRQ7_SRC INT_BA 0x1C R IRQ7 PWM1 Interrupt Source Identity 0xXXXX_XXXX IRQ8_SRC INT_BA 0x20 R IRQ8 TMR0 Interrupt Source Identity 0xXXXX_XXXX IRQ9_SRC INT_BA 0x24 R IRQ9 TMR1 Interrupt Source Identity 0xXXXX_XXXX IRQ10_SRC INT_BA 0x28 R IRQ10 TMR2 Interrupt Source Identity 0xXXXX_XXXX IRQ11_SRC INT_BA 0x2C R IRQ11 TMR3 Interrupt Source Identity 0xXXXX_XXXX IRQ12_SRC INT_BA 0x30...

Page 155: ..._XXXX IRQ27_SRC INT_BA 0x6C R Reserved 0xXXXX_XXXX IRQ28_SRC INT_BA 0x70 R IRQ28 PWRWU Interrupt Source Identity 0xXXXX_XXXX IRQ29_SRC INT_BA 0x74 R IRQ29 ADC Interrupt Source Identity 0xXXXX_XXXX IRQ30_SRC INT_BA 0x78 R IRQ30 IRC CLKD Interrupt Source Identity 0xXXXX_XXXX IRQ31_SRC INT_BA 0x7C R IRQ31 RTC Interrupt Source Identity 0xXXXX_XXXX NMI_SEL INT_BA 0x80 R W NMI Source Interrupt Select Co...

Page 156: ...8 R IRQ10 TMR2 Interrupt Source Identity 0xXXXX_XXXX IRQ11_SRC INT_BA 0x2C R IRQ11 TMR3 Interrupt Source Identity 0xXXXX_XXXX IRQ12_SRC INT_BA 0x30 R IRQ12 UART0 2 Interrupt Source Identity 0xXXXX_XXXX IRQ13_SRC INT_BA 0x34 R IRQ13 UART1 Interrupt Source Identity 0xXXXX_XXXX IRQ14_SRC INT_BA 0x38 R IRQ14 SPI0 Interrupt Source Identity 0xXXXX_XXXX IRQ15_SRC INT_BA 0x3C R IRQ15 SPI1 Interrupt Source...

Page 157: ... 2 1 0 Reserved INT_SRC Bits Description 31 4 Reserved Reserved 3 0 INT_SRC Interrupt Source Define the interrupt sources for interrupt event Bits Address INT Num Description 2 0 INT_BA 0x00 0 Bit2 0 Bit1 0 Bit0 BOD_INT 2 0 INT_BA 0x04 1 Bit2 0 Bit1 WWDT_INT Bit0 WDT_INT 2 0 INT_BA 0x08 2 Bit2 EINT4 external interrupt 4 from PE 0 Bit1 EINT2 external interrupt 2 from PC 0 Bit0 EINT0 external interr...

Page 158: ... 10 Bit2 0 Bit1 0 Bit0 TMR2_INT 2 0 INT_BA 0x2C 11 Bit2 0 Bit1 0 Bit0 TMR3_INT 2 0 INT_BA 0x30 12 Bit2 0 Bit1 UART2_INT Bit0 UART0_INT 2 0 INT_BA 0x34 13 Bit2 0 Bit1 0 Bit0 UART1_INT 2 0 INT_BA 0x38 14 Bit2 0 Bit1 0 Bit0 SPI0_INT 2 0 INT_BA 0x3C 15 Bit2 0 Bit1 0 Bit0 SPI1_INT 2 0 INT_BA 0x40 16 Reserved 2 0 INT_BA 0x44 17 Reserved 2 0 INT_BA 0x48 18 Bit2 0 Bit1 0 Bit0 I2C0_INT 2 0 INT_BA 0x4C 19 B...

Page 159: ..._INT Bit0 SMC0_INT 2 0 INT_BA 0x64 25 Bit2 0 Bit1 0 Bit0 ACMP_INT 2 0 INT_BA 0x68 26 Bit2 0 Bit1 0 Bit0 PDMA_INT 2 0 INT_BA 0x6C 27 Reserved 2 0 INT_BA 0x70 28 Bit2 0 Bit1 0 Bit0 PWRWU_INT 2 0 INT_BA 0x74 29 Bit2 0 Bit1 0 Bit0 ADC_INT0 2 0 INT_BA 0x78 30 Bit2 SRAMF_INT Bit1 CLKD_INT Bit0 IRC_INT 2 0 INT_BA 0x7C 31 Bit2 0 Bit1 0 Bit0 RTC_INT ...

Page 160: ...4 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved NMI_EN 7 6 5 4 3 2 1 0 Reserved NMI_SEL Bits Description 31 8 Reserved Reserved 8 NMI_EN NMI Interrupt Enable Bit Write Protect 0 NMI interrupt Disabled 1 NMI interrupt Enabled Note This bit is write protected Refer to the SYS_REGLCTL register 7 5 Reserved Reserved 4 0 NMI_SEL NMI Interrupt Source Selection The NMI interrup...

Page 161: ...anual and ARM v6 M Architecture Reference Manual 6 2 15 1 System Control Register Map R read only W write only R W both read and write Register Offset R W Description Reset Value SCS Base Address SCS_BA 0xE000_E000 CPUID SCS_BA 0xD00 R CPUID Register 0x410C_C200 ICSR SCS_BA 0xD04 R W Interrupt Control and State Register 0x0000_0000 AIRCR SCS_BA 0xD0C R W Application Interrupt and Reset Control Reg...

Page 162: ...29 28 27 26 25 24 IMPLEMENTER 7 0 23 22 21 20 19 18 17 16 Reserved PART 3 0 15 14 13 12 11 10 9 8 PARTNO 11 4 7 6 5 4 3 2 1 0 PARTNO 3 0 REVISION 3 0 Bits Description 31 24 IMPLEMENTER Implementer Code Assigned by ARM Implementer code assigned by ARM ARM 0x41 23 20 Reserved Reserved 19 16 PART Architecture of the Processor Read as 0xC for ARMv6 M parts 15 4 PARTNO Part Number of the Processor Read...

Page 163: ...tion normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit Entering the handler then clears this bit to 0 This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler 30 29 Reserved Reserved 28 PENDSVSET PendSV Set pending Bit Write Operation 0 No effect 1 Cha...

Page 164: ...PENDSTCLR at the same time 24 Reserved Reserved 23 ISRPREEMPT If Set a Pending Exception Will Be Serviced on Exit From the Debug Halt State This bit is read only 22 ISRPENDING Interrupt Pending Flag Excluding NMI and Faults 0 Interrupt not pending 1 Interrupt pending This bit is read only 21 18 Reserved Reserved 17 12 VECTPENDING Indicates the Exception Number of the Highest Priority Pending Enabl...

Page 165: ...hen writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status Read Operation Read as 0xFA05 15 3 Reserved Reserved 2 SYSRESETREQ System Reset Request Writing this bit 1 will cause a reset signal to be asser...

Page 166: ... the processor When an event or interrupt enters pending state the event signal wakes up the processor from WFE If the processor is not waiting for an event the event is registered and affects the next WFE The processor also wakes up on execution of an SEV instruction or an external event 3 Reserved Reserved 2 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection Controls whether the processor u...

Page 167: ...et Value SHPR2 SCS_BA 0xD1C R W System Handler Priority Register 2 0x0000_0000 31 30 29 28 27 26 25 24 PRI_11 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 30 PRI_11 Priority of System Handler 11 SVCall 0 denotes the highest priority and 3 denotes the lowest priority 29 0 Reserved Reserved ...

Page 168: ..._0000 31 30 29 28 27 26 25 24 PRI_15 Reserved 23 22 21 20 19 18 17 16 PRI_14 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 30 PRI_15 Priority of System Handler 15 SysTick 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_14 Priority of System Handler 14 PendSV 0 denotes the highest priority and 3 denotes the lo...

Page 169: ... speed RC oscillator HIRC 48 MHz internal high speed RC oscillator HIRC48 10 kHz internal low speed RC oscillator LIRC Each of these clock sources has certain stable time to wait for clock operating at stable frequency When clock source is enabled a stable counter start counting and correlated clock stable index HIRCSTB CLK_STATUS 4 LIRCSTB CLK_STATUS 3 PLLSTB CLK_STATUS 2 HXTSTB CLK_STATUS 0 LXTS...

Page 170: ..._PWRCTL 2 0 1 PLL PLLSRC CLK_PLLCTL 19 PLL FOUT X32_OUT External 32 768 kHz Crystal LXT LXT LXTEN CLK_PWRCTL 1 X32_IN Internal10 KHz Oscillator LIRC LIRCEN CLK_PWRCTL 3 HXT HIRC LIRC Internal 48 MHz Oscillator HIRC48 LIRCEN CLK_PWRCTL 13 HIRC48 Note Before clock switching both the pre selected and newly selected clock source must be turned on and stable Figure 6 3 1 Clock Generator Block Diagram ...

Page 171: ...MHz 4 24 MHz 22 1184 MHz 22 1184 MHz 32 768 kHz 32 768 kHz CLK_CLKSEL2 4 2 USB 1 USBDIV 1 PLLFOUT PLLFOUT SPI1 PCLK PCLK 4 24 MHz 4 24 MHz 48 MHz 48 MHz PLLFOUT PLLFOUT CLK_CLKSEL2 25 24 CLK_CLKSEL2 27 26 32 768 kHz 32 768 kHz CLK_CLKSEL2 18 ADC PCLK PCLK 4 24 MHz 4 24 MHz 22 1184 MHz 22 1184 MHz PLLFOUT PLLFOUT CLK_CLKSEL1 3 2 BOD 10 kHz 10 kHz 1 ADCDIV 1 CRC WWDT 10 kHz 10 kHz CLK_CLKSEL1 31 30 ...

Page 172: ...nd LXT clock source and they have individual enable and interrupt control When HXT detector is enabled the HIRC clock is enabled automatically When LXT detector is enabled the LIRC clock is enabled automatically When HXT clock detector is enabled the system clock will auto switch to HIRC if HXT clock stop being detected on the following condition system clock source comes from HXT or system clock ...

Page 173: ...TCLK has 5 clock sources The clock source switch depends on the setting of the register STCLKSEL CLK_CLKSEL0 5 3 The block diagram is shown in Figure 6 3 5 111 011 010 001 HXT LXT HXT HCLK STCLKSEL CLK_CLKSEL0 5 3 STCLK HIRC 000 1 2 1 2 1 2 Note Before clock switching both the pre selected and newly selected clock source must be turned on and stable Figure 6 3 5 SysTick Clock Control Block Diagram...

Page 174: ... CLKO function pin Therefore there are 16 options of power of 2 divided clocks with the frequency from Fin 2 1 to Fin 2 16 where Fin is input clock frequency to the clock divider The output formula is Fout Fin 2 N 1 where Fin is the input clock frequency Fout is the clock divider output frequency and N is the 4 bit value in FREQSEL CLK_CLKOCTL 3 0 When writing 1 to CLKOEN CLK_CLKOCTL 4 the chained...

Page 175: ...16 to 1 MUX 1 2 1 22 1 23 1 215 1 216 FREQSEL CLK_CLKOCTL 3 0 CLKO 16 chained divide by 2 counter CLKOEN CLK_CLKOCTL 4 Enable divide by 2 counter 0 1 DIV1EN CLK_CLKOCTL 5 CLKO_CLK 0 1 CLK1HZEN CLK_CLKOCTL 6 1 Hz clock from RTC 0 1 LXT LIRC RTCSEL CLK_CLKSEL2 18 32768 Figure 6 3 7 Clock Output Block Diagram ...

Page 176: ...70F CLK_CLKSEL2 CLK_BA 0x1C R W Clock Source Select Control Register 2 0x0002_0008 CLK_CLKSEL3 CLK_BA 0x34 R W Clock Source Select Control Register 3 0x0000_0000 CLK_CLKDIV0 CLK_BA 0x18 R W Clock Divider Number Register 0 0x0000_0000 CLK_CLKDIV1 CLK_BA 0x38 R W Clock Divider Number Register 1 0x0000_0000 CLK_PLLCTL CLK_BA 0x20 R W PLL Control Register 0x008D_8418 CLK_STATUS CLK_BA 0x0C R Clock Sta...

Page 177: ...open lock sequence to program it 0 Select INV type 1 Select GM type Note This bit is write protected Refer to the SYS_REGLCTL register 11 10 HXTGAIN HXT Gain Control Bit Write Protect Gain control is used to enlarge the gain of crystal to make sure crystal work normally If gain control is enabled crystal will consume more power than gain control off 00 HXT frequency is lower than from 8 MHz 01 HXT...

Page 178: ...elayed clock cycle is 4096 clock cycles when chip work at 4 24 MHz external high speed crystal oscillator HXT 256 clock cycles when chip work at 22 1184 MHz internal high speed RC oscillator HIRC and 512 clock cycles when chip work at 48 MHz internal high speed RC oscillator HIRC48 0 Clock cycles delay Disabled 1 Clock cycles delay Enabled Note This bit is write protected Refer to the SYS_REGLCTL ...

Page 179: ... 1 1 YES Most clocks are disabled except LIRC LXT and only RTC WDT Timer UART peripheral clocks still enable if their clock sources are selected as LIRC LXT Table 6 3 2 Power down Mode Control Table When the chip enters Power down mode user can wake up chip by some interrupt sources User should enable the related interrupt sources and NVIC IRQ enable bits NVIC_ISER before set PDEN bit in CLK_PWRCT...

Page 180: ...ck Enable Bit 0 GPIO PF group clock Disabled 1 GPIO PF group clock Enabled 20 GPIOECKEN General Purpose I O PE Group Clock Enable Bit 0 GPIO PE group clock Disabled 1 GPIO PE group clock Enabled 19 GPIODCKEN General Purpose I O PD Group Clock Enable Bit 0 GPIO PD group clock Disabled 1 GPIO PD group clock Enabled 18 GPIOCCKEN General Purpose I O PC Group Clock Enable Bit 0 GPIO PC group clock Disa...

Page 181: ...Clock Enable Bit 0 Hardware divider peripheral clock Disabled 1 Hardware divider peripheral clock Enabled 3 EBICKEN EBI Controller Clock Enable Bit 0 EBI peripheral clock Disabled 1 EBI peripheral clock Enabled 2 ISPCKEN Flash ISP Controller Clock Enable Bit 0 Flash ISP peripheral clock Disabled 1 Flash ISP peripheral clock Enabled 1 PDMACKEN PDMA Controller Clock Enable Bit 0 PDMA peripheral cloc...

Page 182: ...KEN I2C0CKEN 7 6 5 4 3 2 1 0 Reserved CLKOCKEN TMR3CKEN TMR2CKEN TMR1CKEN TMR0CKEN RTCCKEN WDTCKEN Bits Description 31 Reserved Reserved 30 ACMP01CKEN Analog Comparator 0 1 Clock Enable Bit 0 Analog Comparator 0 1 clock Disabled 1 Analog Comparator 0 1 clock Enabled 29 Reserved Reserved 28 ADCCKEN Analog digital converter ADC Clock Enable Bit 0 ADC clock Disabled 1 ADC clock Enabled 27 USBDCKEN US...

Page 183: ... CLKO Clock Disabled 1 CLKO Clock Enabled 5 TMR3CKEN Timer3 Clock Enable Bit 0 Timer3 Clock Disabled 1 Timer3 Clock Enabled 4 TMR2CKEN Timer2 Clock Enable Bit 0 Timer2 Clock Disabled 1 Timer2 Clock Enabled 3 TMR1CKEN Timer1 Clock Enable Bit 0 Timer1 Clock Disabled 1 Timer1 Clock Enabled 2 TMR0CKEN Timer0 Clock Enable Bit 0 Timer0 Clock Disabled 1 Timer0 Clock Enabled 1 RTCCKEN Real time clock APB ...

Page 184: ...NUC126 Aug 08 2018 Page 184 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL Note This bit is write protected Refer to the SYS_REGLCTL register ...

Page 185: ...served 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved USCI2CKEN USCI1CKEN USCI0CKEN 7 6 5 4 3 2 1 0 Reserved SC1CKEN SC0CKEN Bits Description 31 11 Reserved Reserved 10 USCI2CKEN USCI2 Clock Enable Bit 0 USCI2 clock Disabled 1 USCI2 clock Enabled 9 USCI1CKEN USCI1 Clock Enable Bit 0 USCI1 clock Disabled 1 USCI1 clock Enabled 8 USCI0CKEN USCI0 Clock Enable Bit 0 USCI0 clock Disable...

Page 186: ... from HCLK 2 Note This bit is write protected Refer to the SYS_REGLCTL register 5 3 STCLKSEL Cortex M0 SysTick Clock Source Selection Write Protect If SYST_CTRL 2 0 SysTick uses listed clock source below 000 Clock source from HXT 001 Clock source from LXT 010 Clock source from HXT 2 011 Clock source from HCLK 2 111 Clock source from HIRC 2 Note1 if SysTick clock source is not from HCLK i e SYST_CT...

Page 187: ...of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 011 Clock source from LIRC 100 Clock source from HIRC48 111 Clock source from HIRC clock Other Reserved Note These bits are write protected Refer to the SYS_REGLCTL register ...

Page 188: ...from PCLK1 28 PWM0SEL PWM0 Clock Source Selection The peripheral clock source of PWM0 is defined by PWM0SEL 0 Clock source from PLL clock 1 Clock source from PCLK0 27 26 Reserved Reserved 25 24 UARTSEL UART Clock Source Selection 00 Clock source from 4 24 MHz external high speed crystal oscillator HXT clock 01 Clock source from PLL clock 10 Clock source from 32 768 kHz external low speed crystal o...

Page 189: ...om 22 1184 MHz internal high speed RC oscillator HIRC clock Others Reserved 11 Reserved Reserved 10 8 TMR0SEL TIMER0 Clock Source Selection 000 Clock source from 4 24 MHz external high speed crystal oscillator HXT clock 001 Clock source from 32 768 kHz external low speed crystal oscillator LXT clock 010 Clock source from PCLK0 011 Clock source from external clock T0 pin 101 Clock source from 10 kH...

Page 190: ...ource from 48 MHz internal high speed RC oscillator HIRC48 clock 25 24 SPI0SEL SPI0 Clock Source Selection 00 Clock source from 4 24 MHz external high speed crystal oscillator HXT clock 01 Clock source from PLL clock 10 Clock source from PCLK0 11 Clock source from 48 MHz internal high speed RC oscillator HIRC48 clock 23 19 Reserved Reserved 18 RTCSEL RTC Clock Source Selection 0 Clock source from ...

Page 191: ... 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 011 Clock source from 22 1184 MHz internal high speed RC oscillator HIRC clock 101 Clock source from 48 MHz internal high speed RC oscillator HIRC48 clock Others Reserved 1 0 Reserved Reserved ...

Page 192: ...SEL USBD Clock Source Selection Write Protect 0 Clock source from 48MHz internal hight speed RC oscillator HIRC48 clock 1 Clock source from PLL clock Note This bit is write protected Refer to the SYS_REGLCTL register 7 4 Reserved Reserved 3 2 SC1SEL SC1 Clock Source Selection 00 Clock source from 4 24 MHz external high speed crystal oscillator HXT clock 01 Clock source from PLL clock 10 Clock sour...

Page 193: ...Bits Description 31 24 Reserved Reserved 23 16 ADCDIV ADC Clock Divide Number From ADC Clock Source ADC clock frequency ADC clock source frequency ADCDIV 1 15 12 Reserved Reserved 11 8 UARTDIV UART Clock Divide Number From UART Clock Source UART clock frequency UART clock source frequency UARTDIV 1 7 4 USBDIV USB Clock Divide Number From PLL Source USB clock frequency PLL frequency USBDIV 1 Note I...

Page 194: ... Number Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 SC1DIV 7 6 5 4 3 2 1 0 SC0DIV Bits Description 31 16 Reserved Reserved 15 8 SC1DIV SC1 Clock Divide Number From SC1 Clock Source SC1 clock frequency SC1 clock source frequency SC1DIV 1 7 0 SC0DIV SC0 Clock Divide Number From SC0 Clock Source SC0 clock frequency SC0 clock source fr...

Page 195: ...EL PLL Stable Counter Selection 0 PLL stable time is 6144 PLL source clock suitable for source clock is equal to or less than 12MHz 1 PLL stable time is 12288 PLL source clock suitable for source clock is larger than 12MHz 22 20 Reserved Reserved 19 PLLSRC PLL Source Clock Selection 0 PLL source clock from external 4 24 MHz high speed crystal HXT 1 PLL source clock from internal 22 1184 MHz high s...

Page 196: ...las below the table Output Clock Frequency Setting NO NR NF FIN FOUT 1 Constraint 1 MHz FIN MHz 24 4 2 MHz NR FIN KHz 8 2 800 3 preferred is MHz FCO MHz NR NF FIN FCO MHz 120 200 100 Symbol Description FOUT Output Clock Frequency FIN Input Reference Clock Frequency NR Input Divider INDIV 2 NF Feedback Divider FBDIV 2 NO OUTDIV 00 NO 1 OUTDIV 01 NO 2 OUTDIV 10 NO 2 OUTDIV 11 NO 4 ...

Page 197: ...switch system clock to selected clock automatically and CLKSFAIL will be cleared automatically by hardware 6 Reserved Reserved 5 HIRC48STB HIRC48 Clock Source Stable Flag Read Only 0 48 MHz internal high speed RC oscillator HIRC48 clock is not stable or disabled 1 48 MHz internal high speed RC oscillator HIRC48 clock is stabe and enabled 4 HIRCSTB HIRC Clock Source Stable Flag Read Only 0 22 1184 ...

Page 198: ...6 SERIES TECHNICAL REFERENCE MANUAL 0 HXTSTB HXT Clock Source Stable Flag Read Only 0 4 24 MHz external high speed crystal oscillator HXT clock is not stable or disabled 1 4 24 MHz external high speed crystal oscillator HXT clock is stable and enabled ...

Page 199: ...k output for 32 768 kHz external low speed crystal oscillator LXT frequency compensation Disabled 1 1 Hz clock output for 32 768 kHz external low speed crystal oscillator LXT frequency compensation Enabled 5 DIV1EN Clock Output Divide One Enable Bit 0 Clock Output will output clock with source frequency divided by FREQSEL 1 Clock Output will output clock with source frequency 4 CLKOEN Clock Output...

Page 200: ...d 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved VDETCKSEL Bits Description 31 1 Reserved Reserved 0 VDETCKSEL Clock Source Selection for Voltage Detector The Voltage Detector clock source for detecting external input voltage is defined by VDETCKSEL 0 Clock source is from 10 kHz internal low speed RC oscillator LIRC clock 1 Clock source is from 32 768 kHz external low speed crystal oscill...

Page 201: ...ator HXT clock frequency monitor Disabled 1 4 24 MHz external high speed crystal oscillator HXT clock frequency monitor Enabled 15 14 Reserved Reserved 13 LXTFIEN LXT Clock Fail Interrupt Enable Bit 0 32 768 kHz external low speed crystal oscillator LXT clock Fail interrupt Disabled 1 32 768 kHz external low speed crystal oscillator LXT clock Fail interrupt Enabled 12 LXTFDEN LXT Clock Fail Detect...

Page 202: ...stal oscillator HXT clock frequency abnormal Note1 This bit can be cleared to 0 by software writing 1 Note2 This bit is write protected Refer to the SYS_REGLCTL register 7 2 Reserved Reserved 1 LXTFIF LXT Clock Fail Interrupt Flag Write Protect 0 32 768 kHz external low speed crystal oscillator LXT clock normal 1 32 768 kHz external low speed crystal oscillator LXT stop Note1 This bit can be clear...

Page 203: ...or Upper Boundary Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved UPERBD 7 6 5 4 3 2 1 0 UPERBD Bits Description 31 10 Reserved Reserved 9 0 UPERBD HXT Clock Frequency Detector Upper Boundary The bits define the high value of frequency monitor window When HXT frequency monitor value higher than this register the HXT frequency de...

Page 204: ...r Low Boundary Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved LOWERBD 9 8 7 6 5 4 3 2 1 0 LOWERBD Bits Description 31 10 Reserved Reserved 9 0 LOWERBD HXT Clock Frequency Detector Low Boundary The bits define the low value of frequency monitor window When HXT frequency monitor value lower than this register the HXT frequency de...

Page 205: ...ion user switches the code executing without the chip reset after the embedded flash updated 6 4 2 Features Supports 128 256 Kbytes application ROM APROM Supports 4 Kbytes loader ROM LDROM Supports 2 Kbytes security protection ROM SPROM to conceal user program Supports Data Flash with configurable memory size Supports 12 bytes User Configuration block to control system initiation Supports 2 Kbytes...

Page 206: ...rity Protection ROM SPROM 2KB Flash Operation Controller Flash Initialization Controller AHB Slave Interface Loader ROM LDROM 4KB Embedded Flash Memory User Configuration Application ROM 128KB 256KB with Data Flash Cortex M0 AHB BUS Flash Memory Controller Flash Control Registers Figure 6 4 1 Flash Memory Controller Block Diagram AHB Slave Interface There is one AHB slave interfaces in flash memor...

Page 207: ... program bit size is 32 bits 6 4 4 Functional Description FMC functions include the memory organization boot selection IAP ISP the embedded flash programming and checksum calculation The flash memory map and system memory map are also introduced in the memory organization 6 4 4 1 Memory Organization The FMC memory consists of the embedded flash memory which is programmable and includes APROM LDROM...

Page 208: ...3 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 0x0003_FFFF 128KB ApplicationROM APROM Data Flash DFBA 256KB ApplicationROM APROM Data Flash DFBA 0x0001_FFFF APROM 128KB Device APROM 256KB Device 0x0000_0000 Figure 6 4 2 Data Flash ...

Page 209: ...bit RSTEN WDT_CTL 1 is set to 1 automatically after power on The clock source of watchdog timer is force at LIRC and LIRC can t be disabled in normal operation mode However if in Power down mode the LIRC may be able to be disabled by setting CWDTPDEN 1 and LIRCEN 0 CLK_PWRCTL 3 CWDTEN 2 0 is CONFIG0 31 4 3 011 WDT hardware enable function is active WDT clock is always on except chip enters Power d...

Page 210: ...z internal high speed RC oscillator HIRC 25 24 Reserved Reserved 23 CBODEN Brown Out Detector Enable Bit 0 Brown out detect Enabled after powered on 1 Brown out detect Disabled after powered on 22 21 CBOV Brown Out Voltage Selection 00 Brown out voltage is 2 2V 01 Brown out voltage is 2 7V 10 Brown out voltage is 3 7V 11 Brown out voltage is 4 5V 20 CBORST Brown Out Reset Enable Bit 0 Brown out re...

Page 211: ...CBS 0 0 5 MERASE ISP Flash Mass Erase Enable Bit This bit is used to control mess erase function 0 ISP Flash Mass Erase command Enabled 1 ISP Flash Mass Erase command Disabled 4 3 CWDTEN 1 0 Watchdog Timer Hardware Enable Bit Please refer to CWDTEN 2 CONFIG0 31 for detail descriptions 2 Reserved Reserved 1 LOCK Security Lock Control This bit is used to enable security lock function If security loc...

Page 212: ...9 18 17 16 Reserved DFBA 15 14 13 12 11 10 9 8 DFBA 7 6 5 4 3 2 1 0 DFBA Bits Descriptions 31 20 Reserved Reserved 19 0 DFBA Data Flash Base Address This register works only when DFEN CONFIG0 0 set to 0 If DFEN CONFIG0 0 is set to 0 the Data Flash base address is defined by user Since on chip flash erase unit is 2 Kbytes it is mandatory to keep bit 10 0 as 0 ...

Page 213: ...of SPROM 0x0000_0000 0x0010_0000 0x0010_0FFF 0x0020_0000 0x0020_07FF 0x0003_FFFF 0x0030_0000 0x0030_0004 0x0020_07FF 0x0020_0000 SPROM Security Mode SPROM Debug Mode SPROM Non security Mode Reserved User Configuration 8 Bytes Reserved Security Protection ROM SPROM 2KB Reserved Loader ROM LDROM 4KB Reserved Application ROM APROM 128KB 256KB Security Protection ROM SPROM 2KB 0xFF Security Protection...

Page 214: ... enter secured mode without program last byte of SPROM Flash Memory Map In the NUC126 series the flash memory map is different from system memory map The system memory map is used by CPU fetch code or data from flash memory The flash memory map is used for ISP function to read program or erase flash memory The flash memory map is as Figure 6 4 4 0x0000_0000 0x0010_0000 0x0010_0FFF APROM 128KB Devi...

Page 215: ... The vector map consist of vector table for stack and exceptions By remapping the vector table in APROM or LDROM to the vector map space it is possible to reboot to different applications There are two kinds of system memory map with IAP mode when chip booting LDROM with IAP and APROM with IAP 0x0000_0000 0x0010_0000 0x0010_1000 0x0020_0000 0x0020_0800 0x0004_0000 DFBA 0x0000_0200 Reserved Securit...

Page 216: ...ROM or LDROM User can also map any 512 bytes alignment space of APROM LDROM or SRAM to vector map space To set vector map space mapping user should write the target remap address to FMC_ISPADDR register and then trigger ISP procedure with the Vector Page Remap command 0x2E The finial system memory vector mapping address is shown on VECMAP FMC_ISPSTS 29 9 Please note that the vector mapping functio...

Page 217: ...s IAP mode the Data Flash is shared with APROM and the Data Flash base address is defined by CONFIG1 Therefore in APROM without IAP mode we still can use Data Flash function 0x0000_0000 0x0003_FFFF APROM without IAP mode 0x0000_0FFF LDROM without IAP mode Application ROM APROM Data Flash SPROM DFBA 0x0020_07FF 0x0020_0000 User Config Loader ROM LDROM SPROM User Config 0x0030_0000 Figure 6 4 8 Syst...

Page 218: ...h as UART USB I 2 C and SPI The NUC126 ISP provides the following functions for embedded flash memory Supports flash page erase function Supports flash mass erase function Supports flash data program function Supports flash data read function Supports company ID read function Supports device ID read function Supports unique ID read function Supports memory CRC32 checksum calculation function Suppo...

Page 219: ... Read Company ID 0x0B 0x0000_0000 FMC_ISPDAT 0x0000_00DA Read Device ID 0x0C 0x0000_0000 FMC_ISPDAT Return Device ID Read Checksum 0x0D Keep address of Run Checksum Calculation FMC_ISPDAT Return Checksum Run Checksum Calculation 0x2D Valid start address of memory organization It must be 512 bytes page alignment FMC_ISPDAT Size It must be 512 bytes alignment Run Flash All One Verification 0x28 Vali...

Page 220: ...SPGO 0 NO YES Start Stop Figure 6 4 9 ISP Procedure Example Finally set the ISPGO FMC_ISPTRG 0 register to trigger the relative ISP function The ISPGO FMC_ISPTRG 0 bit is self cleared when ISP function has been done To make sure ISP function has been finished before CPU goes ahead ISB Instruction Synchronization Barrier instruction is used right after ISPGO FMC_ISPTRG 0 setting Several error condi...

Page 221: ... 0 Copy to SRAM 0x0000_0000 0x2000_0000 Remapping to Vector Map Space 0x0000_0200 0x0000_0200 VECMAP 0x0 VECMAP 0x0 VECMAP 0x2000_0000 Figure 6 4 10 Example for accelerating interrupt by VECMAP Avoid CPU Holt when Flash Programming When flash memory controller is in busy any CPU access to flash memory will cause CPU holt for waiting flash controller ready If flash controller is busy in page erasin...

Page 222: ... 64 bit Programming The NUC126 series 64 bit programming function is faster than 32 bit programming FMC_ISPDAT is used for 32 bit programming data register In 64 bit programming there are two programming data registers one is FMC_MPDAT0 for LSB word and the other is FMC_MPDAT1 for MSB word and ISP command is 0x61 the other registers are the same as 32 bit programming Figure 6 4 11 Figure 6 4 12 sh...

Page 223: ...rogramming length is up to 256 bytes and the minimum programming length is 8 bytes 2 words The multi word programming is the fastest programming function if the programming words more than 8 bytes In multi word programming operation CPU has to monitor the empty status of the programming buffer and prepare the next data for programming continuity The multi program firmware should not be located in ...

Page 224: ... word is FMC_MPDAT2 and 4 th word is FMC_MPDAT3 If the starting ISP address FMC_ISPADDR 3 is 1 the 1 st data word should put on FMC_MPDAT2 and 2 nd word is FMC_MPDAT3 3 rd word is FMC_MPDAT0 and 4 th word is FMC_MPDAT1 The maximum programming size is 256 bytes While FMC controller performs multi word programming operation CPU needs to monitor the buffer status D3 D0 FMC_MPSTS 7 4 and MPBUSY FMC_MP...

Page 225: ...PDAT3 Y N Enable ISPEN Set ISPGO 1 End of ISP Operation Y Programming Finish Read FMC_MPSTS MPBUSY 0 N Y Write FMC_MPDAT0 Write FMC_MPDAT1 Read FMC_MPSTS N Y MPBUSY 0 N Y Write FMC_MPDAT2 Write FMC_MPDAT3 Data Finish MPBUSY 0 Read FMC_MPSTS Multi Word Programming Finish Y Y N N Check D3 D2 00 Check D1 D0 00 Read FMC_MPADDR N N Y Figure 6 4 14 Multi word Programming Flow ...

Page 226: ..._CHKSUM 31 0 CRC32 0 CRC32_R 3 1 CRC32_R 0 CRC_CHKSUM 0 CRC_CHKSUM 3 1 Figure 6 4 15 CRC 32 Checksum Calculation Three steps complete this checksum calculation Step 1 perform ISP Run Memory Checksum operation Step 2 perform ISP Read Memory Checksum operation Step 3 read FMC_ISPDAT to get checksum In step 1 user has to set the memory starting address FMC_ISPADDR and size FMC_ISPDAT to calculate Bot...

Page 227: ...GO 1 Write FMC_ISPADDR Write FMC_ISPDAT Write FMC_ISPCMD 0x2D Add ISB instruction Check ISPGO 0 NO YES Checksum Calculation Start END Set ISPGO 1 Write FMC_ISPCMD 0x0D Add ISB instruction Check ISPGO 0 NO YES Read Checksum from FMC_ISPDAT Step 1 Step 2 Step 3 Figure 6 4 16 CRC 32 Checksum Calculation Flow ...

Page 228: ...cation result The ALLONE must be 1 if all one verification pass Otherwise the all one verification fail In step 1 user has to set the memory starting address FMC_ISPADDR and size FMC_ISPDAT to verify Both address and size have to be 512 bytes alignment the size should be 512 bytes and the starting address includes APROM LDROM and SPROM In step 2 the FMC_ISPADDR should be kept as the same as step 1...

Page 229: ...ister 0x0000_0000 FMC_ISPTRG FMC_BA 0x10 R W ISP Trigger Control Register 0x0000_0000 FMC_DFBA FMC_BA 0x14 R Data Flash Base Address 0xXXXX_XXXX FMC_FTCTL FMC_BA 0x18 R W Flash Access Time Control Register 0x0000_0000 FMC_ISPSTS FMC_BA 0x40 R W ISP Status Register 0xX000_000X FMC_MPDAT0 FMC_BA 0x80 R W ISP Data0 Register 0x0000_0000 FMC_MPDAT1 FMC_BA 0x84 R W ISP Data1 Register 0x0000_0000 FMC_MPD...

Page 230: ...s set by hardware when a triggered ISP meets any of the following conditions This bit needs to be cleared by writing 1 to it 1 APROM writes to itself if APUEN is set to 0 2 LDROM writes to itself if LDUEN is set to 0 3 CONFIG is erased programmed if CFGUEN is set to 0 4 SPROM is erased programmed if SPUEN is set to 0 5 SPROM is programmed at SPROM secured mode 6 Page Erase command at LOCK mode wit...

Page 231: ... be updated Note This bit is write protected Refer to the SYS_REGLCTL register 1 BS Boot Select Write Protect Set clear this bit to select next booting from LDROM APROM respectively This bit also functions as chip booting status flag which can be used to check where chip booted from This bit is initiated with the inversed value of CBS 1 CONFIG0 7 after any reset is happened except CPU reset CPU is...

Page 232: ...3 22 21 20 19 18 17 16 ISPADDR 15 14 13 12 11 10 9 8 ISPADDR 7 6 5 4 3 2 1 0 ISPADDR Bits Description 31 0 ISPADDR ISP Address The NuMicro NUC126 series is equipped with embedded flash ISPADDR 1 0 must be kept 00 for ISP 32 bit operation ISPADDR 2 0 must be kept 000 for ISP 64 bit operation For Checksum Calculation command this field is the flash starting address for checksum calculation 512 bytes...

Page 233: ...4 13 12 11 10 9 8 ISPDAT 7 6 5 4 3 2 1 0 ISPDAT Bits Description 31 0 ISPDAT ISP Data Write data to this register before ISP program operation Read data from this register after ISP read operation For Run Checksum Calculation command ISPDAT is the memory size byte and 512 bytes alignment For ISP Read Checksum command ISPDAT is the checksum result If ISPDAT 0x0000_0000 it means that 1 the checksum ...

Page 234: ... 5 4 3 2 1 0 Reserved CMD Bits Description 31 7 Reserved Reserved 6 0 CMD ISP CMD ISP command table is shown below 0x00 FLASH Read 0x40 FLASH 64 bit Read 0x04 Read Unique ID 0x08 Read Flash All One Result 0x0B Read Company ID 0x0C Read Device ID 0x0D Read Checksum 0x21 FLASH 32 bit Program 0x22 FLASH Page Erase 0x26 FLASH Mass Erase 0x27 FLASH Multi Word Program 0x28 Run Flash All One Verification...

Page 235: ...30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ISPGO Bits Description 31 1 Reserved Reserved 0 ISPGO ISP Start Trigger Write Protect Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished 0 ISP operation is finished 1 ISP is progressed Note This bit is write pr...

Page 236: ...a Flash Base Address 0xXXXX_XXXX 31 30 29 28 27 26 25 24 DFBA 23 22 21 20 19 18 17 16 DFBA 15 14 13 12 11 10 9 8 DFBA 7 6 5 4 3 2 1 0 DFBA Bits Description 31 0 DFBA Data Flash Base Address This register indicates Data Flash start address It is a read only register The Data Flash is shared with APROM the content of this register is loaded from CONFIG1 This register is valid when DFEN CONFIG0 0 0 ...

Page 237: ...EOFF FOM FATS FPSEN Bits Description 31 8 Reserved Reserved 7 CACHEOFF Flash Cache Disable Bit Write Protect 0 Flash Cache function Enabled default 1 Flash Cache function Disabled Note This bit is write protected Refer to the SYS_REGLCTL register 6 4 FOM Frequency Optimization Mode Write Protect The NUC126 series supports adjustable flash access timing to optimize the flash access cycles in differ...

Page 238: ...age erase operation 0 Secured code is inactive 1 Secured code is active 30 Reserved Reserved 29 9 VECMAP Vector Page Mapping Address Read Only All access to 0x0000_0000 0x0000_01FF is remapped to the flash memory or SRAM address VECMAP 20 0 9 h000 VECMAP 20 0 9 h1FF except SPROM VECMAP 20 19 00 system vector address is mapped to flash memory VECMAP 20 19 10 system vector address is mapped to SRAM ...

Page 239: ...onnection 7 Erase or Program command at brown out detected 8 Destination address is illegal such as over an available range 9 Invalid ISP commands 10 system vector address is remapped to SPROM Note This bit is write protected Refer to the SYS_REGLCTL register 5 3 Reserved Reserved 2 1 CBS Boot Selection of CONFIG Read Only This bit is initiated with the CBS CONFIG0 7 6 after any reset is happened ...

Page 240: ...MPDAT0 FMC_BA 0x80 R W ISP Data0 Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPDAT0 23 22 21 20 19 18 17 16 ISPDAT0 15 14 13 12 11 10 9 8 ISPDAT0 7 6 5 4 3 2 1 0 ISPDAT0 Bits Description 31 0 ISPDAT0 ISP Data 0 This register is the first 32 bit data for 32 bit 64 bit multi word programming and it is also the mirror of FMC_ISPDAT both registers keep the same data ...

Page 241: ... Offset R W Description Reset Value FMC_MPDAT1 FMC_BA 0x84 R W ISP Data1 Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPDAT1 23 22 21 20 19 18 17 16 ISPDAT1 15 14 13 12 11 10 9 8 ISPDAT1 7 6 5 4 3 2 1 0 ISPDAT1 Bits Description 31 0 ISPDAT1 ISP Data 1 This register is the second 32 bit data for 64 bit multi word programming ...

Page 242: ...ster Offset R W Description Reset Value FMC_MPDAT2 FMC_BA 0x88 R W ISP Data2 Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPDAT2 23 22 21 20 19 18 17 16 ISPDAT2 15 14 13 12 11 10 9 8 ISPDAT2 7 6 5 4 3 2 1 0 ISPDAT2 Bits Description 31 0 ISPDAT2 ISP Data 2 This register is the third 32 bit data for multi word programming ...

Page 243: ...ter Offset R W Description Reset Value FMC_MPDAT3 FMC_BA 0x8C R W ISP Data3 Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPDAT3 23 22 21 20 19 18 17 16 ISPDAT3 15 14 13 12 11 10 9 8 ISPDAT3 7 6 5 4 3 2 1 0 ISPDAT3 Bits Description 31 0 ISPDAT3 ISP Data 3 This register is the fourth 32 bit data for multi word programming ...

Page 244: ...rogram to flash complete 6 D2 ISP DATA 2 Flag Read Only This bit is set when FMC_MPDAT2 is written and auto clear to 0 when the FMC_MPDAT2 data is programmed to flash complete 0 FMC_MPDAT2 register is empty or program to flash complete 1 FMC_MPDAT2 register has been written and not program to flash complete 5 D1 ISP DATA 1 Flag Read Only This bit is set when FMC_MPDAT1 is written and auto clear to...

Page 245: ...e command at LOCK mode with ICE connection 5 Erase or Program command at brown out detected 6 Destination address is illegal such as over an available range 7 Invalid ISP commands 1 PPGO ISP Multi program Status Read Only 0 ISP multi word program operation is not active 1 ISP multi word program operation is in progress 0 MPBUSY ISP Multi word Program Busy Flag Read Only Write 1 to start ISP Multi ...

Page 246: ...FMC_BA 0xC4 R ISP Multi Program Address Register 0x0000_0000 31 30 29 28 27 26 25 24 MPADDR 23 22 21 20 19 18 17 16 MPADDR 15 14 13 12 11 10 9 8 MPADDR 7 6 5 4 3 2 1 0 MPADDR Bits Description 31 0 MPADDR ISP Multi word Program Address MPADDR is the address of ISP multi word program operation when ISPGO flag is 1 MPADDR will keep the final ISP address when ISP multi word program is complete ...

Page 247: ...nalog input voltage range 0 VDDA voltage of AVDD pin Supports hysteresis function Supports wake up function Selectable input sources of positive input and negative input ACMP0 supports 4 positive sources ACMP0_P0 ACMP0_P1 ACMP0_P2 or ACMP0_P3 3 negative sources ACMP0_N Comparator Reference Voltage CRV Internal band gap voltage VBG ACMP1 supports 4 positive sources ACMP1_P0 ACMP1_P1 ACMP1_P2 or ACM...

Page 248: ... FILTSEL ACMP_CTL0 15 13 ACMPOINV ACMP_CTL1 3 ACMP0_WLA T ACMP_CTL0 5 4 ACMP_CTL1 0 HYSEN ACMP_CTL0 2 ACMP_CTL0 0 0 1 0 1 WCMPSEL WCMPSEL ACMP_CTL0 18 ACMP_CTL1 18 ACMPWO ACMP_STATUS 16 ACMPS0 ACMP_STATUS 12 ACMPS1 ACMP_STATUS 13 ACMP_STATUS 4 ACMP_STATUS 5 ACMP0_N ACMP1_N ACMPOINV ACMP_CTL0 3 WLATOUT0 PWM Timer Brake WLATOUT1 POSSEL ACMP_CTL0 7 6 0 1 INT_VREF CRVCTL ACMP_VREF 3 0 CRVSSEL ACMP_VRE...

Page 249: ...LAT PC 0 MFP5 ACMP1 ACMP1_N PD 0 MFP5 ACMP1_O PC 2 PC 6 MFP5 ACMP1_P0 PD 3 MFP5 ACMP1_P1 PD 2 MFP5 ACMP1_P2 PD 1 MFP5 ACMP1_P3 PD 9 MFP5 ACMP1_WLAT PC 1 MFP5 6 5 5 Functional Description 6 5 5 1 Hysteresis Function The analog comparator provides the hysteresis function to make the comparator to have a stable output transition If comparator output is 0 it will not be changed to 1 until the positive...

Page 250: ... WLATOUT0 Window Latch Enable Bypass ACMPO0 Bypass ACMPO0 Bypass ACMPO0 Keep High Keep Low Keep High Bypass ACMPO0 Bypass ACMPO0 Keep High Window Off Window On Window On Window Off Window Off Window Off Figure 6 5 3 Window Latch Mode of ACMP0 6 5 5 3 Filter Function The analog comparator provides filter function to avoid the un stable state of comparator output By setting FILTSEL ACMP_CTL0 15 13 A...

Page 251: ... ACMPIE the WKIF ACMP_STATUS 8 ACMP_STATUS 9 will be set and cause interrupt rising Figure 6 5 5 shows the interrups of ACMP is coming from ACMPIF or WKIF and enabled or disabled by ACMPIE ACMPIF0 ACMP_STATUS 0 ACMPIE ACMP_CTL0 1 ACMPIF1 ACMP_STATUS 1 ACMPIE ACMP_CTL1 1 ACMP01_INT WKIF0 ACMP_STATUS 8 WKIF1 ACMP_STATUS 9 Figure 6 5 5 Comparator Controller Interrupt 6 5 5 5 Comparator Reference Volt...

Page 252: ... lower bound of the designated range are determined by the voltages applied to the other inputs of both comparators If the output of a comparator is low and the other comparator outputs high which means two comparators implies the upper and lower bound User can directly monitor a specific analog voltage source via ACMPWO ACMP_STATUS 16 If ACMPWO is high it implies a specific analog voltage source ...

Page 253: ...XOR ACMPS1 ACMP1_N ACMP0_N ACMP0 1_P Voltage of upper bound Voltage of lower bound ACMPS1 ACMPS0 1 In the window 0 Out of the window ACMPWO Figure 6 5 8 Example of Window Compare Mode As shown in Figure 6 5 8 if ACMPWO equals 1 it means positive input voltage inside the window Otherwise the positive input voltage outside the window Therefore user can use ACMPWO to monitor voltage transition of ext...

Page 254: ...ion Reset Value ACMP Base Address ACMP01_BA 0x400D_0000 ACMP_CTL0 ACMP01_BA 0x00 R W Analog Comparator 0 Control Register 0x0000_0000 ACMP_CTL1 ACMP01_BA 0x04 R W Analog Comparator 1 Control Register 0x0000_0000 ACMP_STATUS ACMP01_BA 0x08 R W Analog Comparator Status Register 0x0000_0000 ACMP_VREF ACMP01_BA 0x0C R W Analog Comparator Reference Voltage Control Register 0x0000_0000 ...

Page 255: ...h Function Disabled 1 Window Latch Function Enabled 16 WKEN Power down Wake up Enable Bit 0 Wake up function Disabled 1 Wake up function Enabled 15 13 FILTSEL Comparator Output Filter Count Selection 000 Filter function Disabled 001 ACMP0 output is sampled 1 consecutive PCLK 010 ACMP0 output is sampled 2 consecutive PCLKs 011 ACMP0 output is sampled 4 consecutive PCLKs 100 ACMP0 output is sampled ...

Page 256: ...ernal comparator reference voltage CRV 10 Band gap voltage 11 Reserved 3 ACMPOINV Comparator Output Inverse 0 Comparator 0 output inverse Disabled 1 Comparator 0 output inverse Enabled 2 HYSEN Comparator Hysteresis Enable Bit 0 Comparator 0 hysteresis Disabled 1 Comparator 0 hysteresis Enabled 1 ACMPIE Comparator Interrupt Enable Bit 0 Comparator 0 interrupt Disabled 1 Comparator 0 interrupt Enabl...

Page 257: ...isabled 1 Window Latch function Enabled 16 WKEN Power down Wakeup Enable Bit 0 Wake up function Disabled 1 Wake up function Enabled 15 13 FILTSEL Comparator Output Filter Count Selection 000 Filter function Disabled 001 ACMP1 output is sampled 1 consecutive PCLK 010 ACMP1 output is sampled 2 consecutive PCLKs 011 ACMP1 output is sampled 4 consecutive PCLKs 100 ACMP1 output is sampled 8 consecutive...

Page 258: ...1 Internal comparator reference voltage CRV 10 Band gap voltage 11 Ground 3 ACMPOINV Comparator Output Inverse Control 0 Comparator 1 output inverse Disabled 1 Comparator 1 output inverse Enabled 2 HYSEN Comparator Hysteresis Enable Bit 0 Comparator 1 hysteresis Disabled 1 Comparator 1 hysteresis Enabled 1 ACMPIE Comparator Interrupt Enable Bit 0 Comparator 1 interrupt Disabled 1 Comparator 1 inte...

Page 259: ...omparator 1 Status Synchronized to the PCLK to allow reading by software Cleared when the comparator 1 is disabled i e ACMPEN ACMP_CTL1 0 is cleared to 0 12 ACMPS0 Comparator 0 Status Synchronized to the PCLK to allow reading by software Cleared when the comparator 0 is disabled i e ACMPEN ACMP_CTL0 0 is cleared to 0 11 10 Reserved Reserved 9 WKIF1 Comparator 1 Power down Wake up Interrupt Flag Th...

Page 260: ...ved Reserved 1 ACMPIF1 Comparator 1 Interrupt Flag This bit is set by hardware when the edge condition defined by INTPOL ACMP_CTL1 9 8 is detected on comparator 1 output This will cause an interrupt if ACMPIE ACMP_CTL1 1 is set to 1 Note Write 1 to clear this bit to 0 0 ACMPIF0 Comparator 0 Interrupt Flag This bit is set by hardware when the edge condition defined by INTPOL ACMP_CTL0 9 8 is detect...

Page 261: ..._0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CRVSSEL Reserved CRVCTL Bits Description 31 7 Reserved Reserved 6 CRVSSEL CRV Source Voltage Selection 0 AVDD is selected as CRV voltage source 1 The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage 5 4 Reserved Reserved 3 0 CRVCTL Compa...

Page 262: ...ores the result in FIFO Single cycle Scan mode A D conversion is performed only one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel Continuous Scan mode A D converter continuously performs Single cycle Scan mode until software stops A D conversion An A D conversion can be started by Software Write 1 to ADST bit External pin STADC...

Page 263: ... A D Data Register 0 ADDR0 A D Data Register 1 ADDR1 A D Data Register 19 ADDR19 VREF 12 bit DAC ADC PDMA Current Transfer Data Register ADPDMA A D Status Register1 ADSR1 A D Status Register2 ADSR2 TIMER_TRG ADC0_CH19 VBAT APB Bus A D Data Register29 31 ADDR29 31 PDMA request SYS_VREFCTL 4 0 INT_VREF AIN0 AIN1 AIN19 VBATUGEN SYS_IVSCTL 1 VTEMPEN SYS_IVSCTL 0 Figure 6 6 1 AD Controller Block Diagra...

Page 264: ...he A D converter operates by successive approximation with 12 bit resolution The ADC has four operation modes Single Burst Single cycle Scan mode and Continuous Scan mode When user wants to change the operation mode or analog input channel in order to prevent incorrect operation software must clear ADST ADCR 11 bit to 0 in advance 6 6 5 1 ADC peripheral Clock Generator The maximum sampling rate is...

Page 265: ...onversion is finished the result is stored in the ADC data register corresponding to the channel 3 The ADF bit of ADSR0 register will be set to 1 If the ADIE bit of ADCR register is set to 1 the ADC interrupt will be asserted 4 The ADST bit remains 1 during A D conversion When A D conversion ends the ADST bit is automatically cleared to 0 and the A D converter enters idle state Note1 If software e...

Page 266: ...r external trigger input A D conversion is started on the enabled channel with the smallest number 2 When A D conversion for the specified channel is completed the result is sequentially transferred to FIFO and can be accessed only from the ADC data register 0 3 When more than or equal to 8 samples in FIFO the ADF bit in ADSR0 register is set to 1 If the ADIE bit of ADCR register is set to 1 at th...

Page 267: ...s and converts all of the specified channels once in the sequence from the smallest number enabled channel to the largest number enabled channel Operations are as follows 1 When the ADST bit in ADCR register is set to 1 by software or external trigger input A D conversion is started on the enabled channel with the smallest number 2 When A D conversion for each enabled channel is completed the resu...

Page 268: ... external trigger input A D conversion is started on the enabled channel with the smallest number 2 When A D conversion for each enabled channel is completed the result of each enabled channel is stored in the ADC data register corresponding to each enabled channel 3 When A D converter completes the conversions of all enabled channels sequentially the ADF bit in ADSR0 register will be set to 1 If ...

Page 269: ...kept at active state in level trigger mode It is stopped only when external condition trigger condition disappears If edge trigger condition is selected the high and low state must be kept at least 4 PCLKs Pulse that is shorter than this specification will be ignored Note User enables the external trigger function or enables ADC must be at least 4 PCLKs after enabling ADC peripheral clock 6 6 5 7 ...

Page 270: ... CMPMATCNT ADCMPRx 11 8 AIN0 AIN19 CHANNEL ADSR0 31 27 CMPCH ADCMPRx 7 3 ADDRx 11 0 CMPD ADCMPRx 27 16 Note CMPD ADCMPRx 27 16 RSLT ADDRx 11 0 VBG VBAT VTEMP Figure 6 6 7 A D Conversion Result Monitor Logic Diagram 6 6 5 10 Compare Window Mode The ADC controller supports a compare window mode User can set CMPWEN ADCMPR0 15 to enable this function If user enables this function CMPF0 ADSR0 1 will be...

Page 271: ...lags of compare function When the conversion result meets the settings of ADCMPR0 1 registers the corresponding flag will be set to 1 When one of the flags ADF CMPF0 and CMPF1 is set to 1 and the corresponding interrupt enable bit ADIE of ADCR register and CMPIE of ADCMPR0 1 registers is set to 1 the ADC interrupt will be asserted Software can clear these flags to revoke the interrupt request ADF ...

Page 272: ...DDR10 ADC_BA 0x28 R ADC Data Register 10 0x0000_0000 ADC_ADDR11 ADC_BA 0x2C R ADC Data Register 11 0x0000_0000 ADC_ADDR12 ADC_BA 0x30 R ADC Data Register 12 0x0000_0000 ADC_ADDR13 ADC_BA 0x34 R ADC Data Register 13 0x0000_0000 ADC_ADDR14 ADC_BA 0x38 R ADC Data Register 14 0x0000_0000 ADC_ADDR15 ADC_BA 0x3C R ADC Data Register 15 0x0000_0000 ADC_ADDR16 ADC_BA 0x40 R ADC Data Register 16 0x0000_0000...

Page 273: ...90 R W ADC Status Register0 0x0000_0000 ADC_ADSR1 ADC_BA 0x94 R ADC Status Register1 0x0000_0000 ADC_ADSR2 ADC_BA 0x98 R ADC Status Register2 0x0000_0000 ADC_ADTDCR ADC_BA 0x9C R W ADC Trigger Delay Control Register 0x0000_0000 ADC_ADPDMA ADC_BA 0x100 R ADC PDMA Current Transfer Data Register 0x0000_0000 ...

Page 274: ... ADC_BA 0x20 R ADC Data Register 8 0x0000_0000 ADC_ADDR9 ADC_BA 0x24 R ADC Data Register 9 0x0000_0000 ADC_ADDR10 ADC_BA 0x28 R ADC Data Register 10 0x0000_0000 ADC_ADDR11 ADC_BA 0x2C R ADC Data Register 11 0x0000_0000 ADC_ADDR12 ADC_BA 0x30 R ADC Data Register 12 0x0000_0000 ADC_ADDR13 ADC_BA 0x34 R ADC Data Register 13 0x0000_0000 ADC_ADDR14 ADC_BA 0x38 R ADC Data Register 14 0x0000_0000 ADC_ADD...

Page 275: ...in RSLT bits is valid 16 OVERRUN Overrun Flag Read Only If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1 It is cleared by hardware after ADDR register is read 0 Data in RSLT bits is not overwrote 1 Data in RSLT bits is overwrote 15 0 RSLT A D Conversion Result Read Only This field contains conversion result of ADC Note...

Page 276: ...0_0000_0000 0111_1111_1111 0 1 LSB Vref 4096 1111_1000_0000_0000 ADC result in RSLT 15 0 DMOF 1 1111_1000_0000_0001 1111_1000_0000_0010 0000_0111_1111_1111 0000_0111_1111_1110 0000_0111_1111_1101 Vref 1 LSB Vref 1 LSB Differential Input Voltage Vdiff V 0000_0000_0000_0001 0000_0000_0000_0000 1111_1111_1111_1111 0 1 LSB Vref 4096 Note Vref voltage comes from VREF AVDD Note Vref voltage comes from V...

Page 277: ...on cycle sampling cycle 12 000 4 ADC clock for sampling 16 ADC clock for complete conversion 001 5 ADC clock for sampling 17 ADC clock for complete conversion 010 6 ADC clock for sampling 18 ADC clock for complete conversion 011 7 ADC clock for sampling 19 ADC clock for complete conversion 100 8 ADC clock for sampling 20 ADC clock for complete conversion 101 9 ADC clock for sampling 21 ADC clock f...

Page 278: ...igger is enabled the ADST bit can be set to 1 by the selected hardware trigger source 0 External trigger Disabled 1 External trigger Enabled Note The ADC external trigger function is only supported in Single cycle Scan mode 7 6 TRGCOND External Trigger Condition These two bits decide external pin STADC trigger event is level or edge The signal must be kept at stable state at least 8 PCLKs for leve...

Page 279: ...3 NUC126 SERIES TECHNICAL REFERENCE MANUAL 0 A D converter Disabled 1 A D converter Enabled Note Before starting A D conversion function this bit should be set to 1 Clear it to 0 to disable A D converter analog circuit to save power consumption ...

Page 280: ...Enable Control Set ADCHER 19 0 bits to enable the corresponding analog input channel 19 0 If DIFFEN bit is set to 1 only the even number channel needs to be enabled Besides set ADCHER 29 to ADCHER 31 bits will enable internal channel for band gap voltage temperature sensor and battery power respectively Other bits are reserved 0 Channel Disabled 1 Channel Enabled Note1 If the internal channel for ...

Page 281: ... bit is only presented in ADCMPR0 register 14 12 Reserved Reserved 11 8 CMPMATCNT Compare Match Count When the specified A D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1 When the internal counter reaches the value to CMPMATCNT 1 the CMPFx bit will be set 7 3 CMPCH Compare Channel Selection 00000 Channel 0 conversio...

Page 282: ...er conversion result is selected to be compared Others Reserved 2 CMPCOND Compare Condition 0 Set the compare condition as that when a 12 bit A D conversion result is less than the 12 bit CMPD bits the internal match counter will increase one 1 Set the compare condition as that when a 12 bit A D conversion result is greater than or equal to the 12 bit CMPD bits the internal match counter will incr...

Page 283: ...et to 1 15 9 Reserved Reserved 8 VALIDF Data Valid Flag Read Only If any one of VALID ADDRx 17 is set this flag will be set to 1 Note When ADC is in burst mode and any conversion result is valid this flag will be set to 1 7 BUSY BUSY IDLE Read Only This bit is a mirror of ADST bit in ADCR register 0 A D converter is in idle state 1 A D converter is busy at conversion 6 3 Reserved Reserved 2 CMPF1 ...

Page 284: ...indicates the end of A D conversion Software can write 1 to clear this bit ADF bit is set to 1 at the following three conditions 1 When A D conversion ends in Single mode 2 When A D conversion ends on all specified channels in Single cycle Scan mode and Continuous Scan mode 3 When more than or equal to 8 samples in FIFO in Burst mode ...

Page 285: ...ster1 0x0000_0000 31 30 29 28 27 26 25 24 VALID 23 22 21 20 19 18 17 16 VALID 15 14 13 12 11 10 9 8 VALID 7 6 5 4 3 2 1 0 VALID Bits Description 31 0 VALID Data Valid Flag Read Only VALID 31 29 19 0 are the mirror of the VALID bits in ADDR31 17 ADDR29 17 ADDR19 17 ADDR0 17 The other bits are reserved Note When ADC is in burst mode and any conversion result is valid VALID 31 29 19 0 will be set to ...

Page 286: ...ter2 0x0000_0000 31 30 29 28 27 26 25 24 OVERRUN 23 22 23 22 19 18 17 16 OVERRUN 15 14 15 14 11 10 9 8 OVERRUN 7 6 5 4 3 2 1 0 OVERRUN Bits Description 31 0 OVERRUN Overrun Flag Read Only OVERRUN 31 29 19 0 are the mirror of the OVERRUN bit in ADDR31 16 ADDR29 16 ADDR19 16 ADDR0 16 The other bits are reserved Note When ADC is in burst mode and the FIFO is overrun OVERRUN 31 29 19 0 will be set to ...

Page 287: ...DC_ADTDCR ADC_BA 0x9C R W ADC Trigger Delay Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 PTDT Bits Description 31 8 Reserved Reserved 7 0 PTDT PWM Trigger Delay Time Set this field will delay ADC start conversion time after PWM trigger PWM trigger delay time is 4 PTDT system clock ...

Page 288: ...fer Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 23 22 19 18 17 16 Reserved CURDAT 15 14 15 14 11 10 9 8 CURDAT 7 6 5 4 3 2 1 0 CURDAT Bits Description 31 18 Reserved Reserved 17 0 CURDAT ADC PDMA Current Transfer Data Register Read Only When PDMA transferring read this register can monitor current PDMA transfer data Current PDMA transfer data could be the content of ADDR0 ADDR...

Page 289: ...rogrammable seed value Supports programmable order reverse setting for input data and CRC checksum Supports programmable 1 s complement setting for input data and CRC checksum Supports 8 16 32 bit of data width 8 bit write mode 1 AHB clock cycle operation 16 bit write mode 2 AHB clock cycle operation 32 bit write mode 4 AHB clock cycle operation Supports using PDMA to program DATA CRC_DAT 31 0 to ...

Page 290: ...le CRC generator by setting CRCEN CRC_CTL 0 2 Initial setting for CRC calculation Configure 1 s complement for CRC checksum by setting CHKSFMT CRC_CTL 27 Configure bit order reverse for CRC checksum by setting CHKSREV CRC_CTL 25 The funcitonal block is also shown in Figure 6 7 2 Configure 1 s complement for CRC write data by setting DATFMT CRC_CTL 26 Configure bit order reverse for CRC write data ...

Page 291: ...6 SERIES TECHNICAL REFERENCE MANUAL BIT31 Write Data Bit Order Reverse BIT30 BIT24 BIT7 BIT6 BIT0 BIT24 BIT25 BIT31 Bit Order Reverse per byte Bit Order Reverse per byte BIT0 BIT1 BIT7 MSB LSB Figure 6 7 3 Write Data Bit Order Reverse Functional Block ...

Page 292: ... both read and write Register Offset R W Description Reset Value CRC Base Address CRC_BA 0x5001_8000 CRC_CTL CRC_BA 0x00 R W CRC Control Register 0x2000_0000 CRC_DAT CRC_BA 0x04 R W CRC Write Data Register 0x0000_0000 CRC_SEED CRC_BA 0x08 R W CRC Seed Register 0xFFFF_FFFF CRC_CHECKSUM CRC_BA 0x0C R CRC Checksum Register 0xFFFF_FFFF ...

Page 293: ...DATLEN CPU Write Data Length This field indicates the valid write data length of DATA CRC_DAT 31 0 00 Data length is 8 bit mode 01 Data length is 16 bit mode 1x Data length is 32 bit mode Note When the write data length is 8 bit mode the valid data in CRC_DAT register is only DATA 7 0 bits if the write data length is 16 bit mode the valid data in CRC_DAT register is only DATA 15 0 27 CHKSFMT Check...

Page 294: ...sed to enable the bit order reverse function per byte for write data value DATA CRC_DATA 31 0 0 Bit order reversed for CRC DATA Disabled 1 Bit order reversed for CRC DATA Enabled per byte Note If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB 23 2 Reserved Reserved 1 CHKSINIT Checksum Initialization Set this bit will auto reolad SEED CRC_SEED 31 0 to CHECKSU...

Page 295: ... 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 7 6 5 4 3 2 1 0 DATA Bits Description 31 0 DATA CRC Write Data Bits User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation Note When the write data length is 8 bit mode the valid data in CRC_DAT register is only DATA 7 0 bits if the write data length is 16 bit mode the valid...

Page 296: ...0xFFFF_FFFF 31 30 29 28 27 26 25 24 SEED 23 22 21 20 19 18 17 16 SEED 15 14 13 12 11 10 9 8 SEED 7 6 5 4 3 2 1 0 SEED Bits Description 31 0 SEED CRC Seed Value This field indicates the CRC seed value Note1 This SEED value will be loaded to checksum initial value CHECKSUM CRC_CHECKSUM 31 0 after set CHKSINIT CRC_CTL 1 to 1 Note2 The valid bits of CRC_SEED 31 0 is correlated to CRCMODE CRC_CTL 31 30...

Page 297: ...ue CRC_CHECKSUM CRC_BA 0x0C R CRC Checksum Register 0xFFFF_FFFF 31 30 29 28 27 26 25 24 CHECKSUM 23 22 21 20 19 18 17 16 CHECKSUM 15 14 13 12 11 10 9 8 CHECKSUM 7 6 5 4 3 2 1 0 CHECKSUM Bits Description 31 0 CHECKSUM CRC Checksum Results This field indicates the CRC checksum result Note The valid bits of CRC_CHECKSUM 31 0 is correlated to CRCMODE CRC_CTL 31 30 ...

Page 298: ...orts address bus and data bus multiplex mode to save the address pins Supports two chip selects with polarity control Supports external devices with maximum 1 MB size for each chip select Supports variable external bus base clock MCLK which based on HCLK Supports 8 bit or 16 bit data width for each chip select Supports variable address latch enable time tALE Supports variable data access time tACC...

Page 299: ...AHDOFF EBI_ADR 19 16 EBI_nWRL EBI_nWRH Note x 0 or 1 CACCESS CSPOLINV Figure 6 8 1 EBI Block Diagram 6 8 4 Basic Configuration Clock Source Configuration Enable EBI peripheral clock in CLK_AHBCLK 3 Reset Configuration Reset EBI controller in EBIRST SYS_IPRST0 3 Pin Configuration The EBI Controller function pins are configured in SYS_GPA_MFPL SYS_GPB_MFPL SYS_GPB_MFPH SYS_GPC_MFPL SYS_GPD_MFPL SYS_...

Page 300: ... 2 PD 8 PE 4 MFP7 EBI_nCS1 PB 15 PE 0 MFP7 EBI_nRD PD 1 PD 7 MFP7 EBI_nWR PD 2 PD 6 MFP7 EBI_nWRH PB 1 MFP7 EBI_nWRL PB 0 MFP7 6 8 5 Functional Description 6 8 5 1 EBI Area and Address Hit The EBI memory mapping address is located at 0x6000_0000 0x601F_FFFF and the total memory space is 2 MB which split into EBI bank0 and bank1 Table 6 8 1 shows the EBI memory mapping of bank0 and bank1 When syste...

Page 301: ... the latch device to latch the address value EBI_AD pins are the input of the latch device and the output of the latch device is connected to the address of external device Figure 6 8 2 shows an example for the connection of 16 bit device with 16 bit data width For 16 bit device the EBI_AD 15 0 shared by Addr 15 0 and 16 bit Data 15 0 EBI_ADR 18 16 is dedicated for Addr 18 16 and could be connecte...

Page 302: ...9 16 Addr 19 16 Note x 0 or 1 Figure 6 8 3 Connection of 8 bit Device with 8 bit EBI Data Width When system access data width is larger than EBI data width setting EBI controller will finish a system access command by operating EBI access with data width setting more than once For example if system requests a 32 bit data access through EBI device and data width in EBI controller is 8 bit EBI contr...

Page 303: ...After that EBI signals keep for data access hold time tAHD and chip select asserts to high address is released by current access control Figure 6 8 4 and Figure 6 8 5 shows the timing control waveform for 16 bit data width and 8 bit data width The EBI controller provides a flexible timing control for different external device In EBI timing control tASU tLHD and tA2D are fixed to one EBI_MCLK cycle...

Page 304: ...write data output EBI_nCSx EBI_AD 15 0 EBI_MCLK EBI_nRD tACC tASU tAHD EBI_nWR EBI_AD 15 0 EBI_ALE tALE tLHD tA2D Address output 15 0 WData output 15 0 RData input Address output 15 0 EBI_ADR 18 16 Address output 18 16 EBI_ADR 18 16 Address output 18 16 Note1 TALE is 1 TACC is 2 TAHD is 1 and access command width is 16 bit read and write Note2 x 0 or 1 Figure 6 8 4 Timing Control Waveform for 16 b...

Page 305: ... tLHD tA2D Address output 7 0 WData output 7 0 RData input Address output 7 0 EBI_AD 15 8 Address output 15 8 EBI_AD 15 8 Address output 15 8 EBI_ADR 19 16 Address output 19 16 EBI_ADR 19 16 Address output 19 16 Note1 TALE is 1 TACC is 2 TAHD is 1 and access command width is 8 bit read and write Note2 x 0 or 1 Figure 6 8 5 Timing Control Waveform for 8 bit Data Width ...

Page 306: ...C is 2 TAHD is 1 and access command width is 16 bit read and write Note2 x 0 or 1 Figure 6 8 6 Timing Control Waveform for Insert Idle Cycle Chip Select Polarity Control EBI controller supports chip select polarity control for connecting to variable external device When CSPOLINV EBI_CTLx 2 is set to 0 the chip select pins EBI_nCSx works as low active behavior It means the external device can be ac...

Page 307: ...AHD EBI_nWR EBI_AD 15 0 tACC tAHD tA2D Wdata output 15 0 RData input tACC tAHD tA2D Wdata output 15 0 RData input RData input Wdata output 15 0 Idle cycle XX Note1 TACC is 1 TAHD is 1 CACCESS is enabled and access command width is 32 bit read and write Note2 x 0 or 1 Figure 6 8 7 Timing Control Waveform for Continuous Data Access Mode ...

Page 308: ...t Value EBI Base Address EBI_BA 0x5001_0000 EBI_CTL0 EBI_BA 0x00 R W External Bus Interface Bank0 Control Register 0x0000_0000 EBI_TCTL0 EBI_BA 0x04 R W External Bus Interface Bank0 Timing Control Register 0x0000_0000 EBI_CTL1 EBI_BA 0x10 R W External Bus Interface Bank1 Control Register 0x0000_0000 EBI_TCTL1 EBI_BA 0x14 R W External Bus Interface Bank1 Timing Control Register 0x0000_0000 ...

Page 309: ...V DW16 EN Bits Description 31 19 Reserved Reserved 18 16 TALE Extend Time of ALE The EBI_ALE high pulse period tALE to latch the address can be controlled by TALE tALE TALE 1 EBI_MCLK Note This field only available in EBI_CTL0 register 15 11 Reserved Reserved 10 8 MCLKDIV External Output Clock Divider The frequency of EBI output clock MCLK is controlled by MCLKDIV as follow 000 HCLK 1 001 HCLK 2 0...

Page 310: ... select pin EBI_nCSx x 0 or 1 0 Chip select pin EBI_nCSx is active low 1 Chip select pin EBI_nCSx is active high 1 DW16 EBI Data Width 16 bit Select This bit defines if the EBI data width is 8 bit or 16 bit 0 EBI data width is 8 bit 1 EBI data width is 16 bit 0 EN EBI Enable Bit This bit is the functional enable bit for EBI 0 EBI function Disabled 1 EBI function Enabled ...

Page 311: ...sh and next action is going to read R2R idle cycle is inserted and EBI_nCSx return to idle state x 0 or 1 R2R idle cycle R2R EBI_MCLK 23 WAHDOFF Access Hold Time Disable Control When Write 0 Data Access Hold Time tAHD during EBI writing Enabled 1 Data Access Hold Time tAHD during EBI writing Disabled 22 RAHDOFF Access Hold Time Disable Control When Read 0 Data Access Hold Time tAHD during EBI read...

Page 312: ...NUC126 Aug 08 2018 Page 312 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL tACC TACC 1 EBI_MCLK 2 0 Reserved Reserved ...

Page 313: ...rectional mode After the chip is reset the I O mode of all pins are depending on CIOIN CONFIG0 10 Each I O pin has a very weakly individual pull up resistor which is about 110 k 300 k for VDD is from 5 0 V to 2 5 V 6 9 2 Features Four I O modes Quasi bidirectional mode Push Pull Output mode Open Drain Output mode Input only with high impendence mode TTL Schmitt trigger input selectable I O pin can...

Page 314: ... Register PB 15 0 Control Register PC 15 0 Control Register PD 15 0 Control Register PE 15 0 Control Register PF 7 0 Control Register De bounce Control Register Control Registers Interrupt Wake up Event Detector PB 15 0 PC 15 0 PD 15 0 PE 15 0 PF 7 0 GPIO_INT Figure 6 9 1 GPIO Controller Block Diagram Note The PE 14 PE 15 pin is ignored ...

Page 315: ...LK 20 GPIOFCKEN CLK_AHBCLK 21 000 001 010 011 100 111 HIRC Figure 6 9 2 GPIO Clock Control Diagram 6 9 4 Basic Configuration Clock Source Configuration Enable GPIO peripheral clock in CLK_AHBCLK 21 16 Reset Configuration Reset GPIO controller in GPIORST SYS_IPRST1 1 Pin Configuration The GPIO pin functions are configured in SYS_PA_MFPL SYS_PA_MFPH SYS_PB_MFPL SYS_PB_MFPH SYS_PC_MFPL SYS_PC_MFPH SY...

Page 316: ...Input Data Figure 6 9 3 Open Drain Output 6 9 5 4 Quasi bidirectional Mode Set MODEn Px_MODE 2n 1 2n to 11 as the Px n pin is in Quasi bidirectional mode and the I O pin supports digital output and input function at the same time but the source current is only up to hundreds uA Before the digital input function is performed the corresponding DOUT Px_DOUT n bit must be set to 1 The quasi bidirectio...

Page 317: ...r and both rising and falling edge trigger For edge trigger condition user can enable input signal de bounce function to prevent unexpected interrupt happened which caused by noise The de bounce clock source and sampling cycle period can be set through DBCLKSRC GPIO_DBCTL 4 and DBCLKSEL GPIO_DBCTL 3 0 register The GPIO can also be the chip wake up source when chip enters Idle Power down mode The s...

Page 318: ...SLEWCTL GPIO_BA 0x028 R W PA High Slew Rate Control 0x0000_0000 PB_MODE GPIO_BA 0x040 R W PB I O Mode Control 0xXXXX_XXXX PB_DINOFF GPIO_BA 0x044 R W PB Digital Input Path Disable Control 0x0000_0000 PB_DOUT GPIO_BA 0x048 R W PB Data Output Value 0x0000_FFFF PB_DATMSK GPIO_BA 0x04C R W PB Data Output Write Mask 0x0000_0000 PB_PIN GPIO_BA 0x050 R PB Pin Value 0x0000_XXXX PB_DBEN GPIO_BA 0x054 R W P...

Page 319: ... W PD Interrupt Enable Control 0x0000_0000 PD_INTSRC GPIO_BA 0x0E0 R W PD Interrupt Source Flag 0x0000_XXXX PD_SMTEN GPIO_BA 0x0E4 R W PD Input Schmitt Trigger Enable 0x0000_0000 PD_SLEWCTL GPIO_BA 0x0E8 R W PD High Slew Rate Control 0x0000_0000 PE_MODE GPIO_BA 0x100 R W PE I O Mode Control 0xXXXX_XXXX PE_DINOFF GPIO_BA 0x104 R W PE Digital Input Path Disable Control 0x0000_0000 PE_DOUT GPIO_BA 0x...

Page 320: ...XX PF_SMTEN GPIO_BA 0x164 R W PF Input Schmitt Trigger Enable 0x0000_0000 PF_SLEWCTL GPIO_BA 0x168 R W PF High Slew Rate Control 0x0000_0000 GPIO_DBCTL GPIO_BA 0x180 R W Interrupt De bounce Control 0x0000_0020 PAn_PDIO n 0 1 15 GPIO_BA 0x200 0x04 n R W GPIO PA n Pin Data Input Output 0x0000_000X PBn_PDIO n 0 1 15 GPIO_BA 0x240 0x04 n R W GPIO PB n Pin Data Input Output 0x0000_000X PCn_PDIO n 0 1 1...

Page 321: ...29 28 27 26 25 24 MODE n 23 22 21 20 19 18 17 16 MODE n 15 14 13 12 11 10 9 8 MODE n 7 6 5 4 3 2 1 0 MODE n Bits Description 2n 1 2n n 0 1 15 MODE n Port A f I O Pin n Mode Control Determine each I O mode of Px n pins 00 Px n is in Input mode 01 Px n is in Push pull Output mode 10 Px n is in Open drain Output mode 11 Px n is in Quasi bidirectional mode Note1 The initial value of this field is defi...

Page 322: ...nput Path Disable Control 0x0000_0000 PF_DINOFF GPIO_BA 0x144 R W PF Digital Input Path Disable Control 0x0000_0000 31 30 29 28 27 26 25 24 DINOFF n 23 22 21 20 19 18 17 16 DINOFF n 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description n 16 n 0 1 15 DINOFF n Port A f Pin n Digital Input Path Disable Control Each of these bits is used to control if the digital input path of corre...

Page 323: ...Data Output Value 0x0000_00FF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DOUT n 7 6 5 4 3 2 1 0 DOUT n Bits Description 31 16 Reserved Reserved n n 0 1 15 DOUT n Port A f Pin n Output Value Each of these bits controls the status of a Px n pin when the Px n is configured as Push pull output Open drain output or Quasi bidirectional mode 0 Px n will drive ...

Page 324: ...1 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DATMSK n 7 6 5 4 3 2 1 0 DATMSK n Bits Description 31 16 Reserved Reserved n n 0 1 15 DATMSK n Port A f Pin n Data Output Write Mask These bits are used to protect the corresponding DOUT Px_DOUT n bit When the DATMSK Px_DATMSK n bit is set to 1 the corresponding DOUT Px_DOUT n bit is protected If the write signa...

Page 325: ...IN GPIO_BA 0x110 R PE Pin Value 0x0000_XXXX PF_PIN GPIO_BA 0x150 R PF Pin Value 0x0000_00XX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PIN n 7 6 5 4 3 2 1 0 PIN n Bits Description 31 16 Reserved Reserved n n 0 1 15 PIN n Port A f Pin n Pin Value Each bit of the register reflects the actual status of the respective Px n pin If the bit is 1 it indicates t...

Page 326: ... 9 8 DBEN n 7 6 5 4 3 2 1 0 DBEN n Bits Description 31 16 Reserved Reserved n n 0 1 15 DBEN n Port A f Pin n Input Signal De bounce Enable Bit The DBEN n bit is used to enable the de bounce function for each corresponding bit If the input signal pulse width cannot be sampled by continuous two de bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the i...

Page 327: ...n Bits Description 31 16 Reserved Reserved n n 0 1 15 TYPE n Port A f Pin n Edge or Level Detection Interrupt Trigger Type Control TYPE Px_INTTYPE n bit is used to control the triggered interrupt is by level trigger or by edge trigger If the interrupt is by edge trigger the trigger source can be controlled by de bounce If the interrupt is by level trigger the input source is sampled by one HCLK cl...

Page 328: ...tion When setting the RHIEN Px_INTEN n 16 bit to 1 If the interrupt is level trigger TYPE Px_INTTYPE n bit is set to 1 the input Px n pin will generate the interrupt while this pin state is at high level If the interrupt is edge trigger TYPE Px_INTTYPE n bit is set to 0 the input Px n pin will generate the interrupt while this pin state changed from low to high 0 Px n level high or low to high int...

Page 329: ...v 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 0 Px n level low or high to low interrupt Disabled 1 Px n level low or high to low interrupt Enabled Note1 Max n 15 for port A B C D E Max n 7 for port F Note2 The PE 14 PE 15 pin is ignored ...

Page 330: ...t Source Flag 0x0000_XXXX PE_INTSRC GPIO_BA 0x120 R W PE Interrupt Source Flag 0x0000_XXXX PF_INTSRC GPIO_BA 0x160 R W PF Interrupt Source Flag 0x0000_00XX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 INTSRC n 7 6 5 4 3 2 1 0 INTSRC n Bits Description 31 16 Reserved Reserved n n 0 1 15 INTSRC n Port A f Pin n Interrupt Source Flag Write Operation 0 No act...

Page 331: ... 0x0E4 R W PD Input Schmitt Trigger Enable 0x0000_0000 PE_SMTEN GPIO_BA 0x124 R W PE Input Schmitt Trigger Enable 0x0000_0000 PF_SMTEN GPIO_BA 0x164 R W PF Input Schmitt Trigger Enable 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 SMTEN n 7 6 5 4 3 2 1 0 SMTEN n Bits Description 31 16 Reserved Reserved n n 0 1 15 SMTEN n Port A f Pin n Input Sc...

Page 332: ..._SLEWCTL GPIO_BA 0x0E8 R W PD High Slew Rate Control 0x0000_0000 PE_SLEWCTL GPIO_BA 0x128 R W PE High Slew Rate Control 0x0000_0000 PF_SLEWCTL GPIO_BA 0x168 R W PF High Slew Rate Control 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 HSREN n 7 6 5 4 3 2 1 0 HSREN n Bits Description 31 16 Reserved Reserved n n 0 1 15 HSREN n Port A f Pin n High S...

Page 333: ... PE High Drive Strength Control 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved HDRVEN n 7 6 5 4 3 2 1 0 Reserved Bits Description 31 14 Reserved Reserved n n 8 9 13 HDRVEN n Port E Pin n Driving Strength Control 0 Px n output with basic driving strength 1 Px n output with high driving strength Note n 8 9 13 for port E 7 0 Reserved Reser...

Page 334: ...ck Source Selection 0 De bounce counter clock source is the HCLK 1 De bounce counter clock source is the internal 10 kHz internal low speed oscillator 3 0 DBCLKSEL De bounce Sampling Cycle Selection 0000 Sample interrupt input once per 1 clocks 0001 Sample interrupt input once per 2 clocks 0010 Sample interrupt input once per 4 clocks 0011 Sample interrupt input once per 8 clocks 0100 Sample inter...

Page 335: ...Output 0x0000_000X PFn_PDIO n 0 1 7 GPIO_BA 0x340 0x04 n R W GPIO PF n Pin Data Input Output 0x0000_000X 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PDIO Bits Description 31 1 Reserved Reserved 0 PDIO GPIO Px N Pin Data Input Output Writing this bit can control one GPIO pin output value 0 Corresponding GPIO pin set to lo...

Page 336: ...ends to 32 bit Divided by zero warning flag 6 HCLK clocks taken for one cycle calculation Write divisor to trigger calculation Waiting for calculation ready automatically when reading quotient and remainder 6 10 3 Blcok Diagram Divider Calculation Digital Control Logic Dividend Source Register DIVIDEND Divisor Source Register DIVISOR Quotient Result Register DIVQUO Sign extension Divider Status Re...

Page 337: ...nteger and divisor is 16 bit signed integer The quotient is 32 bit signed integer and the remainder is 16 bit signed integer It is noted that the case of dividing the minimum dividend by 1 the quotient is set to be the minimum negative value since overflow and the remainder is set to 0 This is the only case the quotient is not represented in a positive number when a negative number by a negative n...

Page 338: ...ion Reset Value HDIV Base Address HDIV_BA 0x5001_4000 HDIV_DIVIDEND HDIV_BA 0x00 R W Dividend Source Register 0x0000_0000 HDIV_DIVISOR HDIV_BA 0x04 R W Divisor Source Resister 0x0000_FFFF HDIV_DIVQUO HDIV_BA 0x08 R W Quotient Result Resister 0x0000_0000 HDIV_DIVREM HDIV_BA 0x0C R W Remainder Result Register 0x0000_0000 HDIV_DIVSTS HDIV_BA 0x10 R Divider Status Register 0x0000_0001 ...

Page 339: ...egister Offset R W Description Reset Value HDIV_DIVIDEND HDIV_BA 0x00 R W Dividend Source Register 0x0000_0000 31 30 29 28 27 26 25 24 DIVIDEND 23 22 21 20 19 18 17 16 DIVIDEND 15 14 13 12 11 10 9 8 DIVIDEND 7 6 5 4 3 2 1 0 DIVIDEND Bits Description 31 0 DIVIDEND Dividend Source This register is given the dividend of divider before calculation starting ...

Page 340: ...V_BA 0x04 R W Divisor Source Resister 0x0000_FFFF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DIVISOR 7 6 5 4 3 2 1 0 DIVISOR Bits Description 31 16 Reserved Reserved 15 0 DIVISOR Divisor Source This register is given the divisor of divider before calculation starts Note When this register is written hardware divider will start calculate ...

Page 341: ...R W Description Reset Value HDIV_DIVQUO HDIV_BA 0x08 R W Quotient Result Resister 0x0000_0000 31 30 29 28 27 26 25 24 QUOTIENT 23 22 21 20 19 18 17 16 QUOTIENT 15 14 13 12 11 10 9 8 QUOTIENT 7 6 5 4 3 2 1 0 QUOTIENT Bits Description 31 0 QUOTIENT Quotient Result This register holds the quotient result of divider after calculation complete ...

Page 342: ...REMAINDER 23 22 21 20 19 18 17 16 REMAINDER 15 14 13 12 11 10 9 8 REMAINDER 7 6 5 4 3 2 1 0 REMAINDER Bits Description 31 0 REMAINDER Remainder Result The remainder of hardware divider is 16 bit sign integer REMAINDER 15 0 which holds the remainder result of divider after calculation complete The remainder of hardware divider with sign extension REMAINDER 31 16 to 32 bit integer This register hold...

Page 343: ...14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DIV0 FINISH Bits Description 31 2 Reserved Reserved 1 DIV0 Divisor Zero Warning 0 The divisor is not 0 1 The divisor is 0 Note The DIV0 flag is used to indicate divide by zero situation and updated whenever DIVISOR is written This register is read only 0 FINISH Division Finish Flag 0 Under Calculation 1 Calculation finished The flag will become ...

Page 344: ... C bus include Supports up to two I 2 C ports Master Slave mode Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allow devices with different bit rates to communicate via one serial bus Serial clock synchronization used as a hand...

Page 345: ...guration 6 11 4 1 Basic Configuration of I2C0 Clock Source Configuration Enable I2C0 peripheral clock in I2C0CKEN CLK_APBCLK0 8 Reset Configuration Reset I2C0 controller in I2C0RST SYS_IPRST1 8 Pin Configuration Group Pin Name GPIO MFP I2C0 I2C0_SCL PE 4 PE 6 MFP2 PD 5 MFP3 PA 3 PE 12 MFP4 I2C0_SDA PE 5 PE 7 MFP2 PD 4 MFP3 PA 2 PE 13 MFP4 6 11 4 2 Basic Configuration of I2C1 Clock Source Configura...

Page 346: ... DAT Repeated START tSU STA tSU STO STOP tr Figure 6 11 2 I 2 C Bus Timing The device s on chip I 2 C provides the serial interface that meets the I 2 C bus standard mode specification The I 2 C port handles byte transfers autonomously To enable this port the bit I2CEN in I2C_CTL 6 should be set to 1 The I 2 C hardware interfaces to the I 2 C bus via two pins SDA and SCL When I O pins are used as ...

Page 347: ...more devices without releasing the bus and thus with the guarantee that the operation is not interrupted The controller uses this method to communicate with another slave or the same slave in a different transfer direction e g from writing to a device to reading from a device without releasing the bus STOP Signal The master can terminate the communication by generating a STOP signal A STOP signal ...

Page 348: ...wledge NACK the slave the slave releases the SDA line for the master to generate a STOP or Repeated START signal SDA SCL Data line stable data valid Change of data allowed Figure 6 11 5 Bit Transfer on the I 2 C Bus Data output by transmitter SCL from master START condition acknowlegde Data output by receiver S 1 2 8 9 Clock pulse for acknowledgement not acknowlegde Figure 6 11 6 Acknowledge on th...

Page 349: ...ter and slave devices if interrupt is enabled When the microcontroller wishes to become the bus master hardware waits until the bus is free before entering Master mode so that a possible slave action is not be interrupted If bus arbitration is lost in Master mode I 2 C port switches to Slave mode immediately and can detect its own slave address in the same serial transfer To control the I 2 C bus ...

Page 350: ...TOP to perform I 2 C protocol S I2C_DAT SLA W ACK NAK Master to Slave Slave to Master I2C_DAT Data ACK NAK Sr P P S STATUS 0x08 STA STO SI AA 1 0 1 x ACK STATUS 0x18 NAK STATUS 0x20 I2C_DAT SLA W STA STO SI AA 0 0 1 x ACK STATUS 0x28 NAK STATUS 0x30 I2C_DAT Data STA STO SI AA 0 0 1 x STATUS 0x10 STA STO SI AA 1 0 1 x STATUS 0xF8 STA STO SI AA 0 1 1 x STATUS 0x08 STA STO SI AA 1 1 1 x I2C_DAT SLA W...

Page 351: ... 11 Master Receiver Mode Control Flow If the I 2 C is in Master mode and gets arbitration lost the status code will be 0x38 In status 0x38 user may set STA STO SI AA 1 0 1 X to send START to re start Master operation when bus become free Otherwise user may set STA STO SI AA 0 0 1 X to release I 2 C bus and enter not addressed Slave mode Slave Mode When reset default I 2 C is not addressed and will...

Page 352: ...T Data STA STO SI AA 0 0 1 X I2C_DAT Data STA STO SI AA 0 0 1 X STA STO SI AA 0 0 1 1 Sr STA STO SI AA 0 0 1 1 STA STO SI AA 0 0 1 X STA STO SI AA 0 0 1 X I2C_DAT SLA W I2C_DAT SLA R ACK ACK Figure 6 11 12 Slave Mode Control Flow If I 2 C is still receiving data in addressed Slave mode but got a STOP or Repeat START the status code will be 0xA0 User could follow the action for status code 0x88 as ...

Page 353: ...A0 Sr STATUS 0xA0 P Sr STA STO SI AA 0 0 1 1 Sr STA STO SI AA 0 0 1 X STA STO SI AA 0 0 1 X I2C_DAT SLA W 0x00 ACK Figure 6 11 13 GC Mode If I 2 C is still receiving data in GC mode but got a STOP or Repeat START the status code will be 0xA0 User could follow the action for status code 0x98 in Figure 6 11 13 when getting 0xA0 status Note After slave gets status of 0x98 and 0xA0 slave can switch to...

Page 354: ...STATUS1 8 When I2C_STATUS 0x00 a Bus Error is received To recover I 2 C bus from a bus error STO should be set and SI should be cleared and then STO is cleared to release bus Set STA STO SI AA 0 1 1 X to stop current transfer Set STA STO SI AA 0 0 1 X to release bus 6 11 5 3 PDMA Transfer Function I 2 C controller supports PDMA transfer function When TXPDMAEN I2C_CTL1 0 is set to 1 the controller ...

Page 355: ...6 Data0 Data2 Interrupt T7 T9 T10 Clear Data1 Interrupt flag Clear Data2 Interrupt flag T14 Data1 T5 Read Data0 from buffer T8 Read Data1 from buffer Data2 T11 Read Data2 from buffer T12 Clear Data3 Interrupt flag T15 Read Data3 from buffer STA Data0 Data3 STO User command HW Event Time Sequence Data1 Data2 Data3 Interrupt Data3 T13 Figure 6 11 16 Timing of Two level Buffer Transmit in Slave Read ...

Page 356: ...PCLK Only two PCLKs Two PCLKs can not sample for SCL Figure 6 11 17 Setup Time Wrong Adjustment For hold time wrong adjustment example we use I 2 C Baud Rate 1200k and PCLK 72MHz the SCL high low duty 60 PCLK When we set HTCTL 5 0 I2C_TMCTL 11 6 to 61 and STCTL 5 0 I2C_TMCTL 5 0 to 0 then SDA output delay will over SCL high duty and cause bus error The hold time setting limitation HTlimit I2C_CLKD...

Page 357: ...ined state and the serial interrupt flag SI is set data in I2C_DAT 7 0 remains stable While data is being shifted out data on the bus is simultaneously being shifted in I2C_DAT 7 0 always contains the last data byte presented on the bus The acknowledge bit is controlled by the I 2 C hardware and cannot be accessed by the CPU Serial data is shifted into I2C_DAT 7 0 on the rising edges of serial clo...

Page 358: ...ddress ACK 0xB8 1 Slave Transmit Data ACK 0x20 Master Transmit Address NACK 0xC0 Slave Transmit Data NACK 0x28 1 Master Transmit Data ACK 0xC8 1 Slave Transmit Last Data ACK 0x30 Master Transmit Data NACK 0x60 1 Slave Receive Address ACK 0x38 Master Arbitration Lost 0x68 1 Slave Receive Arbitration Lost 0x40 1 Master Receive Address ACK 0x80 1 Slave Receive Data ACK 0x48 Master Receive Address NAC...

Page 359: ... will perform immediately If data transmitted or received when SI event is not clear user must reset I 2 C controller and execute the original operation again Wake up Status Register I2C_WKSTS When system is woken up by other I 2 C master device WKIF I2C_WKSTS 0 is set to indicate this event User needs write 1 to clear this bit When the chip is woken up by address match with one of the device addr...

Page 360: ... and overrun or under run are also list in the this register I 2 C Timing Configure Control Register I2C_TMCTL To configure setup hold time the HTCTL 5 0 I2C_TMCTL 11 6 and STCTL 5 0 I2C_TMCTL 5 0 are set based on actual demand 6 11 5 7 Example for Random Read on EEPROM The following steps are used to configure the I 2 C0 related registers when using I 2 C to read data from EEPROM 1 Set I 2 C0 the...

Page 361: ...AT ROM Address High Byte STA STO SI AA 0 0 1 x STATUS 0x10 STA STO SI AA 1 0 1 x STATUS 0xf8 STA STO SI AA 0 1 1 x I2C_DAT SLA R STA STO SI AA 0 0 1 x STATUS 0x40 NAK STATUS 0x20 I2C_DAT ROM Address Low Byte ACK STATUS 0x28 I2C_DAT ROM Address Low Byte STA STO SI AA 0 0 1 x P STATUS 0xf8 STA STO SI AA 0 1 1 x NAK STATUS 0x30 I2C_DAT Data NAK STATUS 0x58 Read I2C_DAT to Get Data STA STO SI AA 0 0 1...

Page 362: ..._ADDR1 I2Cx_BA 0x18 R W I2 C Slave Address Register1 0x0000_0000 I2C_ADDR2 I2Cx_BA 0x1C R W I2 C Slave Address Register2 0x0000_0000 I2C_ADDR3 I2Cx_BA 0x20 R W I2 C Slave Address Register3 0x0000_0000 I2C_ADDRMSK0 I2Cx_BA 0x24 R W I2 C Slave Address Mask Register0 0x0000_0000 I2C_ADDRMSK1 I2Cx_BA 0x28 R W I2 C Slave Address Mask Register1 0x0000_0000 I2C_ADDRMSK2 I2Cx_BA 0x2C R W I2 C Slave Addres...

Page 363: ...aster mode the I2 C hardware sends a START or repeat START condition to bus when the bus is free 4 STO I2 C STOP Control In Master mode setting STO to transmit a STOP condition to bus then I2 C controller will check the bus condition if a STOP condition is detected This bit will be cleared by hardware automatically 3 SI I2 C Interrupt Flag When a new I2 C state is present in the I2C_STATUS registe...

Page 364: ...Description Reset Value I2C_DAT I2Cx_BA 0x08 R W I2 C Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DAT Bits Description 31 8 Reserved Reserved 7 0 DAT I2 C Data Bit 7 0 is located with the 8 bit transferred received data of I2 C serial port ...

Page 365: ...its contain the status code There are 28 possible status codes When the content of I2C_STATUS is F8H no serial interrupt is requested Others I2C_STATUS values correspond to defined I2 C states When each of these states is entered a status interrupt is requested SI 1 A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been r...

Page 366: ...KDIV I2Cx_BA 0x10 R W I2 C Clock Divided Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DIVIDER Bits Description 31 8 Reserved Reserved 7 0 DIVIDER I2 C Clock Divided Indicates the I2 C clock rate Data Baud Rate of I2 C system clock 4x I2C_CLKDIV 1 Note The minimum value of I2C_CLKDIV is 4 ...

Page 367: ... Time out Counter Enable Bit When Enabled the 14 bit time out counter will start counting when SI is clear Setting flag SI to 1 will reset counter and re start up counting after SI is cleared 0 Time out counter Disabled 1 Time out counter Enabled 1 TOCDIV4 Time out Counter Input Clock Divided by 4 When Enabled The time out period is extend 4 times 0 Time out period is extend 4 times Disabled 1 Tim...

Page 368: ...2C_ADDR3 I2Cx_BA 0x20 R W I2 C Slave Address Register3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 ADDR GC Bits Description 31 8 Reserved Reserved 7 1 ADDR I2 C Address The content of this register is irrelevant when I2 C is in Master mode In the slave mode the seven most significant bits must be loaded with the chip ...

Page 369: ... 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 ADDRMSK Reserved Bits Description 31 8 Reserved Reserved 7 1 ADDRMSK I2 C Address Mask 0 Mask Disabled the received corresponding register bit should be exact the same as address register 1 Mask Enabled the received corresponding address bit is don t care I2 C bus controllers support multiple address recog...

Page 370: ...NHDBUSEN Reserved WKEN Bits Description 31 8 Reserved Reserved 7 NHDBUSEN I2 C No Hold BUS Enable Bit 0 I2 C don t hold bus after wake up disable 1 I2 C don t hold bus after wake up enable Note I2 C controller could response when WKIF event is not clear it may cause error data transmitted or received If data transmitted or received when WKIF event is not clear user must reset I2 C controller and e...

Page 371: ...WRSTSWK Read Write Status Bit in Address Wakeup Frame 0 Write command be record on the address match wakeup frame 1 Read command be record on the address match wakeup frame Note This bit will be cleared when software can write 1 to WKAKDONE bit 1 WKAKDONE Wakeup Address Frame Acknowledge Bit Done 0 The ACK bit cycle of address match frame isn t done 1 The ACK bit cycle of address match frame is do...

Page 372: ...level Buffer Reset 0 No effect 1 Reset the related counters two level buffer state machine and the content of data buffer 5 TWOBUFEN Two level Buffer Enable Bit 0 Two level buffer Disabled 1 Two level buffer Enabled Set to enable the two level buffer for I2 C transmitted or received buffer It is used to improve the performance of the I2 C bus If this bit is set 1 the control bit of STA for repeat ...

Page 373: ...t 0 No effect 1 Reset the PDMA control logic This bit will be cleared to 0 automatically 1 RXPDMAEN PDMA Receive Channel Available 0 Receive PDMA function Disabled 1 Receive PDMA function Enabled 0 TXPDMAEN PDMA Transmit Channel Available 0 Transmit PDMA function Disabled 1 Transmit PDMA function Enabled ...

Page 374: ...n a START condition is detected It is cleared by hardware when a STOP condition is detected 0 The bus is IDLE both SCLK and SDA High 1 The bus is busy 7 UDR I2 C Under Run Status Bit This bit indicates the transmitted two level buffer TX or RX is under run when the TWOBUFEN 1 6 OVR I2 C over Run Status Bit This bit indicates the received two level buffer TX or RX is over run when the TWOBUFEN 1 5 ...

Page 375: ... HTCTL STCTL Bits Description 31 12 Reserved Reserved 11 6 HTCTL Hold Time Configure Control Register This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode The delay hold time is numbers of peripheral clock HTCTL x PCLK 5 0 STCTL Setup Time Configure Control Register This field is used to generate a delay timing between SDA falling edge a...

Page 376: ...n priority Supports transfer data width of 8 16 and 32 bits Supports source and destination address increment size can be byte half word word or no increment Supports software and SPI UART I 2 S I 2 C USB ADC PWM and TIMER request Supports Scatter Gather mode to perform sophisticated transfer through the use of the descriptor link list table Supports single and burst transfer type Supports time ou...

Page 377: ...x30 0x40 Figure 6 12 2 Descriptor Table Entry Structure The PDMA controller also supports single and burst transfer type and the request source can be from software or peripheral request transfer between memory to memory using software request A single transfer means that software or peripheral is ready to transfer one data every data needs one request and the burst transfer means that software or...

Page 378: ...sfer width TXWIDTH PDMA_DSCTn_CTL 13 12 destination address increment size DAINC PDMA_DSCTn_CTL 11 10 source address increment size SAINC PDMA_DSCTn_CTL 9 8 burst size BURSIZE PDMA_DSCTn_CTL 6 4 and transfer type TXTYPE PDMA_DSCTn_CTL 2 then the PDMA controller will perform transfer operation in transfer state after receiving request signal Finishing this task will generate an interrupt to CPU if ...

Page 379: ... 1 0 0x2 the hardware will load the real PDMA information task from the address generated by adding PDMA_DSCTn_FIRST link offset and PDMA_SCATBA base address registers The base address is 0x2000_0000 only MSB 16bits valid in PDMA_SCATBA the first link offset is 0x0000_0100 only LSB 16bits in PDMA_DSCTn_FIRST then current DSCT entry PDMA_CURSCAT4 will update to address 0x2000_0100 and copy DSCT_CTL...

Page 380: ...s DSCT state in Scatter Gather Mode as shown in Figure 6 12 5 When loading the information is finished it will go to transfer state and start transfer by this information automatically However if the next PDMA information is also in the Scatter Gather mode the hardware will catch the next PDMA information block when the current task is finished The Scatter Gather mode stops until the PDMA controll...

Page 381: ...4 0 After transferred BURSIZE PDMA_DSCTn_CTL 6 4 of data TXCNT PDMA_DSCTn_CTL 29 16 will decrease BURSIZE number Transfer task will done until the transfer count TXCNT PDMA_DSCTn_CTL 29 16 decrease to 0 Note that burst transfer type can only be used for PDMA controller to do burst transfer between memory and memory User must use single request type for memory to peripheral and peripheral to memory...

Page 382: ... 4n n 0 1 If time out counter counts up from 0 to corresponding channel s TOCn PDMA_TOC0_1 16 n 1 1 16n n 0 1 the PDMA controller will generate interrupt signal when corresponding TOUTIENn PDMA_TOUTIEN n n 0 1 is enabled When time out occurred corresponding channel s REQTOFn PDMA_INTSTS n 8 n 0 1 will be set to indicate channel time out is happened Time out counter reset to 0 while counter count t...

Page 383: ...EFERENCE MANUAL Time out counter TOC0 PDMA_TOC0_1 15 0 TOUTEN0 PDMA_TOUTEN 0 1 2 3 4 5 0 1 2 3 0 5 0 1 2 3 0 x Peripheral request REQTOF0 PDMA_INTSTS 8 Time out clock HCLK 2 8 TOUTPSC0 PDMA_TOUTPSC 2 0 0 Figure 6 12 7 Example of PDMA Channel 0 Time out Counter Operation ...

Page 384: ...SCT2_DA PDMA_BA 0x028 R W Destination Address Register of PDMA Channel 2 0xXXXX_XXXX PDMA_DSCT2_FIR ST PDMA_BA 0x02C R W First Scatter Gather Descriptor Table Offset of PDMA Channel 2 0xXXXX_XXXX PDMA_DSCT3_CTL PDMA_BA 0x030 R W Descriptor Table Control Register of PDMA Channel 3 0xXXXX_XXXX PDMA_DSCT3_SA PDMA_BA 0x034 R W Source Address Register of PDMA Channel 3 0xXXXX_XXXX PDMA_DSCT3_DA PDMA_BA...

Page 385: ...R W PDMA Channel Read Write Target Abort Flag Register 0x0000_0000 PDMA_TDSTS PDMA_BA 0x424 R W PDMA Channel Transfer Done Flag Register 0x0000_0000 PDMA_SCATSTS PDMA_BA 0x428 R W PDMA Scatter Gather Table Empty Status Register 0x0000_0000 PDMA_TACTSTS PDMA_BA 0x42C R PDMA Transfer Active Flag Register 0x0000_0000 PDMA_TOUTPSC PDMA_BA 0x430 R W PDMA Time out Prescaler Register 0x0000_0000 PDMA_TOU...

Page 386: ...4 3 2 1 0 TBINTDIS BURSIZE Reserved TXTYPE OPMODE Bits Description 31 30 Reserved Reserved 29 16 TXCNT Transfer Count The TXCNT represents the required number of PDMA transfer the real transfer count is TXCNT 1 The maximum transfer count is 16384 every transfer may be byte half word or word that is dependent on TXWIDTH field Note When PDMA finish each transfer data this field will be decrease imme...

Page 387: ...rst Size This field is used for peripheral to determine the burst size or used for determine the re arbitration size 000 128 Transfers 001 64 Transfers 010 32 Transfers 011 16 Transfers 100 8 Transfers 101 4 Transfers 110 2 Transfers 111 1 Transfers Note This field is only useful in burst transfer type 3 Reserved Reserved 2 TXTYPE Transfer Type 0 Burst transfer type 1 Single transfer type 1 0 OPMO...

Page 388: ... R W Source Address Register of PDMA Channel 2 0xXXXX_XXXX PDMA_DSCT3_SA PDMA_BA 0x034 R W Source Address Register of PDMA Channel 3 0xXXXX_XXXX PDMA_DSCT4_SA PDMA_BA 0x044 R W Source Address Register of PDMA Channel 4 0xXXXX_XXXX 31 30 29 28 27 26 25 24 SA 23 22 21 20 19 18 17 16 SA 15 14 13 12 11 10 9 8 SA 7 6 5 4 3 2 1 0 SA Bits Description 31 0 SA PDMA Transfer Source Address Register This fie...

Page 389: ...stination Address Register of PDMA Channel 2 0xXXXX_XXXX PDMA_DSCT3_DA PDMA_BA 0x038 R W Destination Address Register of PDMA Channel 3 0xXXXX_XXXX PDMA_DSCT4_DA PDMA_BA 0x048 R W Destination Address Register of PDMA Channel 4 0xXXXX_XXXX 31 30 29 28 27 26 25 24 DA 23 22 21 20 19 18 17 16 DA 15 14 13 12 11 10 9 8 DA 7 6 5 4 3 2 1 0 DA Bits Description 31 0 DA PDMA Transfer Destination Address Regi...

Page 390: ...et of PDMA Channel 4 0xXXXX_XXXX 31 30 29 28 27 26 25 24 NEXT 23 22 21 20 19 18 17 16 NEXT 15 14 13 12 11 10 9 8 FIRST 7 6 5 4 3 2 1 0 FIRST Bits Description 31 16 NEXT PDMA Next Descriptor Table Offset This field indicates the offset of next descriptor table address in system memory Note write operation is useless in this field 15 0 FIRST PDMA First Descriptor Table Offset This field indicates th...

Page 391: ...tor Table Address of PDMA Channel 2 0xXXXX_XXXX PDMA_CURSCAT3 PDMA_BA 0x05C R Current Scatter Gather Descriptor Table Address of PDMA Channel 3 0xXXXX_XXXX PDMA_CURSCAT4 PDMA_BA 0x060 R Current Scatter Gather Descriptor Table Address of PDMA Channel 4 0xXXXX_XXXX 31 30 29 28 27 26 25 24 CURADDR 23 22 21 20 19 18 17 16 CURADDR 15 14 13 12 11 10 9 8 CURADDR 7 6 5 4 3 2 1 0 CURADDR Bits Description 3...

Page 392: ...29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CHEN4 CHEN3 CHEN2 CHEN1 CHEN0 Bits Description 31 5 Reserved Reserved n n 0 1 4 CHENn PDMA Channel N Enable Bit Set this bit to 1 to enable PDMAn operation Channel cannot be active if it is not set as enabled 0 PDMA channel n Disabled 1 PDMA channel n Enabled Note Set PDMA_PAUSE or P...

Page 393: ... 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PAUSE4 PAUSE3 PAUSE2 PAUSE1 PAUSE0 Bits Description 31 5 Reserved Reserved n n 0 1 4 PAUSEn PDMA Channel N Transfer Pause Control Register Write Only User can set PAUSEn bit field to pause the PDMA transfer When user sets PAUSEn bit the PDMA controller will pause the on going transfer then clear the channel enable bit CHEN PDMA_CHCTL n n 0 1 4 and clear reque...

Page 394: ...0 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SWREQ4 SWREQ3 SWREQ2 SWREQ1 SWREQ0 Bits Description 31 5 Reserved Reserved n n 0 1 4 SWREQn PDMA Channel N Software Request Register Write Only Set this bit to 1 to generate a software request to PDMA n 0 No effect 1 Generate a software request Note1 User can read PDMA_TRGSTS register to know which channel is on active Active flag may be triggered by softwar...

Page 395: ...ved REQSTS4 REQSTS3 REQSTS2 REQSTS1 REQSTS0 Bits Description 31 5 Reserved Reserved n n 0 1 4 REQSTSn PDMA Channel N Request Status Read Only This flag indicates whether channel n have a request or not no matter request from software or peripheral When PDMA controller finishes channel transfer this bit will be cleared automatically 0 PDMA Channel n has no request 1 PDMA Channel n has a request Not...

Page 396: ...SET0 Bits Description 31 5 Reserved Reserved n n 0 1 4 FPRISETn PDMA Channel N Fixed Priority Setting Register Set this bit to 1 to enable fixed priority level The fixed priority channel has higher priority than round robin priority channel If multiple channels are set as the same priority the higher number of channels have higher priority Write Operation 0 No effect 1 Set PDMA channel n to fixed ...

Page 397: ... 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved FPRICLR4 FPRICLR3 FPRICLR2 FPRICLR1 FPRICLR0 Bits Description 31 5 Reserved Reserved n n 0 1 4 FPRICLRn PDMA Channel N Fixed Priority Clear Register Write Only Set this bit to 1 to clear fixed priority level 0 No effect 1 Clear PDMA channel n fixed priority setting Note User can ...

Page 398: ...pt Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved INTEN4 INTEN3 INTEN2 INTEN1 INTEN0 Bits Description 31 12 Reserved Reserved n n 0 1 4 INTENn PDMA Channel N Interrupt Enable Register This field is used for enabling PDMA channel n interrupt 0 PDMA channel n interrupt Disabled 1 PDMA channel n int...

Page 399: ... Peripheral request time out 7 3 Reserved Reserved 2 TEIF Table Empty Interrupt Flag Read Only This bit indicates PDMA channel scatter gather table is empty User can read PDMA_SCATSTS register to indicate which channel scatter gather table is empty 0 PDMA channel scatter gather table is not empty 1 PDMA channel scatter gather table is empty 1 TDIF Transfer Done Interrupt Flag Read Only This bit in...

Page 400: ...0 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ABTIF4 ABTIF3 ABTIF2 ABTIF1 ABTIF0 Bits Description 31 5 Reserved Reserved n n 0 1 4 ABTIFn PDMA Channel N Read Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits 0 No AHB bus ERROR response ...

Page 401: ...0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TDIF4 TDIF3 TDIF2 TDIF1 TDIF0 Bits Description 31 5 Reserved Reserved n n 0 1 4 TDIFn PDMA Channel N Transfer Done Flag Register This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits 0 PDMA channel transfe...

Page 402: ...served TEMPTYF4 TEMPTYF3 TEMPTYF2 TEMPTYF1 TEMPTYF0 Bits Description 31 5 Reserved Reserved n n 0 1 4 TEMPTYFn Table Empty Flag Register T This bit indicates which PDMA channel table is empty when channel have a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished current transfer and next table operation mode is...

Page 403: ...r Active Flag Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TXACTF4 TXACTF3 TXACTF2 TXACTF1 TXACTF0 Bits Description 31 5 Reserved Reserved n n 0 1 4 TXACTFn PDMA Channel N Transfer on Active Flag Register Read Only This bit indicates which PDMA channel is in active 0 PDMA channel is not finished 1 PDM...

Page 404: ...A channel 1 time out clock source is HCLK 210 011 PDMA channel 1 time out clock source is HCLK 211 100 PDMA channel 1 time out clock source is HCLK 212 101 PDMA channel 1 time out clock source is HCLK 213 110 PDMA channel 1 time out clock source is HCLK 214 111 PDMA channel 1 time out clock source is HCLK 215 3 Reserved Reserved 2 0 TOUTPSC0 PDMA Channel 0 Time out Clock Source Prescaler Bits 000 ...

Page 405: ...UTEN PDMA_BA 0x434 R W PDMA Time out Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TOUTEN1 TOUTEN0 Bits Description 31 2 Reserved Reserved n n 0 1 TOUTENn PDMA Channel N Time out Enable Bit 0 PDMA Channel n time out function Disabled 1 PDMA Channel n time out function Enabled ...

Page 406: ...MA_BA 0x438 R W PDMA Time out Interrupt Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TOUTIEN1 TOUTIEN0 Bits Description 31 2 Reserved Reserved n n 0 1 TOUTIENn PDMA Channel N Time out Interrupt Enable Bit 0 PDMA Channel n time out interrupt Disabled 1 PDMA Channel n time out interrupt Enabled ...

Page 407: ...Base Address Register 0x2000_0000 31 30 29 28 27 26 25 24 SCATBA 23 22 21 20 19 18 17 16 SCATBA 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 16 SCATBA PDMA Scatter gather Descriptor Table Address Register In Scatter Gather mode this is the base address for calculating the next link list address The next link address equation is Next Link Address PDMA_SCATBA PDMA_DSCT...

Page 408: ...19 18 17 16 TOC1 15 14 13 12 11 10 9 8 TOC0 7 6 5 4 3 2 1 0 TOC0 Bits Description 31 16 TOC1 Time out Counter for Channel 1 This controls the period of time out function for channel 1 The calculation unit is based on TOUTPSC1 PDMA_TOUTPSC 5 3 clock The example of time out period can refer TOC0 bit description 15 0 TOC0 Time out Counter for Channel 0 This controls the period of time out function fo...

Page 409: ...d RESET4 RESET3 RESET2 RESET1 RESET0 Bits Description 31 5 Reserved Reserved n n 0 1 4 RESETn PDMA Channel N Reset Control Register User can set this bit field to reset the PDMA channel When user sets RESETn bit the PDMA controller will finish the on going transfer then clear the channel enable bit CHEN PDMA_CHCTL n n 0 1 4 and clear request active flag If re enable channel after channel reset PDM...

Page 410: ...ease refer to the explanation of REQSRC0 23 22 Reserved Reserved 21 16 REQSRC2 Channel 2 Request Source Selection This filed defines which peripheral is connected to PDMA channel 2 User can configure the peripheral setting by REQSRC2 Note The channel configuration is the same as REQSRC0 field Please refer to the explanation of REQSRC0 15 14 Reserved Reserved 13 8 REQSRC1 Channel 1 Request Source S...

Page 411: ..._RX 21 Channel connects to PWM0_P1_RX 22 Channel connects to PWM0_P2_RX 23 Channel connects to PWM0_P3_RX 24 Channel connects to PWM1_P1_RX 25 Channel connects to PWM1_P2_RX 26 Channel connects to PWM1_P3_RX 27 Reserved 28 Channel connects to I2C0_TX 29 Channel connects to I2C0_RX 30 Channel connects to I2C1_TX 31 Channel connects to I2C1_RX 32 Channel connects to TMR0 33 Channel connects to TMR1 ...

Page 412: ...egister 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved REQSRC4 Bits Description 31 6 Reserved Reserved 5 0 REQSRC4 Channel 4 Request Source Selection This filed defines which peripheral is connected to PDMA channel 4 User can configure the peripheral setting by REQSRC4 Note The channel configuration is the same ...

Page 413: ...e PWM generator also supports input capture function It supports latch PWM counter value to corresponding register when input channel has a rising transition falling transition or both transition is happened Capture function also support PDMA to transfer captured data to memory 6 13 2 Features 6 13 2 1 PWM function features Supports maximum clock frequency up to144MHz Supports up to two PWM module...

Page 414: ...riod point zero or period point up count compared point down count compared point events PWM up count free trigger compared point down count free trigger compared point events 6 13 2 2 Capture Function Features Supports up to 6 capture input channels with 16 bit resolution for each PWM module Supports rising or falling capture condition Supports input rising falling capture interrupt Supports risi...

Page 415: ...can be set equal or double to HCLK frequency as Figure 6 13 2 the detail register setting please refer to Table 6 13 1 The clock source of PWM counter PWMx_CLK0 x 0 1 can be selected from PWM0 PWM1 system clock or TIMERm interrupt events TMRn_INT n 0 1 3 as Figure 6 13 3 by setting ECLKSRC0 PWM_CLKSRC 2 0 for PWMx_CLK0 ECLKSRC2 PWM_CLKSRC 10 8 for PWMx_CLK2 and ECLKSRC4 PWM_CLKSRC 18 16 for PWMx_C...

Page 416: ...ed channels PWMx_CH0 and PWMx_CH1 PWMx_CH2 and PWMx_CH3 PWMx_CH4 and PWMx_CH5 counters both come from the same clock source and prescaler When counter count to 0 PERIOD PWM_PERIODn 15 0 n 0 1 5 or equal to comparator events will be generated These events are passed to corresponding generators to generate PWM pulse interrupt signal and trigger signal for ADC to start conversion Output control is us...

Page 417: ... 16 16 PWM0_CH5 Counter0 16bits Comparator0 16bits Counter1 16bits Comparator1 16bits Counter2 16bits Comparator2 16bits Counter3 16bits Comparator3 16bits Counter4 16bits Comparator4 16bits Counter5 16bits Comparator5 16bits PWM0_BRAKE0 PWM0_BRAKE1 PWM0_CLK0 PWM0_BRAKE0 PWM0_BRAKE1 PWM0_BRAKE0 PWM0_BRAKE1 PWM0_BRAKE0 PWM0_BRAKE1 PWM0_BRAKE0 PWM0_BRAKE1 PWM0_BRAKE0 PWM0_BRAKE1 PWM0_BRAKE0 PWM0_BRA...

Page 418: ...ator0 Output Control0 16 16 16 PWM0_BRAKE0 PWM0_BRAKE1 16 16 Comparator3 Comparator1 Comparator0 Counter0 Free Trigger Comparator0 Synchronous Signal Synchronous Signal i i i t i b b b b b b b b b b i t denotes interrupt events denotes trigger events denotes interrupt and trigger events Note PWM0_CLK2 PWM0_CLK4 Figure 6 13 5 PWM Complementary Mode Architecture Diagram 6 13 4 Basic Configuration 6 ...

Page 419: ...eset PWM1 peripheral in PWM1RST SYS_IPRST1 21 Pin Configuration Group Pin Name GPIO MFP PWM1 PWM1_BRAKE0 PE 4 PF 1 MFP6 PWM1_BRAKE1 PE 5 PF 2 MFP6 PA 9 MFP7 PWM1_CH0 PC 6 PC 9 PC 15 PD 12 MFP6 PWM1_CH1 PB 12 PC 7 PC 10 PD 13 MFP6 PWM1_CH2 PA 3 PC 11 PD 14 MFP6 PWM1_CH3 PA 2 PC 12 PD 15 MFP6 PWM1_CH4 PA 1 PC 13 MFP6 PWM1_CH5 PA 0 PC 14 MFP6 6 13 5 Functional Description 6 13 5 1 PWM Prescaler PWM p...

Page 420: ...cale counts to 0 PWM generates period point event when the counter counts to PERIOD and prescale counts to 0 Figure 6 13 7 shows an example of up counter wherein PWM period time PERIOD 1 CLKPSC 1 PWMx_CLK 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 PWM Period PWM Period PERIOD 5 PERIOD 8 PWM Period PERIOD 8 zero point event period point event CNT PWM_CNTn 15 0 CNTENn PWM_CNTEN n X Note n...

Page 421: ...hows an example of up down counter wherein PWM period time 2 PERIOD CLKPSC 1 PWMx_CLK The DIRF PWM_CNTn 16 bit is counter direction indicator flag where high is up counting and low is down counting DIRF PWM_CNTn 16 0 1 2 3 4 3 1 2 0 1 2 3 4 3 1 2 0 5 6 7 6 4 5 1 2 3 4 PWM Period PERIOD 4 PERIOD 7 PWM Period zero point event center point event CNT PWM_CNTn 15 0 CNTENn PWM_CNTEN n Note1 When in up d...

Page 422: ...ously compared to even channel s counter value When counter is equal to value of FTCMPDAT register PWM generates an event and only uses to trigger ADC 6 13 5 7 PWM Double Buffering The double buffering uses double buffers to separate software writing and hardware action operation timing There are four loading modes for loading values to buffer period loading mode immediately loading mode window lo...

Page 423: ...rs while each period is completed For example after PWM counter up counts from zero to PERIOD in the up counter operation or down counts from PERIOD to zero in the down counter operation or up counts from zero to PERIOD and then down counts to zero in the up down counter operation Figure 6 13 12 shows period loading timing of up count operation where PERIOD DATA0 denotes the initial data of PERIOD...

Page 424: ...WM_CPSCBUFn_m 15 0 PBUF PWM_PBUFn 15 0 or CMPBUF PWM_CMPBUFn 15 0 after current counter count is completed If the updated PERIOD value is less than current counter value counter will count wraparound Immediately loading mode has the highest priority If IMMLDENn has been set other loading mode for channel n will become invalid Figure 6 13 13 shows an example and its steps sequence is described belo...

Page 425: ...ndow is opened Every channel n s load window is opened by setting the corresponding LOADn PWM_LOAD 5 0 to 1 and hardware will close the window at the end of PWM period Figure 6 13 14 shows an example and its steps sequence is described below 1 Software writes CMPDAT DATA1 at point 1 and the load window is not opened at this period so CMPDAT will not load to CMPBUF 2 Zero point accumulate interrupt...

Page 426: ...e CMPBUF register in center of each period that is counter counts to PERIOD CLKPSC PWM_CLKPSCn_m 11 0 and PERIOD PWM_PERIODn 15 0 will all load to their active CPSCBUF and PBUF registers while each period is completed Center loading mode can work with window loading mode the CMP PWM_CMPDATn 15 0 will load to active CMPBUF register in center of each period but it is valid only at the interval of lo...

Page 427: ...er PWM counter counted a period counter value will keep in zero User can re start next one shot by writing new value to CMP PWM_CMPDATn 15 0 bits If one shot counter still running to update CMPDAT register will cause next one shot as continuous one shot Besides to write CMPDAT register twice under continuous one shot operation latest value in CMPDAT register is valid at next one shot period and on...

Page 428: ...er type and counter equal to comparator point in three types As to up down counter type there are two counter equal comparator points one at up count and the other at down count Besides Complementary mode has two comparators compared with counter and thus comparing equal points will become four in up down counter type and two for up or down counter type Each event point can decide PWM waveform to ...

Page 429: ...ter type Table 6 13 3 and up down counter type Table 6 13 4 By using event priority user can easily generate 0 to 100 duty pulse as shown in Figure 6 13 18 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 CMPDAT 0 0 Duty CMPDAT 1 25 Duty CMPDAT 2 50 Duty CMPDAT 3 75 Duty CMPDAT 4 100 Duty DIRF PWM period PWM period 0 1 2 3 4 0 1 2 3 4 CMPDAT 0 0 Duty CMPDAT 1 20 Duty CMPDAT 2 40 Duty CMPDAT 3 60 Duty CMPDAT 4 80...

Page 430: ...PWM_CH4 and PWM_CH5 are running off its own period and duty as shown in Figure 6 13 19 PWMx_CH2 PWMx_CH0 Setting OUTMODE0 PWMx_CTL1 24 0x0 PWMx_CH1 PWMx_CH3 PWMx_CH4 PWMx_CH5 Setting OUTMODE2 PWMx_CTL1 25 0x0 Setting OUTMODE4 PWMx_CTL1 26 0x0 Figure 6 13 19 PWM Independent Mode Waveform Priority Down Event 1 Highest Zero event CNT zero 2 Compare down event of odd channel CNT CMPDm 3 Compare down e...

Page 431: ...o output functions group and synchronous functions for advanced output control Group function forces the PWM_CH2 and PWM_CH4 synchronous with PWM_CH0 generator and forces the PWM_CH3 and PWM_CH5 synchronous with PWM_CH1 may simplify updating duty control in DC and BLDC motor applications Besides Synchronous function makes any channel of PWM0 in phase user can control phase value and direction 6 13...

Page 432: ...e input signal from PWM0_SYNC_IN pin will be filtered by a 3 bit noise filter as Figure 6 13 22 In addition it can be inversed by setting the bit SINPINV PWM_SYNC 23 to realize the polarity setup for the input signal The noise filter sampling clock can be selected by setting bits SFLTCSEL PWM_SYNC 19 17 to fit different noise properties Moreover by setting the bits SFLTCNT PWM_SYNC 22 20 user can ...

Page 433: ...g together followed by setting the PWM Synchronous Start Trigger Register CNTSEN PWM_SSTRG 0 For applications please do not use Group and Synchronous function simultaneously because the Synchronous function will be inactive 16 bits PWM 3 types counter PHSENn PWM_SYNC 2 0 SINSRCn PWM_SYNC 13 8 SWSYNCn PWM_SWSYNC 2 0 PHS PWM_PHSn 15 0 CNT PWM_CNTn 15 0 DIRF PWM_CNTn 16 SYNC_IN SYNC_OUT PHS load sign...

Page 434: ...ure 6 13 24 PWM Synchronous Function with Synchronize source from SYNC_IN Signal 6 13 5 20PWM Output Control After PWM pulse generation there are four to six steps to control the output of PWM channels In independent mode there are Mask Brake Pin Polarity and Output Enable four steps as shown in Figure 6 13 25 In complementary mode it needs two more steps to precede these four steps Complementary ...

Page 435: ...o enable dead time function and DTCNT PWM_DTCTLn_m 11 0 to control dead time period the dead time can be calculated from the following formula Dead time DTCNT PWM_DTCTLn 11 0 1 PWMx_CLK period Dead time insertion clock source can be selected from prescaler output by setting DTCKSEL PWM_DTCTLn_m 24 to 1 By default clock source is come from PWM_CLK which is prescaler input Then the dead time can be ...

Page 436: ...nel 0 2 4 PWMx_CH4 PWMx_CH5 Figure 6 13 28 Illustration of Mask Control Waveform 6 13 5 23PWM Brake Each PWM module has two external input brake control signals User can select active brake pin source is from PWMx_BRAKEy pin by BKxSRC bits of BNF register x 0 1 y 0 1 The external signals will be filtered by a 3 bits noise filter User can enable the noise filter function by BRKxNFEN bits of BNF rei...

Page 437: ...ut safety state user can setup BRKAEVEN PWM_BRKCTL0_1 17 16 for even channels and BRKAODD PWM_BRKCTL0_1 19 18 for odd channels when the fault brake event happens There are two brake detectors Edge detector and Level detector When the edge detector detects the brake signal and BRKEIENn_m PWM_INTEN1 2 0 is enabled the brake function generates BRK_INT This interrupt needs software to clear and the BR...

Page 438: ... occurs both of the BRKEIF0 and BRKEIF1 flags are set and BRKESTS0 and BRKESTS1 bits are also set to indicate brake state of PWMx_CH0 and PWMx_CH1 For the first occurring event software writes 1 to clear the BRKEIF0 flag After that the BRKESTS0 bit is cleared by hardware at the next start of the PWM period At the same moment the PWMx_CH0 outputs the normal waveform even though the brake event is s...

Page 439: ...9 BRKLIF0 PWM_INTSTS1 8 s w clear BRKLSTS0 PWM_INTSTS1 24 BRKLSTS1 PWM_INTSTS1 25 s w clear PWMx_CH1 No matter BRKLIF0 or BRKLIF1 is cleared or not while no brake event occurs brake state resume at the next start of PWM period Note Output Brake State Setting BRKAEVEN 3 High BRKAODD 2 Low Figure 6 13 32 Level Detector Waveform for PWMx_CH0 and PWMx_CH1 Pair The two kinds of detectors detect the sam...

Page 440: ...TL0 8 CPO1LBEN PWM_BRKCTL0 9 Brake Noise Filter Brake Function Level Detect Brake Source ADCLBEN PWM_BRKCTL0 28 BRKLTRG0 PWM_SWBRK 8 Brake System Fail SYSLBEN PWM_BRKCTL0 15 ADCRM PWM1_BRAKE0 PWM0_BRAKE1 0 1 BK0SRC PWM_BNF 16 0 1 BK1SRC PWM_BNF 24 PWM0_BRAKE0 PWM1_BRAKE1 Figure 6 13 33 Brake Source Block Diagram CSSBRKEN PWM_FAILBRK 0 Clock Fail BODBRKEN PWM_FAILBRK 1 Brown Out Detect CORBRKEN PWM...

Page 441: ... blanking ACMP0_O After blanking CLK LEB counter Setting LEBCNT PWM_LEBCNT 8 0 0x4 Setting LEBEN PWM_LEBCTL 0 0x1 Setting SRCREN4 SRCEN2 SRCEN0 PWM_LEBCTL 10 8 0x3 Setting TRGTYPE PWM_LEBCTL 17 16 0x2 Figure 6 13 35 PWM LEB Function Waveform 6 13 5 25Polarity Control Each PWM channel from PWMx_CH0 to PWMx_CH5 has an independent polarity control module to configure the polarity of the active state ...

Page 442: ...e matching occurs at up count direction the Up Interrupt Flag CMPUIFn PWM_INTSTS0 21 16 is set and if matching at the opposite direction the Down Interrupt Flag CMPDIFn PWM_INTSTS0 29 24 is set If the corresponding interrupt enable bits are set the trigger events will generates interrupt signals PWM_INT can use the PWM_IFA register to accumulate the number of times that the interrupt flags have be...

Page 443: ...nterrupt is the capture interrupt CAP_INT It shares the PWM_INT vector in NVIC The CAP_INT can be generated when the CRLIFn PWM_CAPIF 5 0 flag is triggered and the Capture Rising Interrupt Enable bit CAPRIENn PWM_CAPIEN 5 0 is set to 1 Or in the falling edge condition the CFLIFn PWM_CAPIF 13 8 flag can be triggered when the Capture Falling Interrupt Enable bit CAPFIENn PWM_CAPIEN 13 8 is set to 1 ...

Page 444: ...4 CMPDIF0 PWM_INTSTS0 24 ZIEN1 PWM_INTEN0 1 ZIF1 PWM_INTSTS0 1 PIEN1 PWM_INTEN0 9 PIF1 PWM_INTSTS0 9 CMPUIEN1 PWM_INTEN0 17 CMPUIF1 PWM_INTSTS0 17 CMPDIEN1 PWM_INTEN0 25 CMPDIF1 PWM_INTSTS0 25 CAPRIEN0 PWM_CAPIEN 0 CFLIF0 PWM_CAPIF 8 CAPFIEN0 PWM_CAPIEN 8 CRLIF1 PWM_CAPIF 1 CAPRIEN1 PWM_CAPIEN 1 CFLIF1 PWM_CAPIF9 CAPFIEN1 PWM_CAPIEN 9 BRKLIF0 PWM_INTSTS1 8 BRKLIF1 PWM_INTSTS1 9 BRKLIEN0_1 PWM_INTE...

Page 445: ...l number There are 16 PWM events can be selected as the trigger source for one pair of channels which shown in Figure 6 13 39 Figure 6 13 40 is the trigger ADC timing waveform in the up down counter type 16 to 1 MUX 2h 3h 0h 1h 6h 7h 4h 5h Fh PWM_CH1 down count compared point PWM_CH0 zero point PWM_CH0 period point PWM_CH0 up count compared point PWM_CH0 down count compared point PWM_CH1 zero poin...

Page 446: ...re function will also generate an interrupt CAP_INT using PWM_INT vector if the rising or falling latch occurs and the corresponding channel n s rising or falling interrupt enable bits are set where the CAPRIENn PWM_CAPIEN 5 0 bit is for the rising edge and the CAPFIENn PWM_CAPIEN 13 8 bit is for the falling edge When rising or falling latch occurs the corresponding PWM counter may be reloaded wit...

Page 447: ...e second time the falling edge does not result in a reload because of the disabled FCRLDENn bit In this example the counter also reloads at the rising edge of the capture input because the RCRLDENn bit is enabled too Moreover if the case is setup as the up counter type the counter will reload the value zero and count up to the value PERIOD Figure 6 13 42 also illustrates the timing example for the...

Page 448: ...orts the PDMA transfer function when operating in the capture mode When the corresponding PDMA enable bit CHENn_m CHEN0_1 at PWM_PDMACTL 0 CHEN2_3 at PWM_PDMACTL 8 and CHEN4_5 at PWM_PDMACTL 16 where n and m denote complement pair channels is set the capture module will issue a request to PDMA controller when the preceding capture event has happened The PDMA controller will issue an acknowledgemen...

Page 449: ...tured data will be transferred to the memory The CAPORD0_1 PWM_PDMACTL 1 bit is set to 1 so the rising edge data will be the first data to transfer and following is the falling edge data to transfer As shown in Figure 6 13 43 the last assertions of the CRLIF0 and CFLIF0 signal have some overlap The value of PWM_RCAPDAT0 register is 11 will be loaded to PWM_PDMACAP0_1 register to wait for transfer ...

Page 450: ...24 R W PWM Clear Counter Register 0x0000_0000 PWM_LOAD PWMx_BA 0x28 R W PWM Load Register 0x0000_0000 PWM_PERIOD0 PWMx_BA 0x30 R W PWM Period Register 0 0x0000_0000 PWM_PERIOD1 PWMx_BA 0x34 R W PWM Period Register 1 0x0000_0000 PWM_PERIOD2 PWMx_BA 0x38 R W PWM Period Register 2 0x0000_0000 PWM_PERIOD3 PWMx_BA 0x3C R W PWM Period Register 3 0x0000_0000 PWM_PERIOD4 PWMx_BA 0x40 R W PWM Period Regist...

Page 451: ...00_0000 PWM_BRKCTL0_1 PWMx_BA 0xC8 R W PWM Brake Edge Detect Control Register 0 1 0x0000_0000 PWM_BRKCTL2_3 PWMx_BA 0xCC R W PWM Brake Edge Detect Control Register 2 3 0x0000_0000 PWM_BRKCTL4_5 PWMx_BA 0xD0 R W PWM Brake Edge Detect Control Register 4 5 0x0000_0000 PWM_POLCTL PWMx_BA 0xD4 R W PWM Pin Polar Inverse Register 0x0000_0000 PWM_POEN PWMx_BA 0xD8 R W PWM Output Enable Register 0x0000_000...

Page 452: ...T2 PWMx_BA 0x220 R PWM Falling Capture Data Register 2 0x0000_0000 PWM_RCAPDAT3 PWMx_BA 0x224 R PWM Rising Capture Data Register 3 0x0000_0000 PWM_FCAPDAT3 PWMx_BA 0x228 R PWM Falling Capture Data Register 3 0x0000_0000 PWM_RCAPDAT4 PWMx_BA 0x22C R PWM Rising Capture Data Register 4 0x0000_0000 PWM_FCAPDAT4 PWMx_BA 0x230 R PWM Falling Capture Data Register 4 0x0000_0000 PWM_RCAPDAT5 PWMx_BA 0x234 ...

Page 453: ...0 PWM_CMPBUF4 PWMx_BA 0x32C R PWM CMPDAT4 Buffer 0x0000_0000 PWM_CMPBUF5 PWMx_BA 0x330 R PWM CMPDAT5 Buffer 0x0000_0000 PWM_CPSCBUF0_1 PWMx_BA 0x334 R PWM CLKPSC0_1 Buffer 0x0000_0000 PWM_CPSCBUF2_3 PWMx_BA 0x338 R PWM CLKPSC2_3 Buffer 0x0000_0000 PWM_CPSCBUF4_5 PWMx_BA 0x33C R PWM CLKPSC4_5 Buffer 0x0000_0000 PWM_FTCBUF0_1 PWMx_BA 0x340 R PWM FTCMPDAT0_1 Buffer 0x0000_0000 PWM_FTCBUF2_3 PWMx_BA 0...

Page 454: ... SYS_REGLCTL register 30 DBGHALT ICE Debug Mode Counter Halt Write Protect If counter halt is enabled PWM all counters will keep current value until exit ICE debug mode 0 ICE debug mode counter halt Disabled 1 ICE debug mode counter halt Enabled Note This bit is write protected Refer to SYS_REGLCTL register 29 26 Reserved Reserved 24 GROUPEN Group Function Enable Bit 0 The output waveform of each ...

Page 455: ...od by setting CTRLDn bit 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success 7 6 Reserved Reserved n n 0 1 5 CTRLDn Center Re load Each bit n controls the corresponding PWM channel n ...

Page 456: ...Bits Description 31 27 Reserved Reserved n 2 24 n 0 2 4 OUTMODEn PWM Output Mode Each bit n controls the output mode of corresponding PWM channel n 0 PWM independent mode 1 PWM complementary mode Note When operating in group function these bits must all set to the same mode 23 22 Reserved Reserved n 16 n 0 1 5 CNTMODEn PWM Counter Mode Each bit n controls the corresponding PWM channel n 0 Auto rel...

Page 457: ...counter count increment after synchronizing 23 SINPINV SYNC Input Pin Inverse 0 The state of PWM0_SYNC_IN pin is passed to the negative edge detector 1 The inversed state of PWM0_SYNC_IN pin is passed to the negative edge detector 22 20 SFLTCNT SYNC Edge Detector Filter Count The register bits control the counter number of edge detector 19 17 SFLTCSEL SYNC Edge Detector Filter Clock Selection 000 ...

Page 458: ...ual to 0 10 Counter equal to PWM_CMPDATm m denotes 1 3 5 11 SYNC_OUT signal will not be generated 7 3 Reserved Reserved n 2 n 0 2 4 PHSENn SYNC Phase Enable Bits n denotes PWM channel 0 2 4 and m denotes channel 1 3 5 0 PWM counter disable to load value of PHS PWM_PHSn_m 15 0 bits 1 PWM counter enable to load value of PHS PWM_PHSn_m 15 0 bits ...

Page 459: ...ftware Control Synchronization Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SWSYNC4 SWSYNC2 SWSYNC0 Bits Description 31 3 Reserved Reserved n 2 n 0 2 4 SWSYNCn Software SYNC Function Each bit n controls corresponding PWM channel n When SINSRCn PWM_SYNC 13 8 is selected to 0 SYNC_OUT source is come fro...

Page 460: ...WMx_CH4 5 External Clock Source Select 000 PWMx_CLK x denotes 0 or 1 001 TIMER0 time out event 010 TIMER1 time out event 011 TIMER2 time out event 100 TIMER3 time out event Others Reserved 15 11 Reserved Reserved 10 8 ECLKSRC2 PWMx_CH2 3 External Clock Source Select 000 PWMx_CLK x denotes 0 or 1 001 TIMER0 time out event 010 TIMER1 time out event 011 TIMER2 time out event 100 TIMER3 time out event...

Page 461: ...0x18 R W PWM Clock Pre scale Register 2 3 0x0000_0000 PWM_CLKPS C4_5 PWMx_BA 0x1C R W PWM Clock Pre scale Register 4 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved CLKPSC 7 6 5 4 3 2 1 0 CLKPSC Bits Description 31 12 Reserved Reserved 11 0 CLKPSC PWM Counter Clock Pre scale The clock of PWM counter is decided by clock prescaler Each P...

Page 462: ... Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 Bits Description 31 6 Reserved Reserved n n 0 1 5 CNTENn PWM Counter Enable Bits Each bit n controls the corresponding PWM channel n 0 PWM Counter and clock prescaler Stop Running 1 PWM Counter and clock prescaler ...

Page 463: ...0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNTCLR5 CNTCLR4 CNTCLR3 CNTCLR2 CNTCLR1 CNTCLR0 Bits Description 31 6 Reserved Reserved n n 0 1 5 CNTCLRn Clear PWM Counter Control Bit It is automatically cleared by hardware Each bit n controls the corresponding PWM channel n 0 No effect 1 Clear 16 bit PWM counter t...

Page 464: ...served 7 6 5 4 3 2 1 0 Reserved LOAD5 LOAD4 LOAD3 LOAD2 LOAD1 LOAD0 Bits Description 31 6 Reserved Reserved n n 0 1 5 LOADn Re load PWM Comparator Register CMPDAT Control Bit This bit is software write and hardware clear when current PWM period end Each bit n controls the corresponding PWM channel n Write Operation 0 No effect 1 Set load window of window loading mode Read Operation 0 No load windo...

Page 465: ... 0x0000_0000 PWM_PERIO D5 PWMx_BA 0x44 R W PWM Period Register 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PERIOD 7 6 5 4 3 2 1 0 PERIOD Bits Description 31 16 Reserved Reserved 15 0 PERIOD PWM Period Register Up Count mode In this mode PWM counter counts from 0 to PERIOD and restarts from 0 PWM period time PERIOD 1 CLKPSC 1 PWMx_CLK Down C...

Page 466: ...0x0000_0000 PWM_CMPDA T5 PWMx_BA 0x64 R W PWM Comparator Register 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CMP 7 6 5 4 3 2 1 0 CMP Bits Description 31 16 Reserved Reserved 15 0 CMP PWM Comparator Register CMP bits use to compare with CNT PWM_CNTn 15 0 bits to generate PWM waveform interrupt and trigger ADC In independent mode CMPDAT0 5 r...

Page 467: ... clock source from prescaler output with counter clock prescale Note This register is write protected Refer to SYS_REGLCTL register 23 17 Reserved Reserved 16 DTEN Enable Dead time Insertion for PWM Pair PWMx_CH0 PWMx_CH1 PWMx_CH2 PWMx_CH3 PWMx_CH4 PWMx_CH5 Write Protect Dead time insertion is only active when this pair of complementary PWM is enabled If dead time insertion is inactive the outputs...

Page 468: ...x0000_0000 PWM_PHS2_3 PWMx_BA 0x84 R W PWM Counter Phase Register 2 3 0x0000_0000 PWM_PHS4_5 PWMx_BA 0x88 R W PWM Counter Phase Register 4 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PHS 7 6 5 4 3 2 1 0 PHS Bits Description 31 16 Reserved Reserved 15 0 PHS PWM Synchronous Start Phase Bits PHS bits determines the PWM synchronous start phase ...

Page 469: ...0 PWM_CNT3 PWMx_BA 0x9C R PWM Counter Register 3 0x0000_0000 PWM_CNT4 PWMx_BA 0xA0 R PWM Counter Register 4 0x0000_0000 PWM_CNT5 PWMx_BA 0xA4 R PWM Counter Register 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved DIRF 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 17 Reserved Reserved 16 DIRF PWM Direction Indicator Flag Read Only 0 Counter is Dow...

Page 470: ...ved 2n 17 2n 16 n 0 1 5 PRDPCTLn PWM Period Center Point Control PWM can control output level on period center point event Each bit n controls the corresponding PWM channel n 00 Do nothing 01 PWM period center point output Low 10 PWM period center point output High 11 PWM period center point output Toggle Note This bit is center point control when PWM counter operating in up down counter type 15 1...

Page 471: ...n Point Control PWM can control output level on compare down point event Each bit n controls the corresponding PWM channel n 00 Do nothing 01 PWM compare down point output Low 10 PWM compare down point output High 11 PWM compare down point output Toggle Note In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4 15 12 Reserved Reserved 2n 1 2n n 0 1 5 CMPUCTLn PWM Compare ...

Page 472: ... 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved MSKEN5 MSKEN4 MSKEN3 MSKEN2 MSKEN1 MSKEN0 Bits Description 31 6 Reserved Reserved n n 0 1 5 MSKENn PWM Mask Enable Bits The PWM output signal will be masked when this bit is enabled The corresponding PWM channel n will output MSKDATn PWM_MSK 5 0 data Each bit n controls the corresponding PWM channel n 0 PWM output sig...

Page 473: ...25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved MSKDAT5 MSKDAT4 MSKDAT3 MSKDAT2 MSKDAT1 MSKDAT0 Bits Description 31 6 Reserved Reserved n n 0 1 5 MSKDATn PWM Mask Data Bit This data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled Each bit n controls the corresponding PWM channel n 0 Output logic low to P...

Page 474: ..._BRAKE1 1 Brake 1 pin source come from PWM0_BRAKE1 23 17 Reserved Reserved 16 BK0SRC Brake 0 Pin Source Select For PWM0 setting 0 Brake 0 pin source come from PWM0_BRAKE0 1 Brake 0 pin source come from PWM1_BRAKE0 For PWM1 setting 0 Brake 0 pin source come from PWM1_BRAKE0 1 Brake 0 pin source come from PWM0_BRAKE0 15 BRK1PINV Brake 1 Pin Inverse 0 Brake pin event will be detected if PWM1_BRAKEx p...

Page 475: ...tect or pin status is high in level detect 1 Brake pin event will be detected if PWM0_BRAKEx pin status transfer from high to low in edge detect or pin status is low in level detect 6 4 BRK0FCNT Brake 0 Edge Detector Filter Count The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT 3 1 BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection 000 Filter clock HCLK 001 Filte...

Page 476: ...BRKEN Bits Description 31 4 Reserved Reserved 3 CORBRKEN Core Lockup Detection Trigger PWM Brake Function Enable Bit 0 Brake Function triggered by Core lockup event Disabled 1 Brake Function triggered by Core lockup event Enabled 2 Reserved Reserved 1 BODBRKEN Brown out Detection Trigger PWM Brake Function Enable Bit 0 Brake Function triggered by BOD event Disabled 1 Brake Function triggered by BO...

Page 477: ... level detect brake source Disabled 1 ADCRM as level detect brake source Enabled Note This register is write protected Refer to SYS_REGLCTL register 27 21 Reserved Reserved 20 ADCEBEN Enable ADC Result Monitor ADCRM As Edge detect Brake Source Write Protect 0 ADCRM as edge detect brake source Disabled 1 ADCRM as edge detect brake source Enabled Note This register is write protected Refer to SYS_RE...

Page 478: ...r to SYS_REGLCTL register 8 CPO0LBEN Enable ACMP0_O Digital Output As Level detect Brake Source Write Protect 0 ACMP0_O as level detect brake source Disabled 1 ACMP0_O as level detect brake source Enabled Note This register is write protected Refer to SYS_REGLCTL register 7 SYSEBEN Enable System Fail As Edge detect Brake Source Write Protect 0 System Fail condition as edge detect brake source Disa...

Page 479: ...NUC126 Aug 08 2018 Page 479 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 1 ACMP0_O as edge detect brake source Enabled Note This register is write protected Refer to SYS_REGLCTL register ...

Page 480: ...31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PINV5 PINV4 PINV3 PINV2 PINV1 PINV0 Bits Description 31 6 Reserved Reserved n n 0 1 5 PINVn PWM PIN Polar Inverse Control The register controls polarity state of PWMx_CHn output pin Each bit n controls the corresponding PWM channel n 0 PWMx_CHn output pin polar inverse Disabled...

Page 481: ...WM Output Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved POEN5 POEN4 POEN3 POEN2 POEN1 POEN0 Bits Description 31 6 Reserved Reserved n n 0 1 5 POENn PWMx_CHn Pin Output Enable Bits Each bit n controls the corresponding PWM channel n 0 PWMx_CHn pin at tri state 1 PWMx_CHn pin in output mode ...

Page 482: ...cription 31 11 Reserved Reserved n 2 8 n 0 2 4 BRKLTRGn PWM Level Brake Software Trigger Write Only Write Protect Write 1 to this bit will trigger level brake and set BRKLIFn bits to 1 in PWM_INTSTS1 register Each bit n controls the corresponding PWM pair n Note This register is write protected Refer to SYS_REGLCTL register 7 3 Reserved Reserved n 2 n 0 2 4 BRKETRGn PWM Edge Brake Software Trigger...

Page 483: ...errupt Enabled Note In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4 23 IFAIEN4_5 PWM Channel 4 5 Interrupt Flag Accumulator Interrupt Enable Bit 0 Interrupt Flag accumulator interrupt Disabled 1 Interrupt Flag accumulator interrupt Enabled 22 Reserved Reserved n 16 n 0 1 5 CMPUIENn PWM Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding PWM ...

Page 484: ...pt Flag Accumulator Interrupt Enable Bit 0 Interrupt Flag accumulator interrupt Disabled 1 Interrupt Flag accumulator interrupt Enabled 6 Reserved Reserved n n 0 1 5 ZIENn PWM Zero Point Interrupt Enable Bits Each bit n controls the corresponding PWM channel n 0 Zero point interrupt Disabled 1 Zero point interrupt Enabled Note Odd channels will read always 0 at complementary mode ...

Page 485: ...Brake interrupt for channel2 3 Enabled Note This register is write protected Refer to SYS_REGLCTL register 8 BRKLIEN0_1 PWM Level detect Brake Interrupt Enable for Channel0 1 Write Protect 0 Level detect Brake interrupt for channel0 1 Disabled 1 Level detect Brake interrupt for channel0 1 Enabled Note This register is write protected Refer to SYS_REGLCTL register 7 3 Reserved Reserved 2 BRKEIEN4_5...

Page 486: ...NUC126 Aug 08 2018 Page 486 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL Note This register is write protected Refer to SYS_REGLCTL register ...

Page 487: ...s another CMPDIF for channel 0 2 4 23 IFAIF4_5 PWM Channel 4 5 Interrupt Flag Accumulator Interrupt Flag Flag is set by hardware when condition match IFSEL4_5 bits in PWM_IFA register software can clear this bit by writing 1 to it 22 Reserved Reserved n 16 n 0 1 5 CMPUIFn PWM Compare Up Count Interrupt Flag Flag is set by hardware when PWM counter up count and reaches CMP PWM_CMPDATn 15 0 software...

Page 488: ...ondition match IFSEL0_1 bits in PWM_IFA register software can clear this bit by writing 1 to it 6 Reserved Reserved n n 0 1 5 ZIFn PWM Zero Point Interrupt Flag Each bit n controls the corresponding PWM channel n This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero ...

Page 489: ...cleared by hardware When enabled brake source return to high level PWM will release brake state until current PWM period finished The PWM waveform will start output from next full PWM period 23 22 Reserved Reserved n 16 n 0 1 5 BRKESTSn PWM Channel N Edge detect Brake Status 0 PWM channel n edge detect brake state is released 1 When PWM channel n edge detect brake detects a falling edge of any ena...

Page 490: ...l to PERIOD in channel 4 010 CNT equal to CMPU in channel 4 011 CNT equal to CMPD in channel 4 100 CNT equal to Zero in channel 5 101 CNT equal to PERIOD in channel 5 110 CNT equal to CMPU in channel 5 111 CNT equal to CMPD in channel 5 19 16 IFCNT4_5 PWM Channel 4 5 Interrupt Flag Counter The register sets the count number which defines how many times of PWM Channel 4 5 period occurs to set IFAIF...

Page 491: ...nterrupt flag accumulator Disabled 1 PWM Channel 0 1 interrupt flag accumulator Enabled 6 4 IFSEL0_1 PWM Channel 0 1 Interrupt Flag Accumulator Source Select 000 CNT equal to Zero in channel 0 001 CNT equal to PERIOD in channel 0 010 CNT equal to CMPU in channel 0 011 CNT equal to CMPD in channel 0 100 CNT equal to Zero in channel 1 101 CNT equal to PERIOD in channel 1 110 CNT equal to CMPU in cha...

Page 492: ...od point 0010 PWM_CH2 zero or period point 0011 PWM_CH2 up count compared point 0100 PWM_CH2 down count compared point 0101 PWM_CH3 zero point 0110 PWM_CH3 period point 0111 PWM_CH3 zero or period point 1000 PWM_CH3 up count compared point 1001 PWM_CH3 down count compared point 1010 PWM_CH0 up count free trigger compared point 1011 PWM_CH0 down count free trigger compared point 1100 PWM_CH2 up cou...

Page 493: ...ed point 0101 PWM_CH1 zero point 0110 PWM_CH1 period point 0111 PWM_CH1 zero or period point 1000 PWM_CH1 up count compared point 1001 PWM_CH1 down count compared point 1010 PWM_CH0 up count free trigger compared point 1011 PWM_CH0 down count free trigger compared point 1100 PWM_CH2 up count free trigger compared point 1101 PWM_CH2 down count free trigger compared point 1110 PWM_CH4 up count free ...

Page 494: ... Page 494 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 1101 PWM_CH2 down count free trigger compared point 1110 PWM_CH4 up count free trigger compared point 1111 PWM_CH4 down count free trigger compared point ...

Page 495: ...M_CH4 zero point 0001 PWM_CH4 period point 0010 PWM_CH4 zero or period point 0011 PWM_CH4 up count compared point 0100 PWM_CH4 down count compared point 0101 PWM_CH5 zero point 0110 PWM_CH5 period point 0111 PWM_CH5 zero or period point 1000 PWM_CH5 up count compared point 1001 PWM_CH5 down count compared point 1010 PWM_CH0 up count free trigger compared point 1011 PWM_CH0 down count free trigger ...

Page 496: ...H5 period point 0111 PWM_CH5 zero or period point 1000 PWM_CH5 up count compared point 1001 PWM_CH5 down count compared point 1010 PWM_CH0 up count free trigger compared point 1011 PWM_CH0 down count free trigger compared point 1100 PWM_CH2 up count free trigger compared point 1101 PWM_CH2 down count free trigger compared point 1110 PWM_CH4 up count free trigger compared point 1111 PWM_CH4 down co...

Page 497: ...WM Free Trigger Compare Register 2 3 0x0000_0000 PWM_FTCMP DAT4_5 PWMx_BA 0x108 R W PWM Free Trigger Compare Register 4 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 FTCMP 7 6 5 4 3 2 1 0 FTCMP Bits Description 31 16 Reserved Reserved 15 0 FTCMP PWM Free Trigger Compare Register FTCMP use to compare with even CNT PWM_CNTm 15 0 m 0 2 4 to trig...

Page 498: ...erved SSEN5 SSEN4 SSEN3 SSEN2 SSEN1 SSEN0 Bits Description 31 9 Reserved Reserved 8 SSRC PWM Synchronous Start Source Select Bit 0 Synchronous start source come from PWM0 1 Synchronous start source come from PWM1 7 6 Reserved Reserved n n 0 1 5 SSENn PWM Synchronous Start Function Enable Bits When synchronous start function is enabled the PWM counter enable register PWM_CNTEN can be enabled by wri...

Page 499: ...eserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNTSEN Bits Description 31 1 Reserved Reserved 0 CNTSEN PWM Counter Synchronous Start Enable Write Only PMW counter synchronous enable function is used to make selected PWM channels PWMx_CHn start counting at the same time Writing this bit to 1 will also set the counter enable bit CNTENn n denotes chan...

Page 500: ... edge blanking counter start counting 10 When detect leading edge blanking source rising or falling edge blanking counter start counting 11 Reserved 15 11 Reserved Reserved 10 SRCEN4 PWM Leading Edge Blanking Source From PWMx_CH4 Enable Bit 0 PWM Leading Edge Blanking Source from PWMx_CH4 Disabled 1 PWM Leading Edge Blanking Source from PWMx_CH4 Enabled 9 SRCEN2 PWM Leading Edge Blanking Source Fr...

Page 501: ...0x11 C R W PWM Leading Edge Blanking Counter Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved LEBCNT 7 6 5 4 3 2 1 0 LEBCNT Bits Description 31 9 Reserved Reserved 8 0 LEBCNT PWM Leading Edge Blanking Counter This counter value decides leading edge blanking window size Blanking window size LEBCNT 1 and LEB counter clock base is E...

Page 502: ... corresponding PWM channel n 0 Indicates no ADC start of conversion trigger event has occurred 1 Indicates an ADC start of conversion trigger event has occurred software can write 1 to clear this bit 15 11 Reserved Reserved n 2 8 n 0 2 4 SYNCINFn Input Synchronization Latched Flag Each bit n controls the corresponding PWM channel n 0 Indicates no SYNC_IN event has occurred 1 Indicates an SYNC_IN e...

Page 503: ...19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CAPINEN5 CAPINEN4 CAPINEN3 CAPINEN2 CAPINEN1 CAPINEN0 Bits Description 31 6 Reserved Reserved n n 0 1 5 CAPINENn Capture Input Enable Bits Each bit n controls the corresponding PWM channel n 0 PWM Channel capture input path Disabled The input of PWM channel capture function is always regarded as 0 1 PWM Channel capture in...

Page 504: ... n 0 Falling capture reload counter Disabled 1 Falling capture reload counter Enabled 23 22 Reserved Reserved n 16 n 0 1 5 RCRLDENn Rising Capture Reload Enable Bits Each bit n controls the corresponding PWM channel n 0 Rising capture reload counter Disabled 1 Rising capture reload counter Enabled 15 14 Reserved Reserved n 8 n 0 1 5 CAPINVn Capture Inverter Enable Bits Each bit n controls the corr...

Page 505: ...n 31 14 Reserved Reserved n 8 n 0 1 5 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status Read Only This flag indicates if falling latch happened when the corresponding CFLIFn PWM_CAPIF 13 8 bit is 1 Each bit n controls the corresponding PWM channel n Note This bit will be cleared automatically when user clear corresponding CFLIFn bit 7 6 Reserved Reserved n n 0 1 5 CRLIFOVn Capture Risin...

Page 506: ...g Capture Data Register 2 0x0000_0000 PWM_RCAPD AT3 PWMx_BA 0x224 R PWM Rising Capture Data Register 3 0x0000_0000 PWM_RCAPD AT4 PWMx_BA 0x22C R PWM Rising Capture Data Register 4 0x0000_0000 PWM_RCAPD AT5 PWMx_BA 0x234 R PWM Rising Capture Data Register 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RCAPDAT 7 6 5 4 3 2 1 0 RCAPDAT Bits Descri...

Page 507: ... Capture Data Register 2 0x0000_0000 PWM_FCAPD AT3 PWMx_BA 0x228 R PWM Falling Capture Data Register 3 0x0000_0000 PWM_FCAPD AT4 PWMx_BA 0x230 R PWM Falling Capture Data Register 4 0x0000_0000 PWM_FCAPD AT5 PWMx_BA 0x238 R PWM Falling Capture Data Register 5 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 FCAPDAT 7 6 5 4 3 2 1 0 FCAPDAT Bits Desc...

Page 508: ...FCAPDAT4 5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits are set to 0x3 0 PWM_FCAPDAT4 5 register is the first captured data to memory 1 PWM_RCAPDAT4 5 register is the first captured data to memory 18 17 CAPMOD4_5 Select PWM_RCAPDAT4 5 or PWM_FCAPDAT4 5 to Do PDMA Transfer 00 Reserved 01 PWM_RCAPDAT4 5 register 10 PWM_FCAPDAT4 5 register 11 Both PWM_RCA...

Page 509: ...eserved Reserved 4 CHSEL0_1 Select Channel 0 1 to Do PDMA Transfer 0 Channel0 1 Channel1 3 CAPORD0_1 Capture Channel 0 1 Rising Falling Order Set this bit to determine whether the PWM_RCAPDAT0 1 or PWM_FCAPDAT0 1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to 0x3 0 PWM_FCAPDAT0 1 register is the first captured data to memory 1 PWM_RCAPDAT0 1 r...

Page 510: ...0_0000 PWM_PDMAC AP2_3 PWMx_BA 0x244 R PWM Capture Channel 2 3 PDMA Register 0x0000_0000 PWM_PDMAC AP4_5 PWMx_BA 0x248 R PWM Capture Channel 4 5 PDMA Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CAPBUF 7 6 5 4 3 2 1 0 CAPBUF Bits Description 31 16 Reserved Reserved 15 0 CAPBUF PWM Capture PDMA Register Read Only This register is used ...

Page 511: ... CAPRIEN0 Bits Description 31 14 Reserved Reserved n 8 n 0 1 5 CAPFIENn PWM Capture Falling Latch Interrupt Enable Bits Each bit n controls the corresponding PWM channel n 0 Capture falling edge latch interrupt Disabled 1 Capture falling edge latch interrupt Enabled Note When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled 7 6 Reserved Reserved n n 0 1 5 CAPRIENn PW...

Page 512: ...tch Interrupt Flag This bit is writing 1 to clear Each bit n controls the corresponding PWM channel n 0 No capture falling latch condition happened 1 Capture falling latch condition happened this flag will be set to high Note When Capture with PDMA operating corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data 7 6 Reserved Reserved n n 0 1 5 CRLIFn PWM Capture Rising ...

Page 513: ...r 0x0000_0000 PWM_PBUF2 PWMx_BA 0x30C R PWM PERIOD2 Buffer 0x0000_0000 PWM_PBUF3 PWMx_BA 0x310 R PWM PERIOD3 Buffer 0x0000_0000 PWM_PBUF4 PWMx_BA 0x314 R PWM PERIOD4 Buffer 0x0000_0000 PWM_PBUF5 PWMx_BA 0x318 R PWM PERIOD5 Buffer 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PBUF 7 6 5 4 3 2 1 0 PBUF Bits Description 31 16 Reserved Reserved 15 ...

Page 514: ...000_0000 PWM_CMPBU F2 PWMx_BA 0x324 R PWM CMPDAT2 Buffer 0x0000_0000 PWM_CMPBU F3 PWMx_BA 0x328 R PWM CMPDAT3 Buffer 0x0000_0000 PWM_CMPBU F4 PWMx_BA 0x32C R PWM CMPDAT4 Buffer 0x0000_0000 PWM_CMPBU F5 PWMx_BA 0x330 R PWM CMPDAT5 Buffer 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CMPBUF 7 6 5 4 3 2 1 0 CMPBUF Bits Description 31 16 Reserved R...

Page 515: ...SC0_1 Buffer 0x0000_0000 PWM_CPSCB UF2_3 PWMx_BA 0x338 R PWM CLKPSC2_3 Buffer 0x0000_0000 PWM_CPSCB UF4_5 PWMx_BA 0x33C R PWM CLKPSC4_5 Buffer 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved CPSCBUF 7 6 5 4 3 2 1 0 CPSCBUF Bits Description 31 12 Reserved Reserved 11 0 CPSCBUF PWM Counter Clock Pre scale Buffer Used as PWM counter clock p...

Page 516: ...40 R PWM FTCMPDAT0_1 Buffer 0x0000_0000 PWM_FTCBU F2_3 PWMx_BA 0x344 R PWM FTCMPDAT2_3 Buffer 0x0000_0000 PWM_FTCBU F4_5 PWMx_BA 0x348 R PWM FTCMPDAT4_5 Buffer 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 FTCMPBUF 7 6 5 4 3 2 1 0 FTCMPBUF Bits Description 31 16 Reserved Reserved 15 0 FTCMPBUF PWM FTCMPDAT Buffer Read Only Used as FTCMPDAT acti...

Page 517: ... Bits Description 31 11 Reserved Reserved n 2 8 n 0 2 4 FTCMDn PWM FTCMPDAT Down Indicator Indicator will be set to high when FTCMP PWM_FTCMPDATn 15 0 bits equal to PERIOD PWM_PERIODn 15 0 bits and DIRF PWM_CNTn 16 bit is 0 software can write 1 to clear this bit Each bit n controls the corresponding PWM channel n 7 3 Reserved Reserved n 2 n 0 2 4 FTCMUn PWM FTCMPDAT Up Indicator Indicator will be ...

Page 518: ...time hour minute second and calendar year month day settings in RTC_TALM and RTC_CALM Supports alarm time hour minute second and calendar year month day mask enable in RTC_TAMSK and RTC_CAMSK Selectable 12 hour or 24 hour time scale in RTC_CLKFMT register Supports Leap Year indication in RTC_LEAPYEAR register Supports Day of the Week counter in RTC_WEEKDAY register Frequency of RTC clock source co...

Page 519: ...2 18 Group Pin Name GPIO MFP X32 X32_IN PF 1 MFP1 X32_OUT PF 0 MFP1 6 14 5 Functional Description 6 14 5 1 RTC Initiation When an RTC block is powered on RTC is at reset state User has to write a special number 0xA5EB1357 to INIT RTC_INIT 31 0 to make RTC leaving reset state Once INIT has written as 0xA5EB1357 the RTC will be in normal active state permanently User can read ACTIVE RTC_INIT 0 to ch...

Page 520: ...ss Attribute 6 14 5 3 Frequency Compensation The FREQADJ RTC_FREQADJ 21 0 allows user to make digital compensation to a clock input for RTC application more accurate The FREQADJ default value is 0x00200000 if RTC clock source is LXT and 0x00080000 if RTC clock source is LIRC means no frequency compensate for actual RTC clock frequency Follow the example and formula below to write compensation valu...

Page 521: ... AM01 0x21 PM01 0x02 0x14 0x02 AM02 0x22 PM02 0x03 0x15 0x03 AM03 0x23 PM03 0x04 0x16 0x04 AM04 0x24 PM04 0x05 0x17 0x05 AM05 0x25 PM05 0x06 0x18 0x06 AM06 0x26 PM06 0x07 0x19 0x07 AM07 0x27 PM07 0x08 0x20 0x08 AM08 0x28 PM08 0x09 0x21 0x09 AM09 0x29 PM09 0x10 0x22 0x10 AM10 0x30 PM10 0x11 0x23 0x11 AM11 0x31 PM11 Table 6 14 212 24 Hour Time Scale Selection 6 14 5 6 Day of the Week Counter The RTC...

Page 522: ...ME RTC_CAL RTC_TALM and RTC_CALM registers are expressed in BCD format 2 User has to make sure that the loaded values are reasonable in specified fields For example load RTC_CAL as 201a year 13 month 00 day or RTC_CAL does not match with RTC_WEEKDAY etc 3 Registers value after core power and RTC battery power both first powered on are shown in Table 6 14 3 Register Default Value RTC_INIT 0 RTC_RWE...

Page 523: ... Power Domain RTC_CALM Battery Power Domain RTC_LEAPYEAR Battery Power Domain RTC_INTEN Core Power Domain RTC_INTSTS Core Power Domain RTC_TICK Battery Power Domain RTC_TAMSK Battery Power Domain RTC_CAMSK Battery Power Domain RTC_LXTCTL Battery Power Domain RTC_LXTOCTL Battery Power Domain RTC_LXTICTL Battery Power Domain RTC_PF2CTL Battery Power Domain RTC_DSTCTL Battery Power Domain Table 6 14 ...

Page 524: ...NUAL CTLSEL RTC PFx_OPMODE GPIO PFx_MODE GPIO PFx_DOUT RTC PFx_DOUT Output Buffer PF x RTC PFx_OPMODE GPIO PFx_MODE Weak Pull up Resistor 0 1 0 0 0 1 1 1 GPIO PFx_SMTEN VBAT Pull Up Control Logic Output Enable Control Logic Pin input x 0 1 2 Figure 6 14 2 Backup I O Control Diagram ...

Page 525: ...RTC_TALM RTC_BA 0x1C R W RTC Time Alarm Register 0x0000_0000 RTC_CALM RTC_BA 0x20 R W RTC Calendar Alarm Register 0x0000_0000 RTC_LEAPYEAR RTC_BA 0x24 R RTC Leap Year Indicaton Register 0x0000_0000 RTC_INTEN RTC_BA 0x28 R W RTC Interrupt Enable Register 0x0000_0000 RTC_INTSTS RTC_BA 0x2C R W RTC Interrupt Status Register 0x0000_0000 RTC_TICK RTC_BA 0x30 R W RTC Time Tick Register 0x0000_0000 RTC_T...

Page 526: ...IT 15 14 13 12 11 10 9 8 INIT 7 6 5 4 3 2 1 0 INIT INIT 0 ACTIVE Bits Description 31 1 INIT RTC Initiation When RTC block is first powered on RTC is at reset state User has to write a special number 0xA5EB1357 to INIT to make RTC leaving reset state Once the INIT is written as 0xA5EB1357 the RTC will be at normal active state permanently The INIT 31 1 is a write only field and read value will be a...

Page 527: ...ster write Enabled Note RTCBUSY falg will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles 23 17 Reserved Reserved 16 RWENF RTC Register Access Enable Bit Read Only 0 RTC register read write Disabled 1 RTC register read write Enabled Note1 This bit will be set after RWEN is load a 0xA965 and be cleared automatically after 1024 RTC clocks expired Note2 RWENF wil...

Page 528: ...sation Register 0x0020_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved FREQADJ 15 14 13 12 11 10 9 8 FREQADJ 7 6 5 4 3 2 1 0 FREQADJ Bits Description 31 22 Reserved Reserved 21 0 FREQADJ Frequency Compensation Value User has to get actual clock frequency of LXT LXT frequency FCR 0x200000 32768 LXT frequency Note This formula is suitable only when RTCSEL CLK_CLKSEL2 18 is 0 R...

Page 529: ... Bits Description 31 24 Reserved Reserved 21 20 TENHR 10 hour Time Digit 0 2 Note When RTC runs as 12 hour time scale mode RTC_TIME 21 the high bit of TENHR 1 0 means AM PM indication RTC_TIME 21 is 0 means AM hour and RTC_TIME 21 is 1 means PM hour 19 16 HR 1 Hour Time Digit 0 9 15 Reserved Reserved 14 12 TENMIN 10 Min Time Digit 0 5 11 8 MIN 1 Min Time Digit 0 9 7 Reserved Reserved 6 4 TENSEC 10...

Page 530: ...13 12 11 10 9 8 Reserved TENMON MON 7 6 5 4 3 2 1 0 Reserved TENDAY DAY Bits Description 31 24 Reserved Reserved 23 20 TENYEAR 10 Year Calendar Digit 0 9 19 16 YEAR 1 Year Calendar Digit 0 9 15 13 Reserved Reserved 12 TENMON 10 Month Calendar Digit 0 1 11 8 MON 1 Month Calendar Digit 0 9 7 6 Reserved Reserved 5 4 TENDAY 10 Day Calendar Digit 0 3 3 0 DAY 1 Day Calendar Digit 0 9 Note 1 RTC_CAL is a...

Page 531: ...ection Register 0x0000_0001 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved 24HEN Bits Description 31 1 Reserved Reserved 0 24HEN 24 hour 12 hour Time Scale Selection Indicates that RTC_TIME and RTC_TALM register are in 24 hour time scale or 12 hour time scale 0 12 hour time scale with AM and PM indication selected 1 24 hour...

Page 532: ...f the Week Register 0x0000_0006 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WEEKDAY Bits Description 31 3 Reserved Reserved 2 0 WEEKDAY Day of the Week Register 000 Sunday 001 Monday 010 Tuesday 011 Wednesday 100 Thursday 101 Friday 110 Saturday 111 Reserved Note RTC will not check WEEKDAY setting with RTC_CAL is reasona...

Page 533: ...21 20 TENHR 10 Hour Time Digit of Alarm Setting 0 2 When RTC runs as 12 hour time scale mode RTC_TIME 21 the high bit of TENHR 1 0 means AM PM indication If RTC_TIME 21 is 1 it indicates PM time message 19 16 HR 1 Hour Time Digit of Alarm Setting 0 9 15 Reserved Reserved 14 12 TENMIN 10 Min Time Digit of Alarm Setting 0 5 11 8 MIN 1 Min Time Digit of Alarm Setting 0 9 7 Reserved Reserved 6 4 TENSE...

Page 534: ...eserved TENDAY DAY Bits Description 31 24 Reserved Reserved 23 20 TENYEAR 10 Year Calendar Digit of Alarm Setting 0 9 19 16 YEAR 1 Year Calendar Digit of Alarm Setting 0 9 15 13 Reserved Reserved 12 TENMON 10 Month Calendar Digit of Alarm Setting 0 1 11 8 MON 1 Month Calendar Digit of Alarm Setting 0 9 7 6 Reserved Reserved 5 4 TENDAY 10 Day Calendar Digit of Alarm Setting 0 3 3 0 DAY 1 Day Calend...

Page 535: ...n Reset Value RTC_LEAPYE AR RTC_BA 0x24 R RTC Leap Year Indicaton Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved LEAPYEAR Bits Description 31 1 Reserved Reserved 0 LEAPYEAR Leap Year Indication Register Read Only 0 This year is not a leap year 1 This year is leap year ...

Page 536: ...Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TICKIEN ALMIEN Bits Description 31 2 Reserved Reserved 1 TICKIEN Time Tick Interrupt Enable Bit 0 RTC time tick interrupt Disabled 1 RTC time tick interrupt Enabled 0 ALMIEN Alarm Interrupt Enable Bit 0 RTC alarm interrupt Disabled 1 RTC alarm interr...

Page 537: ...a time tick interrupt signal will be generated if TICKIEN RTC_INTEN 1 is enabled Chip will also be waken up when time tick interrupt signal occurred if chip is running at Power down mode 0 Tick condition did not occur 1 Tick condition occurred Note Writing 1 to clear this bit 0 ALMIF RTC Alarm Interrupt Flag When current RTC counter in RTC_TIME and RTC_CAL are matched RTC alarm settings in RTC_TAL...

Page 538: ...19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TICK Bits Description 31 3 Reserved Reserved 2 0 TICK Time Tick Register These bits are used to select RTC time tick period for periodic time tick interrupt request 000 Time tick is 1 second 001 Time tick is 1 2 second 010 Time tick is 1 4 second 011 Time tick is 1 8 second 100 Time tick is 1 16 second 101 Time tick is 1 ...

Page 539: ...rved 7 6 5 4 3 2 1 0 Reserved MTENHR MHR MTENMIN MMIN MTENSEC MSEC Bits Description 31 6 Reserved Reserved 5 MTENHR Mask 10 hour Time Digit of Alarm Setting 0 2 Note MTENHR function is only for 24 hour time scale mode 4 MHR Mask 1 hour Time Digit of Alarm Setting 0 9 Note MHR function is only for 24 hour time scale mode 3 MTENMIN Mask 10 Min Time Digit of alarm setting 0 5 2 MMIN Mask 1 Min Time D...

Page 540: ...17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved MTENYEAR MYEAR MTENMON MMON MTENDAY MDAY Bits Description 31 6 Reserved Reserved 5 MTENYEAR Mask 10 Year Calendar Digit of alarm setting 0 9 4 MYEAR Mask 1 Year Calendar Digit of alarm setting 0 9 3 MTENMON Mask 10 Month Calendar Digit of alarm setting 0 1 2 MMON Mask 1 Month Calendar Digit of alarm setting 0 9 1 MTENDAY Mask 1...

Page 541: ... 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved GAIN Reserved Bits Description 31 4 Reserved Reserved 3 1 GAIN Oscillator Gain Option User can select oscillator gain according to crystal external loading and operating temperature range The larger gain value corresponding to stronger driving capability and higher power consumption 000 L0 mode 001 L1 mode 010 L...

Page 542: ...m CTLSEL to decide X32KO PF 0 I O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL register 0 X32KO PF 0 pin I O function is controlled by GPIO module 1 X32KO PF 0 pin I O function is controlled by OPMODE and DOUT in RTC_LXTOCT at VBAT power domain Note CTLSEL will be set to 1 automatically by hardware when system power is turned off and RTC is at normal a...

Page 543: ... CTLSEL to decide X32KI PF 1 I O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL register 0 X32KI PF 1 pin I O function is controlled by GPIO module 1 X32KI PF 1 pin I O function is controlled by OPMODE and DOUT in RTC_LXTICTL at VBAT power domain Note CTLSEL will be set to 1 automatically by hardware when system power is turned off and RTC is at normal a...

Page 544: ...nction is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL register 0 GPIO PF 2 pin I O function is controlled by GPIO module 1 GPIO PF 2 pin I O function is controlled by OPMODE and DOUT in RTC_PF2CTL at VBAT power domain Note CTLSEL will be set to 1 automatically by hardware when system power is turned off and RTC is at normal active state ACTIVE RTC_INIT 0 is 1 2 D...

Page 545: ...rved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DSBAK SUBHR ADDHR Bits Description 31 3 Reserved Reserved 2 DSBAK Daylight Saving Back 0 Daylight Saving Time function is not performed 1 Daylight Saving Time function is performed 1 SUBHR Subtract 1 Hour 0 No effect 1 Indicates RTC hour digit has been subtracted one hour for winter time change 0 ADDHR Ad...

Page 546: ...rts hardware activation sequence process and the interval between PWR on and CLK start is configurable Supports hardware warm reset sequence process Supports hardware deactivation sequence process Supports hardware auto deactivation sequence when detected the card removal Supports UART mode Full duplex asynchronous communications Separates receiving transmitting 4 bytes entry FIFO for data payload...

Page 547: ...EEP0 1 SC0DIV 1 SC0CKEN Engine Clock SC1 CLK CLKKEEP1 SC1_PINCTL 6 SC1SEL CLKSEL3 3 2 CLKDIV1 15 8 CLK_APBCLK1 1 SC1DIV SC1CKEN CLKKEEP1 PCLK1 00 01 10 11 SC1SEL PLL HXT HIRC PCLK1 Figure 6 15 1 SC Clock Control Diagram TX_FIFO TX RX Control Unit RX_FIFO TX Shift Register ETU Clock Generator RX Shift Register SC_DATA_EN SC_PWR SC_RST SC_CLK Card Detect Card Detect Clock Generator Interface Signal ...

Page 548: ...is shown in Table 6 15 2 Pin Type Description SC_DATA Input UART Receive Data SC_CLK Output UART Transmit Data Table 6 15 2 UART Pin Description 6 15 4 1 Basic Configuration of SC0 Clock Source Configuration Select the source of SC0 peripheral clock on SC0SEL CLK_CLKSEL3 1 0 Select the clock divider number of SC0 peripheral clock on SC0DIV CLK_CLKDIV1 7 0 Enable SC0 peripheral clock in SC0CKEN CLK...

Page 549: ...P6 SC1_DAT PA 10 MFP5 PB 7 MFP6 SC1_PWR PA 9 MFP5 PB 6 MFP6 SC1_RST PA 8 MFP5 PB 5 MFP6 SC1_nCD PF 5 MFP5 PB 4 MFP6 6 15 5 Functional Description Basically the smart card interface acts as a half duplex asynchronous communication port and its data format is composed of ten consecutive bits which is shown in Figure 6 15 3 Start Pause Start D1 Delay Between Consecutive Characters D2 D3 D4 D5 D6 D7 D...

Page 550: ... SC_RST assert T2 can be selected by programming INITSEL SC_ALTCTL 9 8 This programming procedure provides user with a simple setting for activation sequence The following describes the activation control sequence in hardware activation mode 1 Set activation timing by setting INITSEL SC_ALTCTL 9 8 2 Timer0 can be selected by setting TMRSEL SC_CTL 14 13 is 11 3 Set operation mode OPMODE SC_TMRCTL0 ...

Page 551: ...re provides user with a simple setting for warm reset sequence The following is the warm reset control sequence by hardware 1 Set warm reset timing by setting INITSEL SC_ALTCTL 9 8 2 Select Timer0 by setting TMRSEL SC_CTL 14 13 to 11 3 Set operation mode OPMODE SC_TMRCTL0 27 24 to 0011 and give an Answer to Request ATR value by setting CNT SC_TMRCTL0 23 0 register 4 Set CNTEN0 SC_ALTCTL 5 and WARS...

Page 552: ... SC_RST low T7 SC_RST low to SC_CLK stop T8 and SC_CLK stop to SC_PWR de assert T9 can be selected by programming INITSEL SC_ALTCTL 9 8 This programming procedure provides user with a simple setting for deactivation sequence When hardware de asserts SC_PWR to low the SC controller will generate an interrupt flag INITIF SC_INTSTS 8 and inform to CPU at the same time if INITIEN SC_INTEN 8 is 1 The S...

Page 553: ...s 1101_1100 it is direct convention When decoded by direct convention the conveyed byte is equal to 0x3B User can set AUTOCEN SC_CTL 3 and then the operating convention will be decided by hardware User can also set CONSEL SC_CTL 5 4 set 00 or 11 to change the operating convention after SC received TS of Answer to Request ATR If auto convention function is enabled by setting AUTOCEN SC_CTL 3 the se...

Page 554: ...transfer error interrupt signal to CPU User can also enable received retry function by setting RXRTYEN SC_CTL 19 and define the received retry number limitation in RXRTY SC_CTL 18 16 The receiver retry number is up to RXRTY 1 if the number of received errors by receiver is equal to RXRTY 1 receiver will receive this error data to buffer and RXOVERR SC_STATUS 22 flag will be set by hardware If TERR...

Page 555: ... 7 0 SC_TMRCTL2 7 0 1 Start Start counting when the first START bit reception or transmission detected after CNTENx SC_ALTCTL 7 5 set to 1 End When the down counter equals 0 hardware will set TMRxIF SC_INTSTS 5 3 and clear CNTENx SC_ALTCTL 7 5 automatically 0010 The down counter is started when the first START bit reception detected and ended when counter time out It takes 2 ETU to detect first ST...

Page 556: ...dware will set TMRxIF SC_INTSTS 5 3 and generate an interrupt signal to inform CPU if TMRxIEN SC_INTEN 5 3 enabled The time out value will be CNT SC_TMRCTL0 23 0 SC_TMRCTL1 7 0 SC_TMRCTL2 7 0 1 End The down counter stopped when user clears CNTENx SC_ALTCTL 7 5 bit 0110 Start The down counter is started when the first START bit reception detected after CNTENx SC_ALTCTL 7 5 set to 1 It takes 2 ETU t...

Page 557: ...tive characters between different transfer directions which are shown in Figure 6 15 10 and Figure 6 15 11 This field indicates the counter for the bit length of block guard time According to ISO7816 3 in T 0 mode user must fill 15 real block guard time 16 5 to this field in T 1 mode user must fill 21 real block guard time 22 5 to it In transmit direction the smart card sends data to smart card ho...

Page 558: ...urn idle state 3 In UART mode CONSEL SC_CTL 5 4 and AUTOCEN SC_CTL 3 fields must be set to 0 4 Select the UART baud rate by setting ETURDIV SC_ETUCTL 11 0 fields For example if smartcard module clock is 12 MHz and target baud rate is 115200 bps ETURDIV should fill with 12000000 115200 1 5 Select the data format include data length by setting WLS SC_UARTCTL 5 4 parity format by setting OPE SC_UARTC...

Page 559: ... 0x14 R W SC Element Time Unit Control Register 0x0000_0173 SC_INTEN SCx_BA 0x18 R W SC Interrupt Enable Control Register 0x0000_0000 SC_INTSTS SCx_BA 0x1C R W SC Interrupt Status Register 0x0000_0002 SC_STATUS SCx_BA 0x20 R W SC Transfer Status Register 0x0000_x202 SC_PINCTL SCx_BA 0x24 R W SC Pin Control State Register 0x0000_00x0 SC_TMRCTL0 SCx_BA 0x28 R W SC Timer0 Control Register 0x0000_0000...

Page 560: ...ansmit Holding Buffer Register Undefined 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DAT Bits Description 31 8 Reserved Reserved 7 0 DAT Receive Transmit Holding Buffer Write Operation By writing data to DAT the SC will send out an 8 bit data Read Operation By reading DAT the SC will return an 8 bit received data Note If SCEN SC_...

Page 561: ... to low it indicates a card is detected 1 When hardware detects the card detect pin SC_CD from low to high it indicates a card is detected Note User must select card detect level before Smart Card controller enabled 25 24 CDDBSEL Card Detect De bounce Selection This field indicates the card detect de bounce selection 00 De bounce sample card insert once per 384 128 3 SC modue clocks and de bounce ...

Page 562: ...al timer function Disabled 11 Internal 24 bit Timer0 and two 8 bit Timer0 and Timer1 are enabled User can configure them by setting SC_TMRCTL0 23 0 SC_TMRCTL1 7 0 and SC_TMRCTL2 7 0 Other configurations are reserved 12 8 BGT Block Guard Time BGT Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions This field indic...

Page 563: ... and CONSEL SC_CTL 5 4 will be set to 11 Note2 If the first data is not 0x3B or 0x3F hardware will set ACERRIF SC_INTSTS 10 and generate an interrupt signal to inform CPU when ACERRIEN SC_INTEN 10 is enabled 2 TXOFF TX Transition Disable Bit This bit is used to disable Tx transmit function 0 The transceiver Enabled 1 The transceiver Disabled 1 RXOFF RX Transition Disable Bit This bit is used to di...

Page 564: ...6 Reserved Reserved 15 ACTSTS2 Internal Timer2 Active Status Read Only This bit indicates the timer counter status of timer2 0 Timer2 is not active 1 Timer2 is active Note Timer2 is active does not always mean timer2 is counting the CNT SC_TMRCTL2 7 0 14 ACTSTS1 Internal Timer1 Active Status Read Only This bit indicates the timer counter status of timer1 0 Timer1 is not active 1 Timer1 is active N...

Page 565: ...n TMRSEL SC_CTL 14 13 is not equale to 11 Note2 If the operation mode is not in auto reload mode SC_TMRCTL2 26 0 this bit will be auto cleared by hardware Note3 If SCEN SC_CTL 0 is not enabled this filed cannot be programmed 6 CNTEN1 Internal Timer1 Start Enable Bit This bit enables Timer 1 to start counting User can fill 0 to stop count and set 1 to reload and start count The counter unit is ETU ...

Page 566: ...EN SC_CTL 0 is not enabled this filed cannot be programmed 2 DACTEN Deactivation Sequence Generator Enable Bit This bit enables SC controller to initiate the card by deactivation sequence 0 No effect 1 Deactivation sequence generator Enabled Note1 When the deactivation sequence completed this bit will be cleared automatically and the INITIF SC_INTSTS 8 will be set to 1 Note2 This field will be cle...

Page 567: ...on Reset Value SC_EGT SCx_BA 0x0C R W SC Extra Guard Time Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 EGT Bits Description 31 8 Reserved Reserved 7 0 EGT Extra Guard Time This field indicates the extra guard time value Note The extra guard time unit is ETU base ...

Page 568: ... Description 31 9 Reserved Reserved 8 0 RFTM SC Receiver FIFO Time out Counter The time out down counter resets and starts counting whenever the Rx buffer received a new data Once the counter decrease to 1 and no new data is received or CPU does not read data by reading DAT SC_DAT 7 0 a receiver time out flag RXTOIF SC_INTSTS 9 will be set and hardware will generate an interrupt signal to inform C...

Page 569: ...ent Time Unit Control Register 0x0000_0173 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved ETURDIV 7 6 5 4 3 2 1 0 ETURDIV Bits Description 31 12 Reserved Reserved 11 0 ETURDIV ETU Rate Divider The field is used for define ETU time unit The real ETU time unit is ETURDIV 1 SC clock time Note User can configure this field but this field must be greate...

Page 570: ...eceiver buffer time out interrupt 0 Receiver buffer time out interrupt Disabled 1 Receiver buffer time out interrupt Enabled 8 INITIEN Initial End Interrupt Enable Bit This field is used to enable activation ACTEN SC_ALTCTL 3 1 deactivation DACTEN SC_ALTCTL 2 1 and warm reset WARSTEN SC_ALTCTL 4 sequence complete interrupt 0 Initial end interrupt Disabled 1 Initial end interrupt Enabled 7 CDIEN Ca...

Page 571: ...k error BEF SC_STATUS 6 frame error FEF SC_STATUS 5 parity error PEF SC_STATUS 4 receive buffer overflow error RXOV SC_STATUS 0 transmit buffer overflow error TXOV SC_STATUS 8 receiver retry over limit error RXOVERR SC_STATUS 22 or transmitter retry over limit error TXOVERR SC_STATUS 30 0 Transfer error interrupt Disabled 1 Transfer error interrupt Enabled 1 TXEIEN Transmit Buffer Empty Interrupt ...

Page 572: ... time out interrupt status flag 0 Receive buffer time out interrupt did not occur 1 Receive buffer time out interrupt occurred Note This bit is read only user must read all receive buffer remaining data by reading DAT SC_DAT 7 0 to clear it 8 INITIF Initial End Interrupt Status Flag This field is used for activation ACTEN SC_ALTCTL 3 deactivation DACTEN SC_ALTCTL 2 and warm reset WARSTEN SC_ALTCTL...

Page 573: ...ATUS which includes receiver break error BEF SC_STATUS 6 frame error FEF SC_STATUS 5 parity error PEF SC_STATUS 4 receive buffer overflow error RXOV SC_STATUS 0 transmit buffer overflow error TXOV SC_STATUS 8 receiver retry over limit error RXOVERR SC_STATUS 22 or transmitter retry over limit error TXOVERR SC_STATUS 30 0 Transfer error interrupt did not occur 1 Transfer error interrupt occurred No...

Page 574: ... used for transmitter retry counts over than retry number limitation 0 Transmitter retries counts is not over than TXRTY SC_CTL 22 20 1 1 Transmitter retries counts over than TXRTY SC_CTL 22 20 1 Note This bit can be cleared by writing 1 to it 29 TXRTYERR Transmitter Retry Error This bit is used for indicate transmitter error retry and set by hardware 0 No Tx retry transfer 1 Tx has any error and ...

Page 575: ...POINT increases one When one byte in Rx buffer is read by reading DAT SC_DAT 7 0 RXPOINT decreases one 15 14 Reserved Reserved 13 CDPINSTS Card Detect Pin Status Read Only This bit is the pin status of SC_CD 0 The SC_CD pin state at low 1 The SC_CD pin state at high 12 CINSERT Card Insert Status of SC_CD Pin This bit is set whenever card has been inserted 0 No effect 1 Card insert Note1 This bit c...

Page 576: ...er frame error flag did not occur 1 Receiver frame error flag occurred Note1 This bit can be cleared by writing 1 to it Note2 If user sets receiver retries function by setting RXRTYEN SC_CTL 19 hardware will not set this flag 4 PEF Receiver Parity Error Status Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit 0 Receiver parity error flag did not occur...

Page 577: ...hen writing a new value to SC_PINCTL register 0 Synchronizing is completion user can write new data to SC_PINCTL register 1 Last value is synchronizing 29 19 Reserved Reserved 18 RSTSTS SC_RST Pin Status Read Only This bit is the pin status of SC_RST 0 SC_RST pin is low 1 SC_RST pin is high 17 PWRSTS SC_PWR Pin Status Read Only This bit is the pin status of SC_PWR 0 SC_PWR pin to low 1 SC_PWR pin ...

Page 578: ...activation mode this bit will be changed automatically Thus do not fill in this field when operating in these modes 5 2 Reserved Reserved 1 SCRST SC_RST Pin Signal This bit is the signal status of SC_RST but user can drive SC_RST pin to high or low by control this bit Write this bit can drive SC_RST pin 0 Drive SC_RST pin to low 1 Drive SC_RST pin to high Read this bit to get SC_RST signal status ...

Page 579: ...cription 31 SYNC SYNC Flag Indicator Read Only Due to synchronization user should check this bit when writing a new value to SC_TMRCTL0 register 0 Synchronizing is completion user can write new data to SC_TMRCTL0 register 1 Last value is synchronizing 30 28 Reserved Reserved 27 24 OPMODE Timer 0 Operation Mode Selection This field indicates the internal 24 bit Timer0 operation selection Refer to T...

Page 580: ...ion 31 SYNC SYNC Flag Indicator Read Only Due to synchronization user should check this bit when writing a new value to SC_TMRCTL1 register 0 Synchronizing is completion user can write new data to SC_TMRCTL1 register 1 Last value is synchronizing 30 28 Reserved Reserved 27 24 OPMODE Timer 1 Operation Mode Selection This field indicates the internal 8 bit Timer1 operation selection Refer to Table 6...

Page 581: ...ion 31 SYNC SYNC Flag Indicator Read Only Due to synchronization user should check this bit when writing a new value to SC_TMRCTL2 register 0 Synchronizing is completion user can write new data to SC_TMRCTL2 register 1 Last value is synchronizing 30 28 Reserved Reserved 27 24 OPMODE Timer 2 Operation Mode Selection This field indicates the internal 8 bit Timer2 operation selection Refer to Table 6...

Page 582: ...bit is generated or checked between the last data word bit and stop bit of the serial data 1 Parity bit is not generated transmitting data or checked receiving data during transfer Note In smart card mode this bit must be 0 default setting is with parity bit 5 4 WLS Word Length Selection This field is used to select UART data transfer length 00 Word length is 8 bits 01 Word length is 7 bits 10 Wor...

Page 583: ... Description Reset Value SC_TMRDAT0 SCx_BA 0x38 R SC Timer0 Current Data Register 0x0000_07FF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CNT0 15 14 13 12 11 10 9 8 CNT0 7 6 5 4 3 2 1 0 CNT0 Bits Description 31 24 Reserved Reserved 23 0 CNT0 Timer0 Current Data Value Read Only This field indicates the current counter values of Timer0 ...

Page 584: ... 0 CNT1 Bits Description 31 16 Reserved Reserved 15 8 CNT2 Timer2 Current Data Value Read Only This field indicates the current counter values of Timer2 7 0 CNT1 Timer1 Current Data Value Read Only This field indicates the current counter values of Timer1 SC Activation Control Register SC_ACTCTL Register Offset R W Description Reset Value SC_ACTCTL SCx_BA 0x4C R W SC Activation Control Register 0x...

Page 585: ...e the configurable cycles to extend the activation time T1 period Please refer to SC activation sequence in Figure 6 15 4 The cycle scaling factor is 2048 and Extend cycles T1EXT 2048 cycles For example If SCLK is 4MHz each clock cycle is 0 25us Filled 20 to T1EXT then Extend time 20 2048 0 25us 10 24 ms Note Setting 0 to this field conforms to the protocol ISO IEC 7816 3 ...

Page 586: ...is controller also supports the PDMA function to access the data buffer The SPI controller also support I 2 S mode to connect external audio CODEC 6 16 2 Features SPI Mode Up to two sets of SPI controllers Supports Master or Slave mode operation Configurable bit length of a transaction word from 8 to 32 bit Provides separate 4 level depth transmit and receive FIFO buffers Supports MSB first or LSB...

Page 587: ...t register buffer The receive control logic will store the received data to this buffer The FIFO buffer data can be read from SPIx_RX register by software TX Shift Register The transmit shift register is a 32 bit wide register buffer The transmit data is loaded from the TX FIFO buffer and shifted out bit by bit to the skew buffer RX Shift Register The receive shift register is also a 32 bit wide r...

Page 588: ...B 5 PC 3 PC 10 PE 11 MFP2 SPI0_SS PB 4 PC 2 PC 13 PE 12 MFP2 6 16 4 2 Basic Configuration of SPI1 Clock source Configuration Select the source of SPI1 peripheral clock on SPI1SEL CLK_CLKSEL2 27 26 Enable SPI1 peripheral clock in SPI1CKEN CLK_APBCLK0 13 Reset Configuration Reset SPI1 controller in SPI1RST SYS_IPRST1 13 Pin Configuration Group Pin Name GPIO MFP SPI1 SPI1_CLK PE 13 MFP1 PA 7 PD 4 PD ...

Page 589: ... SPIx_CLKDIV and the clock source which can be HXT PLL PCLK0 or HIRC48 SPIxSEL of CLK_CLKSEL2 register determines the clock source of the peripheral clock The DIVIDER SPIx_CLKDIV 7 0 setting determines the divisor of the clock rate calculation SPIx Clock Divider SPIx_CLKDIV 7 0 SPIx_I2SCLK 16 8 SPIxSEL HXT PLL PCLK0 HIRC48 SPIxCKEN SPIx Peripheral Clock Note x 0 1 SPI0SEL CLK_CLKSEL2 25 24 SPI0CKE...

Page 590: ...the slave select output pin SPIx_SS In Slave mode the off chip master device drives the slave selection signal from the SPIx_SS input port to this SPI controller The duration between the slave select active edge and the first SPI clock input shall over 3 SPI peripheral clock cycles of slave In Master Slave mode the active state of slave selection signal can be programmed to low or high active in S...

Page 591: ...the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word The default value of SUSPITV is 0x3 3 5 SPI clock cycles 6 16 5 2 Automatic Slave Selection In Master mode if AUTOSS SPIx_SSCTL 3 is set the slave selection signal will be generated automatically and output to the SPIx_SS pin according to whether SS SPIx_SSCTL 0 is ...

Page 592: ...t as MSB first LSB 0 and the REORDER SPIx_CTL 19 is set to 1 the data stored in the TX buffer and RX buffer will be rearranged in the order as Byte0 Byte1 Byte2 Byte3 in 32 bit transfer DWIDTH 0 The sequence of transmitted received data will be Byte0 Byte1 Byte2 and then Byte3 If the DWIDTH is set as 24 bit transfer mode the data in TX buffer and RX buffer will be rearranged as unknown byte Byte0 ...

Page 593: ...K SPIx_MISO SPIx_MOSI TX 6 TX 0 TX 15 TX 14 TX 8 RX 6 RX 0 RX 14 RX 8 MSB RX 7 Suspend Interval 1st Transaction Byte 2nd Transaction Byte RX 15 MSB TX 7 Note Timing Condition is CLKPOL 0 LSB 0 TXNEG 1 DWIDTH 0 REORDER 1 and SLAVE 0 Figure 6 16 9 Timing Waveform for Byte Suspend 6 16 5 4 Half Duplex Communication The SPI controller can communicate in half duplex mode by setting HALFDPX SPIx_CTL 14 ...

Page 594: ...PIx_MOSI pin of SPI Master device is not used for communication and can be configured as GPIO The status BUSY SPIx_STATUS 0 will be asserted in receive only mode due to the generation of SPI bus clock Entering this mode will produce the TXRST SPIx_FIFOCTL 1 and RXRST SPIx_FIFOCTL 0 at the same time automatically After enabling this mode the output SPI bus clock will be sent out in 6 peripheral clo...

Page 595: ...SPIx_FIFOCTL 29 28 setting TXTHIF SPIx_STATUS 18 will be set to 1 When the count of valid data stored in receive FIFO buffer is larger than RXTH SPIx_FIFOCTL 25 24 setting RXTHIF SPIx_STATUS 10 will be set to 1 Comparator Valid Data Count in Transmit FIFO Buffer TXTHIF 1 when A B TXTHIF 0 when A B TXTH Comparator Valid Data Count in Receive FIFO Buffer RXTH A B C D RXTHIF 1 when C D RXTHIF 0 when ...

Page 596: ...matically if the transmitted data are updated in time If the SPIx_TX register does not be updated after all data transfer are done the transfer will stop In Master mode during receiving operation the serial data are received from SPIx_MISO pin and stored to receive FIFO buffer The received data Data0 s b0 b1 b31 is stored into skew buffer first according the serial clock SPIx_CLK and then it is sh...

Page 597: ...evice receives clock signal from master Data can be written to SPIx_TX register as long as the TXFULL SPIx_STATUS 17 is 0 After all data have been drawn out by the SPI transmission logic unit and the SPIx_TX register is not updated by software the TXEMPTY SPIx_STATUS 16 will be set to 1 If there is no any data written to the SPIx_TX register the transmit underflow interrupt flag TXUFIF SPIx_STATUS...

Page 598: ...I Slave Selection Active Inactive Interrupt In Slave mode the slave selection active inactive interrupt flag SSACTIF SPIx_STATUS 2 and SSINAIF SPIx_STATUS 3 will be set to 1 when the SPIEN SPIx_CTL 0 and SLAVE SPIx_CTL 18 are set to 1 and the slave selection signal goes to active inactive state The SPI controller will issue an interrupt if the SSINAIEN SPIx_SSCTL 13 or SSACTIEN SPIx_SSCTL 12 are s...

Page 599: ...OCTL 29 28 the transmit FIFO interrupt flag TXTHIF SPIx_STATUS 18 will be set to 1 The SPI controller will generate a transmit FIFO interrupt to the system if the transmit FIFO interrupt enable bit TXTHIEN SPIx_FIFOCTL 3 is set to 1 Receive FIFO Interrupt In FIFO mode if the valid data count of the receive FIFO buffer is larger than the setting value of RXTH SPIx_FIFOCTL 25 24 the receive FIFO int...

Page 600: ...upports PCM mode A and PCM mode B The I2Sx_LRCLK signal in PCM mode indicates the beginning of an audio frame word N 1 right channel I2Sx_BCLK I2Sx_LRCLK I2Sx_DI I2Sx_DO MSB word N left channel word N 1 left channel LSB MSB LSB MSB word N right channel LSB Figure 6 16 19 PCM Mode A Timing Diagram word N 1 right channel I2Sx_BCLK I2Sx_LRCLK I2Sx_DI I2Sx_DO MSB word N left channel word N 1 left chan...

Page 601: ...data mode ORDER SPIx_I2SCTL 7 0 Mono 16 bit data mode Stereo 16 bit data mode ORDER SPIx_I2SCTL 7 0 N LEFT RIGHT N N 1 0 0 0 Mono 24 bit data mode Stereo 24 bit data mode 23 23 23 N LEFT RIGHT N N 1 0 31 31 31 0 0 Mono 32 bit data mode Stereo 32 bit data mode LEFT 1 RIGHT LEFT RIGHT 1 7 7 7 7 0 0 0 0 Stereo 8 bit data mode ORDER SPIx_I2SCTL 7 1 LEFT RIGHT 0 15 0 15 Stereo 16 bit data mode ORDER SP...

Page 602: ...Ix_CTL 2 1 Four SPI timing diagrams for master slave operations and the related settings are shown below SPIx_CLK SPIx_MISO SPIx_MOSI TX 6 TX 4 TX 3 TX 2 LSB TX 0 RX 6 RX 4 RX 2 LSB RX 0 MSB RX 7 RX 3 MSB TX 7 SPIx_SS CLKPOL 0 CLKPOL 1 TX 5 RX 5 TX 1 RX 1 SSACTPOL 0 SSACTPOL 1 Master Mode SLVAE 0 LSB 0 DWIDTH 0x08 1 CLKPOL 0 TXNEG 1 RXNEG 0 or 2 CLKPOL 1 TXNEG 0 RXNEG 1 Figure 6 16 22 SPI Timing i...

Page 603: ...e Mode SLVAE 1 LSB 0 DWIDTH 0x08 1 CLKPOL 0 TXNEG 1 RXNEG 0 or 2 CLKPOL 1 TXNEG 0 RXNEG 1 Figure 6 16 24 SPI Timing in Slave Mode SPIx_CLK SPIx_MOSI SPIx_MISO TX 1 TX 7 TX 0 TX 1 MSB TX 7 RX 1 RX 7 RX 1 MSB RX 7 LSB RX 0 RX 0 LSB TX 0 SPIx_SS CLKPOL 0 CLKPOL 1 SSACTPOL 0 SSACTPOL 1 Slave Mode SLVAE 1 LSB 1 DWIDTH 0x08 1 CLKPOL 0 TXNEG 0 RXNEG 1 or 2 CLKPOL 1 TXNEG 1 RXNEG 0 Figure 6 16 25 SPI Timi...

Page 604: ...r as master device by setting SLAVE SPIx_CTL 18 to 0 2 Force the SPI clock idle state at low by clearing CLKPOL SPIx_CTL 3 to 0 3 Select data transmitted on negative edge of SPI bus clock by setting TXNEG SPIx_CTL 2 to 1 4 Select data latched on positive edge of SPI bus clock by clearing RXNEG SPIx_CTL 1 to 0 5 Set the bit length of a transaction as 8 bit in DWIDTH bit field SPIx_CTL 12 8 0x08 6 S...

Page 605: ...positive edge of SPI bus clock by clearing RXNEG SPIx_CTL 1 to 0 5 Set the bit length of a transaction as 8 bit in DWIDTH bit field SPIx_CTL 12 8 0x08 6 Set LSB transfer first by setting LSB SPIx_CTL 13 to 1 3 Set the SPIEN SPIx_CTL 0 to 1 Wait for the slave select trigger input and SPI clock input from the off chip master device to start the data transfer 4 If this SPI slave attempts to transmit ...

Page 606: ...SCTL SPIx_BA 0x08 R W SPI Slave Select Control Register 0x0000_0000 SPIx_PDMACTL SPIx_BA 0x0C R W SPI PDMA Control Register 0x0000_0000 SPIx_FIFOCTL SPIx_BA 0x10 R W SPI FIFO Control Register 0x2200_0000 SPIx_STATUS SPIx_BA 0x14 R W SPI Status Register 0x0005_0110 SPIx_TX SPIx_BA 0x20 W SPI Data Transmit Register 0x0000_0000 SPIx_RX SPIx_BA 0x30 R SPI Data Receive Register 0x0000_0000 SPIx_I2SCTL ...

Page 607: ...Disabled 1 Byte Reorder function Enabled A byte suspend interval will be inserted among each byte The period of the byte suspend interval depends on the setting of SUSPITV Note Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits 18 SLAVE Slave Mode Control 0 Master mode 1 Slave mode 17 UNITIEN Unit Transfer Interrupt Enable Bit 0 SPI unit transfer interrupt Disabled 1...

Page 608: ...lowing transaction word The default value is 0x3 The period of the suspend interval is obtained according to the following equation SUSPITV 3 0 0 5 period of SPICLK clock cycle Example SUSPITV 0x0 0 5 SPICLK clock cycle SUSPITV 0x1 1 5 SPICLK clock cycle SUSPITV 0xE 14 5 SPICLK clock cycle SUSPITV 0xF 15 5 SPICLK clock cycle 3 CLKPOL Clock Polarity 0 SPI bus clock is idle low 1 SPI bus clock is id...

Page 609: ...ription 31 8 Reserved Reserved 7 0 DIVIDER Clock Divider The value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master The frequency is obtained according to the following equation 1 _ _ _ DIVIDER f f src clock spi eclk spi where f src clock spi _ _ is the peripheral clock source which is defined in the clock control register CLK...

Page 610: ... Bit 0 Slave select active interrupt Disabled 1 Slave select active interrupt Enabled 11 10 Reserved Reserved 9 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 0 Slave mode TX under run interrupt Disabled 1 Slave mode TX under run interrupt Enabled 8 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 0 Slave mode bit count error interrupt Disabled 1 Slave mode bit count error interrupt...

Page 611: ...e SPIx_SS line to inactive state 1 set the SPIx_SS line to active state If the AUTOSS bit is set to 1 0 Keep the SPIx_SS line at inactive state 1 SPIx_SS line will be automatically driven to active state for the duration of data transfer and will be driven to inactive state for the rest of the time The active state of SPIx_SS is specified in SSACTPOL SPIx_SSCTL 2 ...

Page 612: ...tion 31 3 Reserved Reserved 2 PDMARST PDMA Reset 0 No effect 1 Reset the PDMA control logic of the SPI controller This bit will be automatically cleared to 0 1 RXPDMAEN Receive PDMA Enable Bit 0 Receive PDMA function Disabled 1 Receive PDMA function Enabled 0 TXPDMAEN Transmit PDMA Enable Bit 0 Transmit PDMA function Disabled 1 Transmit PDMA function Enabled Note In SPI Master mode with full duple...

Page 613: ...s larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0 23 10 Reserved Reserved 9 TXFBCLR Transmit FIFO Buffer Clear 0 No effect 1 Clear transmit FIFO pointer The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 Note The TX shift register will not ...

Page 614: ...interrupt Disabled 1 TX FIFO threshold interrupt Enabled 2 RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 0 RX FIFO threshold interrupt Disabled 1 RX FIFO threshold interrupt Enabled 1 TXRST Transmit Reset 0 No effect 1 Reset transmit FIFO pointer and transmit circuit The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 This bit will be cleared to 0 by hardware about 3 sys...

Page 615: ...T or RXRST Note Both the reset operations of TXRST and RXRST need 3 system clock cycles 2 peripheral clock cycles User can check the status of this bit to monitor the reset function is doing or done 22 20 Reserved Reserved 19 TXUFIF TX Underflow Interrupt Flag When the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL 0 No effect 1 N...

Page 616: ...FO is overrun Note This bit will be cleared by writing 1 to it 10 RXTHIF Receive FIFO Threshold Interrupt Flag Read Only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH 9 RXFULL Receive FIFO Buffer Full Indicator Read Only 0 Receive FIFO buffer ...

Page 617: ...select active interrupt event occurred Note Only available in Slave mode This bit will be cleared by writing 1 to it 1 UNITIF Unit Transfer Interrupt Flag 0 No transaction has been finished since this bit was cleared to 0 1 SPI controller has finished one unit transfer Note This bit will be cleared by writing 1 to it 0 BUSY Busy Status Read Only 0 SPI controller is in idle state 1 SPI controller i...

Page 618: ...of valid bits depends on the setting of DWIDTH SPIx_CTL 12 8 in SPI mode or WDWIDTH SPIx_I2SCTL 5 4 in I2 S mode In SPI mode if DWIDTH is set to 0x08 the bits TX 7 0 will be transmitted If DWIDTH is set to 0x00 the SPI controller will perform a 32 bit transfer In I2 S mode if WDWIDTH SPIx_I2SCTL 5 4 is set to 0x2 the data width of audio channel is 24 bit and corresponding to TX 23 0 If WDWIDTH is ...

Page 619: ... 28 27 26 25 24 RX 23 22 21 20 19 18 17 16 RX 15 14 13 12 11 10 9 8 RX 7 6 5 4 3 2 1 0 RX Bits Description 31 0 RX Data Receive Register There are 4 level FIFO buffers in this controller The data receive register holds the data received from SPI data input pin If the RXEMPTY SPIx_STATUS 8 or SPIx_I2SSTS 8 is not set to 1 the receive FIFO buffers can be accessed through software by reading this reg...

Page 620: ...it is set to 1 and left channel zero cross event occurs 0 Interrupt Disabled 1 Interrupt Enabled 24 RZCIEN Right Channel Zero Cross Interrupt Enable Bit Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs 0 Interrupt Disabled 1 Interrupt Enabled 23 RXLCH Receive Left Channel Enable Bit When monaural format is selected MONO 1 I2 S controller will receive right channel...

Page 621: ... chip In Slave mode I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip 0 Master mode 1 Slave mode 7 ORDER Stereo Data Order in FIFO 0 Left channel data at high byte 1 Left channel data at low byte 6 MONO Monaural Data 0 Data is stereo format 1 Data is monaural format 5 4 WDWIDTH Word Width 00 data size is 8 bit 01 data size is...

Page 622: ...ock s i _ _ 2 is the frequency of I2 S peripheral clock source which is defined in the clock control register CLK_CLKSEL2 In I2 S Slave mode this field is used to define the frequency of peripheral clock and it s determined by 1 2 BCLKDIV _ _ 2 f src clock s i The peripheral clock frequency in I2 S Slave mode must be equal to or faster than 6 times of input bit clock 7 6 Reserved Reserved 5 0 MCLK...

Page 623: ...6 Aug 08 2018 Page 623 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL Note User should set BCLKDIV carefully because the peripheral clock frequency must be slower than or equal to system frequency ...

Page 624: ...tion of TXRST or RXRST is done 1 Doing the reset function of TXRST or RXRST Note Both the reset operations of TXRST and RXRST need 3 system clock cycles 2 peripheral clock cycles User can check the status of this bit to monitor the reset function is doing or done 22 Reserved Reserved 21 LZCIF Left Channel Zero Cross Interrupt Flag 0 No zero cross event occurred on left channel 1 Zero cross event o...

Page 625: ...de or over 576 SPI peripheral clock period in Slave mode When the received FIFO buffer is read by software the time out status will be cleared automatically Note This bit will be cleared by writing 1 to it 11 RXOVIF Receive FIFO Overrun Interrupt Flag When the receive FIFO buffer is full the follow up data will be dropped and this bit will be set to 1 Note This bit will be cleared by writing 1 to ...

Page 626: ...h CNT TIMERx_CNT 23 0 Supports event counting function 24 bit capture value is readable through CAPDAT TIMERx_CAP 23 0 Supports external capture pin event for interval measurement Supports external capture pin event to reset 24 bit up counter Supports chip wake up from Idle Power down mode if a timer interrupt signal is generated Support Timer0 Timer3 time out interrupt signal or capture interrupt...

Page 627: ...e state until brake interrupt cleared Level detect brake source to auto recover function after brake condition removed Supports interrupt on the following events PWM zero point period point up count compared or down count compared point events Brake condition happened Supports trigger ADC on the following events PWM zero point period zero or period point up count compared or down count compared po...

Page 628: ... CAPIEN TIMERx_EXTCTL 5 INTEN TIMERx_CTL 29 24 bit CAPDAT TIMERx_CAP 23 0 24 bit CNT TIMERx_CNT 23 0 CAPIF TIMERx_ EINTSTS 0 CAPFUNCS TIMERx_EXTCTL 4 Timer Wakeup CAPSRC TIMERx_CTL 22 T0_EXT T3_EXT 00 01 10 CAPEDGE TIMERx_EXTCTL 2 1 ACMP0_O ACMP1_O 1 0 0 1 0 1 0 1 0 1 ACMPSSEL TIMERx_EXTCTL 8 Figure 6 17 1 Timer Controller Block Diagram Set FUNMODE TIMERx_ALTCTL 0 0 to enable timer mode The clock ...

Page 629: ...Hz LXT T0 T1 TMR0CKEN CLK_APBCLK0 2 TMR1CKEN CLK_APBCLK0 3 TMR0_CLK TMR1_CLK TMR0SEL CLK_CLKSEL1 10 8 TMR1SEL CLK_CLKSEL1 14 12 111 010 001 000 011 101 111 010 001 PCLK1 000 011 101 Legend HIRC High Speed Internal clock signal 22 1184 MHz HIRC 10 kHz LIRC 4 24 MHz HXT 32 768 kHz LXT T2 T3 TMR2CKEN CLK_APBCLK0 4 TMR3CKEN CLK_APBCLK0 5 TMR2SEL CLK_CLKSEL1 18 16 TMR3SEL CLK_CLKSEL1 22 20 TMR2_CLK TMR...

Page 630: ... PWM mode The clock source of Timer0 Timer3 in PWM mode can be enabled in TMRxCKEN CLK_APBCLK0 5 2 TMR0_CLK and TMR1_CLK clock sources are fixed to PCLK0 TMR2_CLK and TMR3_CLK clock sources are fixed to PCLK1 PWM system clock frequency will be PCLKx frequency as Figure 6 17 4 The clock source of PWM counter TIMERx_PWMCLK can be selected from PWM system clock TMRx_CLK or Timer interrupt events TMRx...

Page 631: ...assed to corresponding generators to generate PWM pulse Pulse Generator interrupt signal Interrupt Generator and trigger signal Trigger Generator for ADC to start conversion Output Control block is used to decide PWM pulse output brake function in Output Control block also generates interrupt events And Dead Time Control is available only in PWM complementary mode Prescale Pulse Generator Output C...

Page 632: ...requency in TMR0SEL CLK_CLKSEL1 10 8 for Timer0 TMR1SEL CLK_CLKSEL1 14 12 for Timer1 TMR2SEL CLK_CLKSEL1 18 16 for Timer2 and TMR3SEL CLK_CLKSEL1 22 20 for Timer3 Set FUNMODE TIMERx_ALTCTL 0 1 to enable PWM mode The clock source of Timer0 Timer3 in PWM mode can be enabled in TMRxCKEN CLK_APBCLK0 5 2 TMR0_CLK and TMR1_CLK clock sources are fixed to PCLK0 TMR2_CLK and TMR3_CLK clock sources are fixe...

Page 633: ...controller in TMR2RST SYS_IPRST1 4 and TMR3RST SYS_IPRST1 5 Pin Configuration Group Pin Name GPIO MFP TM2 TM2 PD 3 MFP1 PB 0 PD 10 MFP4 PA 14 PD 8 MFP6 PA 9 MFP8 TM2_EXT PA 5 MFP3 PE 0 MFP4 PE 12 MFP8 PB 2 MFP10 TM3 TM3 PB 1 PD 11 MFP4 PA 15 PD 9 MFP6 TM3_EXT PA 4 PE 1 PF 5 MFP3 PE 13 MFP8 6 17 5 Timer Functional Description 6 17 5 1 Timer Interrupt Flag The timer controller supports two interrupt...

Page 634: ...oggle Output Mode If the timer controller is configured at toggle output mode TIMERx_CTL 28 27 is 10 and CNTEN TIMERx_CTL 30 is set the timer counter starts up counting The counting operation of toggle output mode is almost the same as periodic mode except toggle output mode has associated T0 T3 pin to output signal while specify TIF TIMERx_INTSTS 0 is set Thus the toggle output signal on T0 T3 pi...

Page 635: ...NTPHASE TIMERx_EXTCTL 0 bit In event counting mode the timer counting operation mode can be selected as one shot periodic and continuous counting mode to counts the counter value CNT TIMERx_CNT 23 0 for Tx pin 6 17 5 8 External Capture Mode The event capture function is used to load CNT TIMERx_CNT 23 0 value to CAPDAT TIMERx_CAP 23 0 value while edge transition detected on Tx_EXT x 0 3 pin In this...

Page 636: ...7 10 External Reset Counter Mode 6 17 5 10Timer Trigger Function The timer controller provides timer time out interrupt or capture interrupt internal trigger event to generate PWM counter counting once start ADC convert and trigger PDMA transfer If TRGSSEL TIMERx_TRGCTL 0 is 0 time out interrupt signal is used to trigger PWM ADC and PDMA If TRGSSEL TIMERx_TRGCTL 0 is 1 capture interrupt signal is ...

Page 637: ...Timer0 Inter timer Trigger Capture enabled trigger counting capture function is forced on Timer1 Setting Timer2 Inter Timer Trigger enabled trigger counting capture function is forced on Timer3 Start Trigger While INTRGEN TIMERx_CTL 19 in Timer0 2 is set the Timer0 2 will make a rising edge transition of INTR_TMR_TRG while Timer0 2 24 bit counter value CNT is counting from 0x0 to 0x1 and Timer1 3 ...

Page 638: ...1 output User can set ACMPSSEL TIMERx_EXTCTL 9 8 to decide which ACMP output signal as Timerx x 0 3 capture source The detail setting of capture function is the same as previous descriptions in External Capture Mode 6 17 6 PWM Functional Description 6 17 6 1 PWM Prescale The PWM prescale is used to divide clock source and the clock of PWM counter is divided by CLKPSC 1 The prescale is set by CLKPS...

Page 639: ... 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 PWM Period PWM Period PERIOD 5 PERIOD 8 PWM Period PERIOD 8 zero point event period point event CNT TIMERx_PWMCNT 15 0 CNTEN TIMERx_PWMCTL 0 Figure 6 17 14 PWM Up Count Type 6 17 6 4 Down Count Type When the PWM counter is set to down count type CNTTYPE TIMERx_PWMCTL 2 1 is 0x1 it starts down counting from PERIOD to zero current counter value can be read from CNT...

Page 640: ...ot mode and auto reload mode PWM counter will operate in one shot mode if CNTMODE TIMERx_PWMCTL 3 bit is set to 1 and operate in auto reload mode if CNTMODE bit is set to 0 In both modes CMP TIMERx_PWMCMPDAT 15 0 and PERIOD TIMERx_PWMPERIOD 15 0 should be written first and then set CNTEN TIMERx_PWMCTL 0 bit to 1 to start counter running In one shot mode PWM counter value will reload to default val...

Page 641: ...MERx_PWMCMPBUF 15 0 is the active CMP buffer register In period loading mode both PERIOD TIMERx_PWMPERIOD 15 0 and CMP TIMERx_PWMCMPDAT 15 0 will load to their active PBUF and CMPBU register while each PWM period is completed Figure 6 17 18 shows period loading timing of up count type where PERIOD DATA0 denotes the initial data of PERIOD PERIOD DATA1 denotes the first updated PERIOD data by user a...

Page 642: ...MPDAT 15 0 PERIOD or CMP will be load to active PBUF TIMERx_PWMPBUF 15 0 or CMPBUF TIMERx_PWMCMPBUF 15 0 after current counter count is completed If the update PERIOD value is less than current counter value counter will count wraparound The following steps are the sequence of Figure 6 17 19 1 User writes CMP DATA1 at point 1 and hardware will load CMP DATA1 to CMPBUF after current counter count i...

Page 643: ... pulse The events are zero point and period point in up count type and down count type center point in up down count type and counter equal to comparator point in three count types Each event point can generate PWM output waveform in differente count type as shown in Figure 6 17 20 CNT PWM period Zero CMPDAT Center PWM OUT CNT Figure 6 17 20 PWM Pulse Generation in Up Down Count Type The PWM gener...

Page 644: ...2 3 4 3 2 1 0 PWM period PWM period 0 1 2 3 4 0 1 2 3 4 CMPU L Zero H PWM period PWM period CMPU L CMPD H CMPDAT 0 0 Duty CMPDAT 1 25 Duty CMPDAT 2 50 Duty CMPDAT 3 75 Duty CMPDAT 4 100 Duty CMPDAT 0 0 Duty CMPDAT 1 20 Duty CMPDAT 2 40 Duty CMPDAT 3 60 Duty CMPDAT 4 80 Duty CMPDAT 4 100 Duty Figure 6 17 21 PWM 0 to 100 Duty Cycle in Up Count Type and Up Down Count Type Priority Zero And CMPU Point...

Page 645: ...n Figure 6 17 23 PWMx_CH1 PWMx_CH0 Figure 6 17 23 PWM Complementary Mode Output Waveform 6 17 6 14PWM Output Control After PWM pulse generator there are four steps to control output waveform in independent output mode and five control steps in complementary output mode User can set POEN0 TIMERx_PWMPOEN 0 and POEN1 TIMERx_PWMPOEN 1 1 to enable PWMx_CH0 and PWMx_CH1 output waveform In Independent mo...

Page 646: ...own in Figure 6 17 26 User sets DTEN TIMERx_PWMDTCTL 16 bit to enable dead time control function DTCNT TIMERx_PWMDTCTL 11 0 and DTCKSEL TIMERx_PWMDTCTL 24 to control dead time interval The dead time interval can be calculated from the following formula Dead time interval DTCNT 1 TMRx_PWMCLK period if DTCKSEL is 0 Dead time interval DTCNT 1 TMRx_PWMCLK CLKPSC 1 period if DTCKSEL is 1 PWMx_CH0 PWMx_...

Page 647: ...er will recognize the effective edge of the brake pin signal In addition brake pin polar can be inversed by setting BRKPINV TIMERx_PWMBNF 7 to realize the polarity setup for the brake control signals Set BRKPINV to 0 brake event will occurred when TM_BRAKEx x 0 3 pin status from low to high set BRKPINV to 1 brake event will occurred when TM_BRAKEx x 0 3 pin status from high to low Filter counter 3...

Page 648: ...rupt status BRKEIF1 0 can be cleared by writing 1 to it and the brake event status BRKESTS1 0 will keep until the next PWM period starts when corresponding BRKEIF1 0 flag has been cleared and PWM generator can resume normal output Figure 6 17 30 shows an example of edge detector brake waveform for PWMx_CH0 and PWMx_CH1 In this case the edge detect brake source has occurred twice for the brake even...

Page 649: ... brake function generates interrupt status for PWMx_CH1 0 is BRKLIF1 0 TIMERx_PWMINTSTS1 9 8 and brake event status for PWMx_CH1 0 is BRKLSTS1 0 TIMERx_PWMINTSTS1 25 24 The interrupt status BRKLIF1 0 can be cleared by writing 1 to it and the brake event status BRKLSTS1 0 will be cleared only when current period is completed and brake condition removed then PWM generator can resume normal output wh...

Page 650: ... 15 0 Level Detect Brake Source PWMx_CH0 BRKLIF1 TIMERx_PWMINTSTS1 1 BRKLIF0 TIMERx_PWMINTSTS1 0 BRKLSTS0 TIMERx_PWMINTSTS1 16 BRKLSTS1 TIMERx_PWMINTSTS1 17 PWMx_CH1 Figure 6 17 31 Level Detector Brake Waveform for PWMx_CH0 and PWMx_CH1 The two kinds of detectors detect the same five brake sources as shown in Figure 6 17 32 one from TM_BRAKEx x 0 3 external input signals two from internal ACMP com...

Page 651: ...ce ACMP0_O ACMP1_O CPO1EBEN TIMERx_PWMBRKCTL 1 Figure 6 17 32 Brake Source Block Diagram Among the above described brake sources the brake source coming from system fail event can be specified to one of the different system fail conditions these conditions include clock fail BOD detect and CPU lockup as shown in Figure 6 17 33 Brake Source CSSBRKEN TIMERx_PWMFAILBRK 0 Clock Fail BODBRKEN TIMERx_PW...

Page 652: ...PWM as shown in Figure 6 17 35 The PWM interrupt PWMx_INT comes from PWM complementary pair events The counter can generate the zero point interrupt flag ZIF TIMERx_PWMINTSTS0 0 and the period point interrupt flag PIF TIMERx_PWMINTSTS0 1 When counter equals to the comparator value stored in CMP TIMERx_PWMCMPDAT 15 0 the different interrupt flags will be triggered depending on the counting directio...

Page 653: ... 35 PWM Interrupt Architecture Diagram 6 17 6 20 PWM Trigger ADC Generator The PWM counter event can be one of the ADC conversion trigger source User sets TRGSEL TIMERx_PWMADCTS 3 0 to select which PWM counter event can trigger ADC conversion after TRGEN TIMERx_PWMADCTS 7 is enabled There are five PWM counter events can be selected as the trigger source to start ADC conversion which shown in Figur...

Page 654: ..._BA 0x20 R W Timer0 Alternative Control Register 0x0000_0000 TIMER0_PWM CTL TMR01_BA 0x40 R W Timer0 PWM Control Register 0x0000_0000 TIMER0_PWM CLKSRC TMR01_BA 0x44 R W Timer0 PWM Counter Clock Source Register 0x0000_0000 TIMER0_PWM CLKPSC TMR01_BA 0x48 R W Timer0 PWM Counter Clock Pre scale Register 0x0000_0000 TIMER0_PWM CNTCLR TMR01_BA 0x4C R W Timer0 PWM Clear Counter Register 0x0000_0000 TIM...

Page 655: ...0000_0000 TIMER0_PWM STRG TMR01_BA 0x98 W Timer0 PWM Synchronous Trigger Register 0x0000_0000 TIMER0_PWM STATUS TMR01_BA 0x9C R W Timer0 PWM Status Register 0x0000_0000 TIMER0_PWM PBUF TMR01_BA 0xA0 R Timer0 PWM Period Buffer Register 0x0000_0000 TIMER0_PWM CMPBUF TMR01_BA 0xA4 R Timer0 PWM Comparator Buffer Register 0x0000_0000 TIMER1_CTL TMR01_BA 0x100 R W Timer1 Control Register 0x0000_0005 TIM...

Page 656: ...00 TIMER1_PWM BRKCTL TMR01_BA 0x170 R W Timer1 PWM Brake Control Register 0x0000_0000 TIMER1_PWM POLCTL TMR01_BA 0x174 R W Timer1 PWM Pin Output Polar Control Register 0x0000_0000 TIMER1_PWM POEN TMR01_BA 0x178 R W Timer1 PWM Pin Output Enable Register 0x0000_0000 TIMER1_PWM SWBRK TMR01_BA 0x17C W Timer1 PWM Software Trigger Brake Control Register 0x0000_0000 TIMER1_PWM INTEN0 TMR01_BA 0x180 R W T...

Page 657: ...mer2 PWM Counter Clock Source Register 0x0000_0000 TIMER2_PWM CLKPSC TMR23_BA 0x48 R W Timer2 PWM Counter Clock Pre scale Register 0x0000_0000 TIMER2_PWM CNTCLR TMR23_BA 0x4C R W Timer2 PWM Clear Counter Register 0x0000_0000 TIMER2_PWM PERIOD TMR23_BA 0x50 R W Timer2 PWM Period Register 0x0000_0000 TIMER2_PWM CMPDAT TMR23_BA 0x54 R W Timer2 PWM Comparator Register 0x0000_0000 TIMER2_PWM DTCTL TMR2...

Page 658: ...Buffer Register 0x0000_0000 TIMER2_PWM CMPBUF TMR23_BA 0xA4 R Timer2 PWM Comparator Buffer Register 0x0000_0000 TIMER3_CTL TMR23_BA 0x100 R W Timer3 Control Register 0x0000_0005 TIMER3_CMP TMR23_BA 0x104 R W Timer3 Comparator Register 0x0000_0000 TIMER3_INTS TS TMR23_BA 0x108 R W Timer3 Interrupt Status Register 0x0000_0000 TIMER3_CNT TMR23_BA 0x10C R W Timer3 Data Register 0x0000_0000 TIMER3_CAP ...

Page 659: ...ar Control Register 0x0000_0000 TIMER3_PWM POEN TMR23_BA 0x178 R W Timer3 PWM Pin Output Enable Register 0x0000_0000 TIMER3_PWM SWBRK TMR23_BA 0x17C W Timer3 PWM Software Trigger Brake Control Register 0x0000_0000 TIMER3_PWM INTEN0 TMR23_BA 0x180 R W Timer3 PWM Interrupt Enable Register 0 0x0000_0000 TIMER3_PWM INTEN1 TMR23_BA 0x184 R W Timer3 PWM Interrupt Enable Register 1 0x0000_0000 TIMER3_PWM...

Page 660: ...isabled TIMER counter will keep going no matter CPU is held by ICE or not Note This bit is write protected Refer to the SYS_REGLCTL register 30 CNTEN Timer Counting Enable Bit 0 Stop Suspend counting 1 Start counting Note1 In stop status and then set CNTEN to 1 will enable the 24 bit up counter to keep counting from the last stop counting value Note2 This bit is auto cleared by hardware in one sho...

Page 661: ...ACMP output signal User can set ACMPSSEL TIMERx_EXTCTL 8 to decide which internal ACMP output signal as timer capture source 21 TGLPINSEL Toggle output Pin Select 0 Toggle mode output to Tx Timer Event Counter Pin 1 Toggle mode output to Tx_EXT Timer External Capture Pin 20 PERIOSEL Periodic Mode Behavior Selection Enable Bit 0 The behavior selection in periodic mode Disabled When user updates CMP...

Page 662: ...ANUAL 7 0 PSC Prescale Counter Timer input clock or event source is divided by PSC 1 before it is fed to the timer up counter If this field is 0 PSC 0 then there is no scaling Note Update prescale counter value will reset internal 8 bit prescale counter and 24 bit up counter value ...

Page 663: ...ts Description 31 24 Reserved Reserved 23 0 CMPDAT Timer Comparator Value CMPDAT is a 24 bit compared value register When the internal 24 bit up counter value is equal to CMPDAT value the TIF TIMERx_INTSTS 0 Timer Interrupt Flag will set to 1 Time out period Period of timer clock input 8 bit PSC 1 24 bit CMPDAT Note1 Never write 0x0 or 0x1 in CMPDAT field or the core will run into unknown state No...

Page 664: ... 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TWKF TIF Bits Description 31 2 Reserved Reserved 1 TWKF Timer Wake up Flag This bit indicates the interrupt wake up flag status of timer 0 Timer does not cause CPU wake up 1 CPU wake up from Idle or Power down mode if timer time out interrupt signal generated Note This bit is cle...

Page 665: ...ve When user writes this CNT register timer starts to reset its internal 24 bit timer up counter to 0 and reload 8 bit pre scale counter At the same time timer set this flag to 1 to indicate the counter reset operation is in progress Once the counter reset operation done timer clear this bit to 0 automatically 0 Reset operation is done 1 Reset operation triggered by writing TIMERx_CNT is in progre...

Page 666: ...x0000_0000 TIMER3_CAP TMR23_BA 0x110 R Timer3 Capture Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CAPDAT 15 14 13 12 11 10 9 8 CAPDAT 7 6 5 4 3 2 1 0 CAPDAT Bits Description 31 24 Reserved Reserved 23 0 CAPDAT Timer Capture Data Register When CAPEN TIMERx_EXTCTL 3 bit is set CAPFUNCS TIMERx_EXTCTL 4 bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE ...

Page 667: ...is from Tx x 0 3 pin 1 Event Counter input source is from USB internal SOF output signal 15 Reserved Reserved 14 12 CAPEDGE Timer External Capture Pin Edge Detect When first capture event is generated the CNT TIMERx_CNT 23 0 will be reset to 0 and first CAPDAT TIMERx_CAP 23 0 should be to 0 000 Capture event occurred when detect falling edge transfer on Tx_EXT x 0 3 pin 001 Capture event occurred ...

Page 668: ...ection Interrupt Enabled Note CAPIEN is used to enable timer external interrupt If CAPIEN enabled timer will rise an interrupt when CAPIF TIMERx_EINTSTS 0 is 1 For example while CAPIEN 1 CAPEN 1 and CAPEDGE 00 a 1 to 0 transition on the Tx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU 4 CAPFUNCS Capture Function Selection 0 External Ca...

Page 669: ...23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CAPIF Bits Description 31 1 Reserved Reserved 0 CAPIF Timer External Capture Interrupt Flag This bit indicates the timer external capture interrupt flag status 0 Tx_EXT x 0 3 pin interrupt did not occur 1 Tx_EXT x 0 3 pin interrupt occurred Note1 This bit is cleared by writing 1 to it Note2 When CAPEN TIMERx_E...

Page 670: ...PDMA Trigger PDMA Enable Bit If this bit is set to 1 each timer time out event or capture event can be triggered PDMA transfer 0 Timer interrupt trigger PDMA Disabled 1 Timer interrupt trigger PDMA Enabled Note If TRGSSEL TIMERx_TRGCTL 0 0 time out interrupt signal will trigger PDMA transfer If TRGSSEL TIMERx_TRGCTL 0 1 capture interrupt signal will trigger PDMA transfer 3 Reserved Reserved 2 TRGA...

Page 671: ...errupt signal as PWM counter clock source If TRGSSEL TIMERx_TRGCTL 0 1 capture interrupt signal as PWM counter clock source 0 TRGSSEL Trigger Source Select Bit This bit is used to select internal trigger source is form timer time out interrupt signal or capture interrupt signal 0 Time out interrupt signal is used to internal trigger PWM PDMA and ADC 1 Capture interrupt signal is used to internal t...

Page 672: ..._ALT CTL TMR23_BA 0x20 R W Timer2 Alternative Control Register 0x0000_0000 TIMER3_ALT CTL TMR23_BA 0x120 R W Timer3 Alternative Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved FUNCSEL Bits Description 31 1 Reserved Reserved 0 FUNCSEL Function Selection 0 Timer controller is used as timer function...

Page 673: ...Protect 0 ICE debug mode acknowledgement effects PWM output PWM output pin will be forced as tri state while ICE debug mode acknowledged 1 ICE debug mode acknowledgement Disabled PWM output pin will keep output no matter ICE debug mode acknowledged or not Note This register is write protected Refer to SYS_REGLCTL register 30 DBGHALT ICE Debug Mode Counter Halt Write Protect If debug mode counter h...

Page 674: ...e PERIOD CMP Note If IMMLDEN is enabled CTRLD will be invalid 8 CTRLD Center Re load In up down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period 7 4 Reserved Reserved 3 CNTMODE PWM Counter Mode 0 Auto reload mode 1 One shot mode 2 1 CNTTYPE PWM Counter Behavior Type 00 Up count type 01 Down count type ...

Page 675: ...e Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CLKSRC Bits Description 31 3 Reserved Reserved 2 0 CLKSRC PWM Counter Clock Source Select The PWM counter clock source can be selected from TMRx_CLK or internal timer time out or capture event 000 TMRx_CLK 001 Internal TIMER0 time out or capture event 010...

Page 676: ...x0000_0000 TIMER2_PWM CLKPSC TMR23_BA 0x48 R W Timer2 PWM Counter Clock Pre scale Register 0x0000_0000 TIMER3_PWM CLKPSC TMR23_BA 0x148 R W Timer3 PWM Counter Clock Pre scale Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved CLKPSC 7 6 5 4 3 2 1 0 CLKPSC Bits Description 31 12 Reserved Reserved 11 0 CLKPSC PWM Counter Clock Pre sc...

Page 677: ... TIMER2_PWM CNTCLR TMR23_BA 0x4C R W Timer2 PWM Clear Counter Register 0x0000_0000 TIMER3_PWM CNTCLR TMR23_BA 0x14C R W Timer3 PWM Clear Counter Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNTCLR Bits Description 31 1 Reserved Reserved 0 CNTCLR Clear PWM Counter Control Bit It is automatically cleare...

Page 678: ...4 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PERIOD 7 6 5 4 3 2 1 0 PERIOD Bits Description 31 16 Reserved Reserved 15 0 PERIOD PWM Period Register In up count type PWM counter counts from 0 to PERIOD and restarts from 0 In down count type PWM counter counts from PERIOD to 0 and restarts from PERIOD In up down count type PWM counter counts from 0 to PERIOD then decrements to 0...

Page 679: ...WM Comparator Register 0x0000_0000 TIMER2_PWM CMPDAT TMR23_BA 0x54 R W Timer2 PWM Comparator Register 0x0000_0000 TIMER3_PWM CMPDAT TMR23_BA 0x154 R W Timer3 PWM Comparator Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CMP 7 6 5 4 3 2 1 0 CMP Bits Description 31 16 Reserved Reserved 15 0 CMP PWM Comparator Register PWM CMP is used to c...

Page 680: ...me clock source from TMRx_PWMCLK without counter clock prescale 1 Dead time clock source from TMRx_PWMCLK with counter clock prescale Note This register is write protected Refer to SYS_REGLCTL register 23 17 Reserved Reserved 16 DTEN Enable Dead time Insertion for PWMx_CH0 and PWMx_CH1 Write Protect Dead time insertion function is only active when PWM complementary mode is enabled If dead time ins...

Page 681: ...3_BA 0x5C R Timer2 PWM Counter Register 0x0000_0000 TIMER3_PWM CNT TMR23_BA 0x15C R Timer3 PWM Counter Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved DIRF 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 17 Reserved Reserved 16 DIRF PWM Counter Direction Indicator Flag Read Only 0 Counter is active in down counting 1 Counter is active in up ...

Page 682: ...gister 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved MSKEN1 MSKEN0 Bits Description 31 2 Reserved Reserved 1 MSKEN1 PWMx_CH1 Output Mask Enable Bit The PWMx_CH1 output signal will be masked when this bit is enabled The PWMx_CH1 will output MSKDAT1 TIMER_PWMMSK 1 data 0 PWMx_CH1 output signal is non masked 1 PWM...

Page 683: ... W Timer3 PWM Output Mask Data Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved MSKDAT1 MSKDAT0 Bits Description 31 2 Reserved Reserved 1 MSKDAT1 PWMx_CH1 Output Mask Data Control Bit This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled MSKEN1 ...

Page 684: ...d 17 16 BKPINSRC Brake Pin Source Select 00 Brake pin source comes from TM_BRAKE0 01 Brake pin source comes from TM_BRAKE1 10 Brake pin source comes from TM_BRAKE2 11 Brake pin source comes from TM_BRAKE3 15 8 Reserved Reserved 7 BRKPINV Brake Pin Detection Control Bit 0 Brake pin event will be detected if TM_BRAKEx pin status transfer from low to high in edge detect or pin status is high in level...

Page 685: ...CAL REFERENCE MANUAL 101 Noise filter clock is PCLKx 32 110 Noise filter clock is PCLKx 64 111 Noise filter clock is PCLKx 128 0 BRKNFEN Brake Pin Noise Filter Enable Bit 0 Pin noise filter detect of TM_BRAKEx Disabled 1 Pin noise filter detect of TM_BRAKEx Enabled ...

Page 686: ...000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CORBRKEN Reserved BODBRKEN CSSBRKEN Bits Description 31 4 Reserved Reserved 3 CORBRKEN Core Lockup Detection Trigger PWM Brake Function Enable Bit 0 Brake Function triggered by core lockup event Disabled 1 Brake Function triggered by core lockup event Enabled 2 Reserved Res...

Page 687: ...H1 output 01 PWMx_CH1 output tri state when TIMERx_PWM brake event happened 10 PWMx_CH1 output low level when TIMERx_PWM brake event happened 11 PWMx_CH1 output high level when TIMERx_PWM brake event happened Note This register is write protected Refer to SYS_REGLCTL register 17 16 BRKAEVEN PWM Brake Action Select for PWMx_CH0 Write Protect 00 TIMERx_PWM brake event will not affect PWMx_CH0 output...

Page 688: ...ite Protect 0 System fail condition as edge detect brake source Disabled 1 System fail condition as edge detect brake source Enabled Note This register is write protected Refer to SYS_REGLCTL register 6 5 Reserved Reserved 4 BRKPEEN Enable TM_BRAKEx Pin As Edge detect Brake Source Write Protect 0 TM_BRAKEx pin event as edge detect brake source Disabled 1 TM_BRAKEx pin event as edge detect brake so...

Page 689: ...0 TIMER3_PWM POLCTL TMR23_BA 0x174 R W Timer3 PWM Pin Output Polar Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PINV1 PINV0 Bits Description 31 2 Reserved Reserved 1 PINV1 PWMx_CH1 Output Pin Polar Control Bit The bit is used to control polarity state of PWMx_CH1 output pin 0 PWMx_CH1 output p...

Page 690: ...00 TIMER2_PWM POEN TMR23_BA 0x78 R W Timer2 PWM Pin Output Enable Register 0x0000_0000 TIMER3_PWM POEN TMR23_BA 0x178 R W Timer3 PWM Pin Output Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved POEN1 POEN0 Bits Description 31 2 Reserved Reserved 1 POEN1 PWMx_CH1 Output Pin Enable Bit 0 PWMx_CH1 pin ...

Page 691: ... 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved BRKLTRG 7 6 5 4 3 2 1 0 Reserved BRKETRG Bits Description 31 9 Reserved Reserved 8 BRKLTRG Software Trigger Level detect Brake Source Write Only Write Protect Write 1 to this bit will trigger PWM level detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 regist...

Page 692: ...9 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CMPDIEN CMPUIEN PIEN ZIEN Bits Description 31 4 Reserved Reserved 3 CMPDIEN PWM Compare Down Count Interrupt Enable Bit 0 Compare down count interrupt Disabled 1 Compare down count interrupt Enabled 2 CMPUIEN PWM Compare Up Count Interrupt Enable Bit 0 Compare up count interrupt Disab...

Page 693: ... Timer3 PWM Interrupt Enable Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved BRKLIEN 7 6 5 4 3 2 1 0 Reserved BRKEIEN Bits Description 31 9 Reserved Reserved 8 BRKLIEN PWM Level detect Brake Interrupt Enable Bit Write Protect 0 PWM level detect brake interrupt Disabled 1 PWM level detect brake interrupt Enabled Note This bit i...

Page 694: ...rved 3 CMPDIF PWM Compare Down Count Interrupt Flag This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP Note1 If CMP equal to PERIOD there is no CMPDIF flag in down count type Note2 This bit is cleared by writing 1 to it 2 CMPUIF PWM Compare Up Count Interrupt Flag This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP Note...

Page 695: ...H1 at level detect brake state Note If TIMERx_PWM level detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period 24 BRKLSTS0 Level detect Brake Status of PWMx_CH0 Read Only 0 PWMx_CH0 level detect brake state is released 1 PWMx_CH0 at level detect brake stat...

Page 696: ...etect Brake Interrupt Flag on PWMx_CH0 Write Protect 0 PWMx_CH0 level detect brake event did not happen 1 PWMx_CH0 level detect brake event happened Note1 This bit is cleared by writing 1 to it Note2 This register is write protected Refer to SYS_REGLCTL register 7 2 Reserved Reserved 1 BRKEIF1 Edge detect Brake Interrupt Flag PWMx_CH1 Write Protect 0 PWMx_CH1 edge detect brake event did not happen...

Page 697: ...egister 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 TRGEN Reserved TRGSEL Bits Description 31 8 Reserved Reserved 7 TRGEN PWM Counter Event Trigger ADC Conversion Enable Bit 0 PWM counter event trigger ADC conversion Disabled 1 PWM counter event trigger ADC conversion Enabled 6 3 Reserved Reserved 2 0 TRGSEL PWM Count...

Page 698: ... 0 Reserved SYNCMODE Bits Description 31 9 Reserved Reserved 8 SYNCSRC PWM Synchronous Counter Start Clear Source Select 0 Counter synchronous start clear by trigger TIMER0_PWMSTRG STRGEN 1 Counter synchronous start clear by trigger TIMER2_PWMSTRG STRGEN Note1 If TIMER0 1 2 3 PWM counter synchronous source are from TIMER0 TIME0_PWMSCTL 8 TIME1_PWMSCTL 8 TIME2_PWMSCTL 8 and TIME3_PWMSCTL 8 should b...

Page 699: ...Trigger Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved STRGEN Bits Description 31 1 Reserved Reserved 0 STRGEN PWM Counter Synchronous Trigger Enable Bit Write Only PMW counter synchronous function is used to make selected PWM channels include TIMER0 1 2 3 PWM TIMER0 1 PWM and TIMER2 3 PWM start countin...

Page 700: ...WM Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved ADCTRGF 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNTMAXF Bits Description 31 17 Reserved Reserved 16 ADCTRGF Trigger ADC Start Conversion Flag 0 PWM counter event trigger ADC start conversion has not occurred 1 PWM counter event trigger ADC start conversion has occurred Note This bit is ...

Page 701: ..._PWM PBUF TMR01_BA 0x1A0 R Timer1 PWM Period Buffer Register 0x0000_0000 TIMER2_PWM PBUF TMR23_BA 0xA0 R Timer2 PWM Period Buffer Register 0x0000_0000 TIMER3_PWM PBUF TMR23_BA 0x1A0 R Timer3 PWM Period Buffer Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PBUF 7 6 5 4 3 2 1 0 PBUF Bits Description 31 16 Reserved Reserved 15 0 PBUF PWM P...

Page 702: ...MPBUF TMR01_BA 0x1A4 R Timer1 PWM Comparator Buffer Register 0x0000_0000 TIMER2_PWM CMPBUF TMR23_BA 0xA4 R Timer2 PWM Comparator Buffer Register 0x0000_0000 TIMER3_PWM CMPBUF TMR23_BA 0x1A4 R Timer3 PWM Comparator Buffer Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CMPBUF 7 6 5 4 3 2 1 0 CMPBUF Bits Description 31 16 Reserved Reserved...

Page 703: ...are four different interrupt events in this controller They are the wake up idle event device plug in or plug out event USB events like IN ACK OUT ACK etc and BUS events like suspend and resume etc Any event will cause an interrupt and users just need to check the related event flags in interrupt event status register USBD_INTSTS to acknowledge what kind of interrupt occurring and then check the r...

Page 704: ...LK0 27 Reset Configuration Reset USBD controller in USBDRST SYS_IPRST1 27 6 18 5 Functional Description 6 18 5 1 Serial Interface Engine SIE The SIE is the front end of the device controller and handles most of the USB packet protocol The SIE typically comprehends signaling up to the transaction level The functions that it handles could include Packet recognition and transaction sequencing SOF SOP...

Page 705: ... out User can acknowledge USB plug in plug out by reading USBD_VBUSDET register The VBUSDET flag represents the current state on the bus without de bouncing If VBUSDET is 1 it means the USB cable is plugged in If user polls the flag to check USB state software de bouncing must be added if needed 6 18 5 5 Interrupt Control The USB provides 1 interrupt vector with 4 interrupt events WKIDLE VBUSDET U...

Page 706: ... to USBD_ATTR 4 to disable PHY under special circumstances like suspend to conserve power 6 18 5 7 Buffer Control There is 512 bytes SRAM in the controller and the 8 endpoints share this buffer User shall configure each endpoint s effective starting address in the buffer segmentation register before the USB function active The Buffer Control block is used to control each endpoint s effective start...

Page 707: ...e After buffering the required data user needs to write the actual data length in the specified USBD_MXPLDx register Once this register is written the internal signal In_Rdy will be asserted and the buffering data will be transmitted immediately after receiving associated IN token from Host Note that after transferring the specified data the signal In_Rdy will de assert automatically by hardware U...

Page 708: ...he client device L1 Sleep L1 is similar to L2 below but supports finer granularity in use When in L1 the line state is identical to L2 Entry to L1 is started by a request to a hub or host port to transition to L1 A LPM transaction is sent to the downstream device The requested transition can only occur if the device response with an ACK handshake Exit from L1 is via remote wake resume signaling re...

Page 709: ...1 L0 L2 L3 Reset and Enable ACK response to LPM 3ms of inactivity Resume Remote wake Resume Remote wake same as L2 to L0 Disconnect Power Loss and Disable Remote Wake enable by LPM Transaction Remote wake enabled by SetFeature Device RemoteWake Figure 6 18 6 LPM State Transition Diagram ...

Page 710: ... W Endpoint 0 Maximal Payload Register 0x0000_0000 USBD_CFG0 USBD_BA 0x508 R W Endpoint 0 Configuration Register 0x0000_0000 USBD_CFGP0 USBD_BA 0x50C R W Endpoint 0 Set Stall and Clear In Out Ready Control Register 0x0000_0000 USBD_BUFSEG1 USBD_BA 0x510 R W Endpoint 1 Buffer Segmentation Register 0x0000_0000 USBD_MXPLD1 USBD_BA 0x514 R W Endpoint 1 Maximal Payload Register 0x0000_0000 USBD_CFG1 US...

Page 711: ...D_BA 0x560 R W Endpoint 6 Buffer Segmentation Register 0x0000_0000 USBD_MXPLD6 USBD_BA 0x564 R W Endpoint 6 Maximal Payload Register 0x0000_0000 USBD_CFG6 USBD_BA 0x568 R W Endpoint 6 Configuration Register 0x0000_0000 USBD_CFGP6 USBD_BA 0x56C R W Endpoint 6 Set Stall and Clear In Out Ready Control Register 0x0000_0000 USBD_BUFSEG7 USBD_BA 0x570 R W Endpoint 7 Buffer Segmentation Register 0x0000_0...

Page 712: ...ll not be updated to USBD_EPSTS register so that the USB interrupt event will not be asserted 1 IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event will be asserted when the device responds NAK after receiving IN token 14 9 Reserved Reserved 8 WKEN Wake up Function Enable Bit 0 USB Wake up Function Disabled 1 USB Wake up Function Enabled 7 5 Reserved Reserved 4 SOFIEN ...

Page 713: ...NUC126 Aug 08 2018 Page 713 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 0 BUSIEN Bus Event Interrupt Enable Bit 0 BUS Event Interrupt Disabled 1 BUS Event Interrupt Enabled ...

Page 714: ... occurred cleared by write 1 to USBD_INTSTS 23 or USBD_INTSTS 1 22 EPEVT6 Endpoint 6 s USB Event Status 0 No event occurred in endpoint 6 1 USB event occurred on Endpoint 6 check USBD_EPSTS 28 26 to know which kind of USB event was occurred cleared by write 1 to USBD_INTSTS 22 or USBD_INTSTS 1 21 EPEVT5 Endpoint 5 s USB Event Status 0 No event occurred in endpoint 5 1 USB event occurred on Endpoin...

Page 715: ...Interrupt Status 0 SOF event does not occur 1 SOF event occurred cleared by write 1 to USBD_INTSTS 4 3 WKIDLEIF No event wake up Interrupt Status 0 WKIDLE event does not occur 1 No event wake up event occurred cleared by write 1 to USBD_INTSTS 3 2 VBDETIF VBUS Detection Interrupt Status 0 There is not attached detached event in the USB 1 There is attached detached event in the USB bus and it is cl...

Page 716: ... address of a device on the USB BUS Register Offset R W Description Reset Value USBD_FADDR USBD_BA 0x008 R W USB Device Function Address Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved FADDR Bits Description 31 7 Reserved Reserved 6 0 FADDR USB Device Function Address ...

Page 717: ...te the current status of this endpoint 000 In ACK 001 In NAK 010 Out Packet Data0 ACK 011 Setup ACK 110 Out Packet Data1 ACK 111 Isochronous transfer end 28 26 EPSTS6 Endpoint 6 Status These bits are used to indicate the current status of this endpoint 000 In ACK 001 In NAK 011 Setup ACK 010 Out Packet Data0 ACK 110 Out Packet Data1 ACK 111 Isochronous transfer end 25 23 EPSTS5 Endpoint 5 Status T...

Page 718: ...Packet Data0 ACK 011 Setup ACK 110 Out Packet Data1 ACK 111 Isochronous transfer end 13 11 EPSTS1 Endpoint 1 Status These bits are used to indicate the current status of this endpoint 000 In ACK 001 In NAK 010 Out Packet Data0 ACK 011 Setup ACK 110 Out Packet Data1 ACK 111 Isochronous transfer end 10 8 EPSTS0 Endpoint 0 Status These bits are used to indicate the current status of this endpoint 000...

Page 719: ...set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged 11 LPMACK LPM Token Acknowledge Enable Bit The NYET ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState 0001 L1 is received else ERROR and STALL will be returned automatically respectively 0 the valid LPM Token will b...

Page 720: ...sceiver function Disabled 1 PHY transceiver function Enabled 3 TOUT Time out Status Read Only 0 No time out 1 No Bus response more than 18 bits time 2 RESUME Resume Status Read Only 0 No bus resume 1 Resume from suspend 1 SUSPEND Suspend Status Read Only 0 No Bus suspend 1 Bus idle more than 3ms either cable is plugged off or host is sleeping 0 USBRST USB Reset Status Read Only 0 No Bus reset 1 Bu...

Page 721: ...t Value USBD_VBUSDET USBD_BA 0x014 R USB Device VBUS Detection Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved VBUSDET Bits Description 31 1 Reserved Reserved 0 VBUSDET Device VBUS Detection 0 Controller is not attached to the USB host 1 Controller is attached to the USB host ...

Page 722: ... 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved STBUFSEG 7 6 5 4 3 2 1 0 STBUFSEG Reserved Bits Description 31 9 Reserved Reserved 8 3 STBUFSEG SETUP Token Buffer Segmentation It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is USBD_SRAM address STBUFSEG 8 3 3 b000 Where the USB...

Page 723: ... Bits Description 31 9 Reserved Reserved 8 LPMRWAKUP LPM Remote Wakeup This bit contains the bRemoteWake value received with last ACK LPM Token 7 4 LPMBESL LPM Best Effort Service Latency These bits contain the BESL value received with last ACK LPM Token 0000 125us 0001 150us 0010 200us 0011 300us 0100 400us 0101 500us 0110 1000us 0111 2000us 1000 3000us 1001 4000us 1010 5000us 1011 6000us 1100 70...

Page 724: ...escription Reset Value USBD_FN USBD_BA 0x08C R USB Frame number Register 0x0000_0XXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved FN 7 6 5 4 3 2 1 0 FN Bits Description 31 11 Reserved Reserved 10 0 FN Frame Number These bits contain the 11 bits frame number in the last received SOF packet ...

Page 725: ...Device Drive SE0 Control Register 0x0000_0001 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SE0 Bits Description 31 1 Reserved Reserved 0 SE0 Drive Single Ended Zero in USB Bus The Single Ended Zero SE0 is when both lines USB_D and USB_D are being pulled low 0 Normal operation 1 Force USB PHY transceiver to drive SE0 ...

Page 726: ...D_BUFSEG5 USBD_BA 0x550 R W Endpoint 5 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG6 USBD_BA 0x560 R W Endpoint 6 Buffer Segmentation Register 0x0000_0000 USBD_BUFSEG7 USBD_BA 0x570 R W Endpoint 7 Buffer Segmentation Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved BUFSEG 7 6 5 4 3 2 1 0 BUFSEG Reserved Bits Description 3...

Page 727: ...d 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved MXPLD 7 6 5 4 3 2 1 0 MXPLD Bits Description 31 9 Reserved Reserved 8 0 MXPLD Maximal Payload Define the data length which is transmitted to host IN token or the actual data length which is received from the host OUT token It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token 1 Wh...

Page 728: ...8 R W Endpoint 6 Configuration Register 0x0000_0000 USBD_CFG7 USBD_BA 0x578 R W Endpoint 7 Configuration Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved CSTALL Reserved 7 6 5 4 3 2 1 0 DSQSYNC STATE ISOCH EPNUM Bits Description 31 10 Reserved Reserved 9 CSTALL Clear STALL Response 0 Disable the device to clear the STALL handshak...

Page 729: ...RIES TECHNICAL REFERENCE MANUAL This bit is used to set the endpoint as Isochronous endpoint no handshake 0 No Isochronous endpoint 1 Isochronous endpoint 3 0 EPNUM Endpoint Number These bits are used to define the endpoint number of the current endpoint ...

Page 730: ...USBD_CFGP6 USBD_BA 0x56C R W Endpoint 6 Set Stall and Clear In Out Ready Control Register 0x0000_0000 USBD_CFGP7 USBD_BA 0x57C R W Endpoint 7 Set Stall and Clear In Out Ready Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SSTALL CLRRDY Bits Description 31 2 Reserved Reserved 1 SSTALL Set STALL 0...

Page 731: ...CIx_CTL0 1 Wake up Control Protocol Relative Clock Generator fPCLK Output Configuration Note x 0 1 or 2 Figure 6 19 1 USCI Block Diagram 6 19 4 Functional Description The structure of the Universal Serial Control Interface USCI controller is shown in Figure 6 19 1 USCI Block Diagram The input signal is implemented in input processor The data buffers and the data shift unit support the data transfe...

Page 732: ..._CTL1 Data Input USCIx_DAT0 RX SPI_MOSI_0 SDA USCIx_DAT1 SPI_MISO_0 Table 6 19 1 Input Signals for Different Protocols The description of protocol specific items are given in the related protocol chapters General Input Structure The input structures of data and control signals include inverter digital filter and edge detection data signal only Data Shift Unit Digital Filter USCIx_DAT 1 0 USCIx_CTL...

Page 733: ...ate machine If the SYNCSEL USCI_DATIN0 0 USCI_CTLIN0 0 USCI_CLKIN 0 is set to 0 the paths of input signals do not contain any delay due to synchronization or filtering If there is noise on the input signals there is the possibility to synchronize the input signal signal IN_SYNC is synchronized to fPCLK The synchronized input signal is taken into account by SYNCSEL 1 The synchronization leads to a ...

Page 734: ...e data interrupts status and control information A transmitter includes transmit shift register TX_SFTR and a transmit data buffer TX_BUF The TXFULL TXEMPTY USCI_BUFSTS 9 8 and TXENDIF USCI_PROTSTS 2 can indicate the status of transmitter A receiver includes receive shift register RX_SFTR and a double receive buffer structure RX_BUF0 RX_BUF1 In double buffer structure user need not care about the ...

Page 735: ...or transmission Shift Control Status Control TX_SFTR Data Serial Bus Clock Input Control Input Shift Data Output TX_BUF 16 Transmit Buffer Status USCI_LINECTL USCI_BUFSTS USCI_TXDAT Figure 6 19 6 Transmit Data Path Transmit Data Validation The status of TXEMPTY USCI_BUFSTS 8 indicates the transmission data is valid or not in the transmit buffer TX_BUF and the TXSTIF USCI_PROTSTS 1 labels the start...

Page 736: ...USCI_BUFSTS 8 will be cleared automatically when transmit buffer TX_BUF is updated with new data While a transmission is in progress TX_BUF can be loaded with new data User has to update the TX_BUF before a new transmission Receive Data Path The receive data path is based on 16 bit wide receive shift register RX_SFTR and receive buffers RX_BUF0 and RX_BUF1 The data transfer parameters like data wo...

Page 737: ...ocol Related Clock fSAMP_CL K fDS_CNT 0 1 Protocol Processor Unit Note Refer the Basic Clock Divider Counter section to get the fSAMP_CLK Figure 6 19 8 Protocol Relative Clock Generator The protocol related counter contains basic clock divider counter and timing measurement counter It is based on a divider stages providing the frequencies needed for the different protocols It contains The basic cl...

Page 738: ... with fPROT_CLK or fDIV_CLK It stops counting when it reaches the user specified value Divider by 2 0 1 fREF_CLK PTCTLSEL USCI_BRGEN 1 Up Counter fPROT_CLK Protocol Relation Definition Clear 0 1 fDIV_CLK FUNMODE USCI_CTL 2 0 TMCNTSRC USCI_BRGEN 5 TMCNTEN USCI_BRGEN 4 Figure 6 19 10 Block of Timing Measurement Counter The timing measurement counter is used to perform time out function or auto baud ...

Page 739: ...it start interrupt Transmit end interrupt event to indicate that a data word transmission has been done A transmit end interrupt event occurs when the current transmit data in shift register had finished It is indicated by flag TXENDIF USCI_PROTSTS 2 and if enabled leads to transmit end interrupt This event also indicates when the shift control settings word length shift direction etc are internal...

Page 740: ...CI are shown in Table 6 19 3 Table 6 19 3 Data Transfer Events and Interrupt Handling 6 19 4 7 Protocol specific Events and Interrupts These events are related to protocol specific actions that are described in the corresponding protocol chapters The related indication flags are located in register USCI_PROTSTS All events can be individually enabled for the generation of the common protocol interr...

Page 741: ...ed wake up functional information is located in the Wake up Control Register USCI_WKCTL and in the Wake up Status Register USCI_WKSTS These registers are shared between the available protocols As a consequence the meaning of the bit positions in these registers is different within the protocols Protocol specific events in I2 C mode USCI_PROTSTS 13 8 USCI_PROTSTS 5 USCI_PROTIEN 6 0 ...

Page 742: ...re are two conditions to wake up the system 6 20 2 Features Supports one transmit buffer and two receive buffer for data payload Supports hardware auto flow control function Supports programmable baud rate generator Support 9 Bit Data Transfer Support 9 Bit RS 485 Baud rate detection possible by built in capture event of baud rate generator Supports Wake up function Data and nCTS Wakeup Only 6 20 ...

Page 743: ...rs Group Pin Name GPIO MFP USCI0 USCI0_CLK PE 5 MFP4 PC 4 MFP5 PB 9 MFP8 USCI0_CTL0 PE 4 MFP4 PC 3 MFP5 PB 8 PE 2 MFP8 USCI0_CTL1 PC 2 PC 7 MFP4 PB 4 MFP8 USCI0_DAT0 PC 0 PC 5 MFP4 PB 2 MFP8 USCI0_DAT1 PC 1 PC 6 MFP4 PB 3 MFP8 6 20 4 2 Basic Configuration of USCI1 UART Clock Source Configuration Enable USCI1 peripheral clock in USCI1CKEN CLK_APBCLK1 9 Reset Configuration Reset USCI1 controller in ...

Page 744: ...IPRST2 10 Pin Configuration USCI2 pins are configured in SYS_GPB_MFPL SYS_GPC_MFPH SYS_GPD_MFPL SYS_GPD_MFPH and SYS_GPF_MFPL registers Group Pin Name GPIO MFP USCI2 USCI2_CLK PC 11 PD 1 MFP4 PF 2 MFP5 USCI2_CTL0 PC 12 PD 0 PD 9 MFP4 PF 1 MFP5 USCI2_CTL1 PB 7 PC 9 PD 8 MFP4 PF 0 MFP5 USCI2_DAT0 PC 13 PD 2 MFP4 PD 10 MFP5 USCI2_DAT1 PC 10 PD 3 MFP4 PD 11 MFP5 6 20 5 Functional Description 6 20 5 1 ...

Page 745: ...CIx_DAT1 USCIx_DAT0 RXD TXD TXD RXD Figure 6 20 2 UART Signal Connection for Full Duplex Communication Input Signal For UART protocol the number of input signals be figured in Table 6 20 1 Each input signal is handled by an input processor for signal conditioning such as signal inverse selection control or a digital input filter They can be classified according to their meaning for the protocols s...

Page 746: ...dered to be due to noise and the receiver is considered to be idle again Data Field The length of the data field number of data bits can be programmed by the bit field of DWIDTH UUART_LINECTL 11 8 It can vary between 6 to 13 data bits Note In UART protocol the data transmission order is LSB first by setting LSB UUART_LINECTL 0 to 1 Parity Bit The UART allows parity generation for transmission and ...

Page 747: ...ignal nCTS in UART protocol The property of input control signal can be configured in UUART_CTLIN0 The USCI_CTL1 pin is used for UART request to send signal nRTS in UART protocol The property of output control signal can be configured in UUART_LINECTL Bit Timing Configuration The desired baud rate setting has to be selected comprising the baud rate generator and the bit timing Frame Format Configu...

Page 748: ...PCLKSEL 2 b00 fSAMP_CLK fDIV_CLK Under these conditions the baud rate is given by To generate slower frequencies additional divide by 2 stages can be selected by PTCLKSEL 1 fPROT_CLK fREF_CLK2 leading to If SPCLKSEL 2 b10 fSAMP_CLK fSCLK and RCLKSEL 0 fREF_CLK fPCLK PTCLKSEL 0 fPROT_CLK fREF_CLK The baud rate is given by 6 20 5 7 Auto Baud Rate Detection The UART controller supports auto baud rate...

Page 749: ... time of timing measurement counter can t calculate the correct period of the input bit time there is a ABERRSTS bit UUART_PROTSTS 11 to indicate the error information of the auto baud rate detection At this time the user shall revise the value of CLKDIV and require the Host device to send the 0x55 pattern again According the limitation of timing measurement counter the maximum auto baud rate dete...

Page 750: ...CNT UUART_PROTCTL 14 11 shall be set These bits field of WAKECNT UUART_PROTCTL 14 11 indicate how many clock cycle selected by fPDS_CLK do the controller can get the 1 st bit start bit when the device is wakeup from Power down mode Note1 By the WAKECNT is loaded into the hardware counter at the time of WKF UUART_WKSTS 0 is clear so that the user shall clear the wakeup flag first to make sure the t...

Page 751: ...laborated for each data frame The break error flag is assigned when the receive data is 0 the received parity and the stop bit are also 0 The interrupt indicates that there are parity error frame error or the break data detection in the BREAK FRMERR PARITYERR UUART_PROTSTS 7 5 bits Auto Baud Rate Detection The auto baud rate interrupt ABRDETIF UUART_PROTSTS 9 indicate that the timing measurement c...

Page 752: ...nd PDSCNT UUART_BRGEN 9 8 to determine the baud rate divider 3 Write line control register UUART_LINECTL and protocol control register UUART_PROTCTL to configure the transmission data format and UART protocol setting Program data field length in DWIDTH UUART_LINECTL 11 8 Enable parity bit and determine the parity bit type by setting EVENPARITY UUART_PROTCTL 2 and PARITYEN UUART_PROTCTL 1 Configure...

Page 753: ... 0x0000_0000 UUART_CLKIN UUARTx_BA 0x28 R W USCI Input Clock Signal Configuration Register 0x0000_0000 UUART_LINECTL UUARTx_BA 0x2C R W USCI Line Control Register 0x0000_0000 UUART_TXDAT UUARTx_BA 0x30 W USCI Transmit Data Register 0x0000_0000 UUART_RXDAT UUARTx_BA 0x34 R USCI Receive Data Register 0x0000_0000 UUART_BUFCTL UUARTx_BA 0x38 R W USCI Transmit Receive Buffer Control Register 0x0000_000...

Page 754: ...iption 31 3 Reserved Reserved 2 0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller Selecting a protocol that is not available or a reserved combination disables the USCI When switching between two protocols the USCI has to be disabled before selecting a new protocol Simultaneously the USCI will be reset when user write 000 to FUNMODE 000 The USCI is disabled All p...

Page 755: ...ation in case of a receive finish event 0 The receive end interrupt Disabled 1 The receive end interrupt Enabled 3 RXSTIEN Receive Start Interrupt Enable Bit This bit enables the interrupt generation in case of a receive start event 0 The receive start interrupt Disabled 1 The receive start interrupt Enabled 2 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt generation in ...

Page 756: ...t 6 The user can use revised CLKDIV and new BRDETITV UUART_PROTCTL 24 16 to calculate the precise baud rate 15 Reserved Reserved 14 10 DSCNT Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK The divided frequency fDS_CNT fPDS_CNT DSCNT 1 Note The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is s...

Page 757: ...CLK fSCLK 11 fSAMP_CLK fREF_CLK 1 PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock fPROT_CLK 0 Reference clock fREF_CLK 1 fREF_CLK2 its frequency is half of fREF_CLK 0 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock fREF_CLK 0 Peripheral device clock fPCLK 1 Reserved ...

Page 758: ...ctivates the trigger event of input data signal 10 A falling edge activates the trigger event of input data signal 11 Both edges activate the trigger event of input data signal Note In UART function mode it is suggested to set this bit field as 10 2 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal will not...

Page 759: ...ption 31 3 Reserved Reserved 2 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal will not be inverted 1 The un synchronized input signal will be inverted 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal with optionally inverted or the ...

Page 760: ...4 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SYNCSEL Bits Description 31 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal or the synchronized and optionally filtered signal can be used as input for the data shift unit 0 The un synchronized signal can be taken as input for...

Page 761: ...d at bit positions 15 0 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 The data word contains 4 bits located at bit positions 3 0 0x5 The data word contains 5 bits located at bit positions 4 0 0xF The data word contains 15 bits located at bit positions 14 0 Note In UART protocol the length can be configured as 6 13 bits 7 CTLOINV Control Signal Output Inverse Selection This bit defines the relation be...

Page 762: ...RIES TECHNICAL REFERENCE MANUAL 0 LSB LSB First Transmission Selection 0 The MSB which bit of transmit receive data buffer depends on the setting of DWIDTH is transmitted received first 1 The LSB the bit 0 of data buffer will be transmitted received first ...

Page 763: ...cription Reset Value UUART_TXDAT UUARTx_BA 0x30 W USCI Transmit Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TXDAT 7 6 5 4 3 2 1 0 TXDAT Bits Description 31 16 Reserved Reserved 15 0 TXDAT Transmit Data Software can use this bit field to write 16 bit transmit data for transmission ...

Page 764: ...R USCI Receive Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXDAT 7 6 5 4 3 2 1 0 RXDAT Bits Description 31 16 Reserved Reserved 15 0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer Note RXDAT 15 13 indicate the same frame status of BREAK FRMERR and PARITYERR UUART_PROTSTS 7 5 ...

Page 765: ...ore this bit will be set to 1 16 TXRST Transmit Reset 0 No effect 1 Reset the transmit related counters state machine and the content of transmit shift register and data buffer Note It is cleared automatically after one PCLK cycle 15 RXCLR Clear Receive Buffer 0 No effect 1 The receive buffer is cleared filling level is cleared and output pointer is set to input pointer value Should only be used w...

Page 766: ...NUC126 Aug 08 2018 Page 766 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 6 0 Reserved Reserved ...

Page 767: ...full 1 Transmit buffer is full 8 TXEMPTY Transmit Buffer Empty Indicator 0 Transmit buffer is not empty 1 Transmit buffer is empty 7 4 Reserved Reserved 3 RXOVIF Receive Buffer Over run Error Interrupt Status This bit indicates that a receive buffer overrun error event has been detected If RXOVIEN UUART_BUFCTL 14 is enabled the corresponding interrupt request is activated It is cleared by software...

Page 768: ... 0 Reserved PDBOPT Reserved WKEN Bits Description 31 3 Reserved Reserved 2 PDBOPT Power Down Blocking Option 0 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring MCU will stop the transfer and enter Power down mode immediately 1 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring the on going transfer will n...

Page 769: ...Value UUART_WKSTS UUARTx_BA 0x58 R W USCI Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKF Bits Description 31 1 Reserved Reserved 0 WKF Wake up Flag When chip is woken up from Power down mode this bit is set to 1 Software can write 1 to clear this bit ...

Page 770: ...utput TX is forced to the Spacing State logic 0 This bit acts only on TX line and has no effect on the transmitter logic 27 Reserved Reserved 26 STICKEN Stick Parity Enable Bit 0 Stick parity Disabled 1 Stick parity Enabled Note Refer to RS 485 Support section for detail information 25 Reserved Reserved 24 16 BRDETITV Baud Rate Detection Interval This bit fields indicate how many clock cycle selec...

Page 771: ...the RTSAUTOEN is not set 4 CTSAUTOEN nCTS Auto flow Control Enable Bit When nCTS auto flow is enabled the UART will send data to external device when nCTS input assert UART will not send data to device if nCTS input is dis asserted 0 nCTS auto flow control Disabled 1 nCTS auto flow control Enabled 3 RTSAUTOEN nRTS Auto flow Control Enable Bit When nRTS auto flow is enabled if the receiver buffer i...

Page 772: ...22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved RLSIEN ABRIEN Reserved Bits Description 31 3 Reserved Reserved 2 RLSIEN Receive Line Status Interrupt Enable Bit 0 Receive line status interrupt Disabled 1 Receive line status interrupt Enabled Note UUART_PROTSTS 7 5 indicates the current interrupt event for receive line status interrupt 1 ABRIEN Auto baud Rate I...

Page 773: ...l Status Read Only This bit is used to indicate the current status of the internal synchronized nCTS signal 0 The internal synchronized nCTS is low 1 The internal synchronized nCTS is high 15 12 Reserved Reserved 11 ABERRSTS Auto baud Rate Error Status This bit is set when auto baud rate detection counter overrun When the auto baud rate counter overrun the user shall revise the CLKDIV UUART_BRGEN ...

Page 774: ...generated 1 Framing error is generated Note This bit can be cleared by write 1 among the BREAK FRMERR and PARITYERR bits 5 PARITYERR Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit 0 No parity error is generated 1 Parity error is generated Note This bit can be cleared by write 1 among the BREAK FRMERR and PARITYERR bits 4 RXENDIF Receiv...

Page 775: ... in master and Slave mode are shown below SPI Slave Device Master Transmit Data Master Receive Data Serial Bus Clock Slave Select SPI_MOSI USCIx_DAT0 SPI_MISO USCIx_DAT1 SPI_CLK USCIx_CLK SPI_SS USCIx_CTL SPI_MOSI SPI_MISO USCI SPI Master USCI SPI Master SPI_CLK SPI_SS Note x 0 1 2 Figure 6 21 1 SPI Master Mode Application Block Diagram SPI Master Device Slave Receive Data Slave Transmit Data Seri...

Page 776: ...Buffer Control Interrupt Generation USCIx_DAT0 1 To Interrupt Signal USCIx_CLK USCIx_CTL0 Wake up Control Protocol Relative Clock Generator fPCLK Output Configuration Note x 0 1 or 2 Figure 6 21 3 USCI SPI Mode Block Diagram 6 21 4 Basic Configuration 6 21 4 1 Basic Configuration of USCI0 SPI Clock Source Configuration Enable USCI0 peripheral clock in USCI0CKEN CLK_APBCLK1 8 Enable USCI0_SPI funct...

Page 777: ... Enable USCI1_SPI functi on USCI_CTL 2 0 register USCI_CTL 2 0 3 b001 Reset Configuration Reset USCI1 controller in USCI1RST SYS_IPRST2 9 Pin Configuration Group Pin Name GPIO MFP USCI1 USCI1_CLK PD 15 MFP1 PA 15 MFP4 PA 3 MFP8 USCI1_CTL0 PD 12 MFP1 PA 0 MFP4 PA 2 MFP8 USCI1_CTL1 PD 7 MFP1 PA 1 PA 14 MFP4 USCI1_DAT0 PD 14 MFP1 PB 0 MFP6 USCI1_DAT1 PD 13 MFP1 PB 1 MFP8 6 21 4 3 Basic Configuration ...

Page 778: ... a data transfer as well as the generation of the SPI bus clock and slave select signal The slave select signal indicates the start and the end of a data transfer and the master device can use it to enable the transmitting or receiving operations of Slave device Slave device receives the SPI bus clock and optionally a slave select signal for data transaction The signals for SPI communication are s...

Page 779: ... USCI controller needs the peripheral clock to drive the USCI logic unit to perform the data transfer The peripheral clock frequency is equal to PCLK frequency In Master mode the frequency of the SPI bus clock is determined by protocol relative clock generator In general the SPI bus clock is denoted as SPI clock The frequency of SPI clock is half of fSAMP_CLK which can be selected by SPCLKSEL USPI...

Page 780: ...E 1 0 SPI Clock Idle State Transmit Timing Receive Timing 0x0 Low Falling edge Rising edge 0x1 Low Rising edge Falling edge 0x2 High Rising edge Falling edge 0x3 High Falling edge Rising edge Table 6 21 2 Serial Bus Clock Configuration Figure 6 21 6 SPI Communication with Different SPI Clock Configuration SCLKMODE 0x0 Data N Data N 1 Data Frame SPI_SS USCIx_CTL0 SPI_MOSI USCIx_DAT0 SPI_CLK USCIx_C...

Page 781: ...Ix_CLK SPI_MISO USCIx_DAT1 MSB TX n TX n 1 RX n 1 MSB RX n MSB TX n TX n 1 LSB TX 0 LSB RX 0 RX n 1 MSB RX n LSB TX 0 LSB RX 0 Note x 0 1 2 USPI_PROTCTL 0 0 USPI_PROTCTL 7 6 0x1 USPI_CTLIN0 2 1 USPI_LINECTL 0 0 USPI_LINECTL 7 1 Data N Data N 1 Data Frame SPI_SS USCIx_CTL0 SPI_MOSI USCIx_DAT0 SPI_CLK USCIx_CLK SPI_MISO USCIx_DAT1 MSB TX n TX n 1 LSB TX 0 LSB RX 0 RX n 1 MSB RX n MSB TX n TX n 1 LSB...

Page 782: ...ion between the slave select active edge and the first SPI clock input edge shall over 2 USCI peripheral clock cycles The input slave select signal of SPI Slave has to be keep inactive for at least 2 USCI peripheral clock cycles between two consecutive frames in order to correctly detect the end of a frame 6 21 5 5 Transmit and Receive Data The bit length of a transmit receive data word in SPI pro...

Page 783: ...n Word MSB RX 15 MSB TX 15 Transfer Frame Suspend Interval Note Timing Condition is SCLKMODE 1 0 0x0 LSB 0 DWIDTH 3 0 0x0 Note x 0 1 2 Figure 6 21 11 Word Suspend Interval between Two Transaction Words 6 21 5 7 Automatic Slave Select Function AUTOSS USPI_PROTCTL 3 is used for SPI Master mode to enable the automatic slave select function If the bit AUTOSS USPI_PROTCTL 3 is set the slave select sign...

Page 784: ...NV USPI_LINECTL 7 SPI_CLK USCIx_CLK SS USPI_PROTCTL 2 Note Automatic slave select is enabled 1 SPI clock 1 5 SPI clock Figure 6 21 12 Auto Slave Select SUSPITV 0x3 SPI_SS USCIx_CTL0 TXEMPTY USPI_BUFSTS 8 CTLOINV USPI_LINECTL 7 SPI_CLK USCIx_CLK SS USPI_PROTCTL 2 Note Automatic slave select is enabled One word transaction One word transaction Figure 6 21 13 Auto Slave Select SUSPITV 0x3 6 21 5 8 Sl...

Page 785: ...level of the last data bit of a data word is held on USCIx_DAT0 pin until the next data word begins with the next corresponding edge of the serial bus clock One Data Channel Half duplex SPI Transfer In one data channel half duplex SPI transfer there is only one data pin for data transfer Thus the data transmission and data reception are at different time interval The data shift direction is determ...

Page 786: ... start interrupt The interrupt event TXSTIF USPI_PROTSTS 1 is set after the start of the first data bit of a transmit data word It can be cleared only by writing 1 to it Transmit end interrupt The interrupt event TXENDIF USPI_PROTSTS 2 is set after the start of the last data bit of the last transmit data which has been stored in transmit buffer It can be cleared only by writing 1 to it Receive sta...

Page 787: ...saction If the value of the time out counter is equal to or greater than the value of SLVTOCNT USPI_PROTCTL 25 16 before one word transaction is done the Slave time out interrupt event occurs and the SLVTOIF USPI_PROTSTS 5 will be set to 1 Buffer Related Interrupts The buffer related interrupts are available if there is transmit receive buffer in USCI controller Receive buffer overrun interrupt If...

Page 788: ... 1 Master Mode FUNMODE 0x1 SLAVE 0 LSB 0 DWIDTH 0x8 SCLKMODE 0x2 CTLOINV 0 CTLOINV 1 Figure 6 21 16 SPI Timing in Master Mode SPI_CLK SPI_MISO SPI_MOSI TX 1 TX 3 TX 4 TX 5 MSB TX 7 RX 1 RX 3 RX 5 MSB RX 7 LSB RX 0 RX 4 LSB TX 0 SPI_SS SCLKMODE 0x1 TX 2 RX 2 TX 6 RX 6 SCLKMODE 0x3 Master Mode FUNMODE 0x1 SLAVE 0 LSB 1 DWIDTH 0x8 CTLOINV 0 CTLOINV 1 Figure 6 21 17 SPI Timing in Master Mode Alternate...

Page 789: ...X1 1 MSB TX1 7 RX0 1 RX0 7 RX1 1 MSB RX1 7 LSB RX0 0 RX1 0 LSB TX0 0 SPI_SS SCLKMODE 0x1 SCLKMODE 0x3 Slave Mode FUNMODE 0x1 SLAVE 1 SLV3WIRE 0 LSB 1 DWIDTH 0x8 CTLOINV 0 CTLOINV 1 Figure 6 21 19 SPI Timing in Slave Mode Alternate Phase of Serial Bus Clock 6 21 5 12Programming Flow This section describes the programming flow for USCI SPI data transfer For Master mode 1 Enable USCI peripheral clock...

Page 790: ... USPI_BUFSTS 0 is 0 The SPI data transfer can be triggered by writing USPI_TXDAT register as long as TXFULL USPI_BUFSTS 9 is 0 For Slave mode 1 Enable USCI peripheral clock by setting CLK_APBCLK1 register 2 Configure user specified pins as USCI function pins by setting corresponding multiple function control registers 3 Set FUNMODE USPI_CTL 2 0 to 1 to select SPI mode 4 According to the requiremen...

Page 791: ...NUC126 Aug 08 2018 Page 791 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL protocol is the transition of input slave select signal ...

Page 792: ...er 0 0x0000_0000 USPI_CLKIN USPIx_BA 0x28 R W USCI Input Clock Signal Configuration Register 0x0000_0000 USPI_LINECTL USPIx_BA 0x2C R W USCI Line Control Register 0x0000_0000 USPI_TXDAT USPIx_BA 0x30 W USCI Transmit Data Register 0x0000_0000 USPI_RXDAT USPIx_BA 0x34 R USCI Receive Data Register 0x0000_0000 USPI_BUFCTL USPIx_BA 0x38 R W USCI Transmit Receive Buffer Control Register 0x0000_0000 USPI...

Page 793: ...tion 31 3 Reserved Reserved 2 0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller Selecting a protocol that is not available or a reserved combination disables the USCI When switching between two protocols the USCI has to be disabled before selecting a new protocol Simultaneously the USCI will be reset when user write 000 to FUNMODE 000 The USCI is disabled All pro...

Page 794: ...ion in case of a receive finish event 0 The receive end interrupt Disabled 1 The receive end interrupt Enabled 3 RXSTIEN Receive Start Interrupt Enable Bit This bit enables the interrupt generation in case of a receive start event 0 The receive start interrupt Disabled 1 The receive start interrupt Enabled 2 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt generation in ca...

Page 795: ... C function the minimum value of CLKDIV is 8 15 6 Reserved Reserved 5 TMCNTSRC Time Measurement Counter Clock Source Selection 0 Time measurement counter with fPROT_CLK 1 Time measurement counter with fDIV_CLK 4 TMCNTEN Time Measurement Counter Enable Bit This bit enables the 10 bit timing measurement counter 0 Time measurement counter Disabled 1 Time measurement counter Enabled 3 2 SPCLKSEL Sampl...

Page 796: ...NUC126 Aug 08 2018 Page 796 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 0 Peripheral device clock fPCLK 1 Reserved ...

Page 797: ...is bit defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal will not be inverted 1 The un synchronized input signal will be inverted Note In SPI protocol it is suggested this bit should be set as 0 1 Reserved Reserved 0 SYNCSEL Input Signal Synchronization Selection This bit selects if the un synchronized input signal with optionally inverted or the synch...

Page 798: ...NV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal will not be inverted 1 The un synchronized input signal will be inverted 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal with optionally inverted or the synchronized and optionally filter...

Page 799: ... Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SYNCSEL Bits Description 31 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal or the synchronized and optionally filtered signal can be used as input for the data shift unit 0 The un synchronized signal can be taken as input for the data shift unit 1 The synchro...

Page 800: ...ated at bit positions 15 0 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 The data word contains 4 bits located at bit positions 3 0 0x5 The data word contains 5 bits located at bit positions 4 0 0xF The data word contains 15 bits located at bit positions 14 0 7 CTLOINV Control Signal Output Inverse Selection This bit defines the relation between the internal control signal and the output control sign...

Page 801: ... Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 0 The MSB which bit of transmit receive data buffer depends on the setting of DWIDTH is transmitted received first 1 The LSB the bit 0 of data buffer will be transmitted received first ...

Page 802: ...ction Control This bit field is only available while USCI operates in SPI protocol FUNMODE 0x1 with half duplex transfer It is used to define the direction of the data port pin When software writes USPI_TXDAT register the transmit data and its port direction are settled simultaneously 0 The data pin is configured as output mode 1 The data pin is configured as input mode 15 0 TXDAT Transmit Data So...

Page 803: ...scription Reset Value USPI_RXDAT USPIx_BA 0x34 R USCI Receive Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXDAT 7 6 5 4 3 2 1 0 RXDAT Bits Description 31 16 Reserved Reserved 15 0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer ...

Page 804: ...one PCLK cycle 16 TXRST Transmit Reset 0 No effect 1 Reset the transmit related counters state machine and the content of transmit shift register and data buffer Note It is cleared automatically after one PCLK cycle 15 RXCLR Clear Receive Buffer 0 No effect 1 The receive buffer is cleared Should only be used while the buffer is not taking part in data traffic Note It is cleared automatically after...

Page 805: ...NUC126 Aug 08 2018 Page 805 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 1 Transmit under run interrupt Enabled 5 0 Reserved Reserved ...

Page 806: ...are writes 1 to this bit 0 A transmit buffer under run event has not been detected 1 A transmit buffer under run event has been detected 10 Reserved Reserved 9 TXFULL Transmit Buffer Full Indicator 0 Transmit buffer is not full 1 Transmit buffer is full 8 TXEMPTY Transmit Buffer Empty Indicator 0 Transmit buffer is not empty 1 Transmit buffer is empty and available for the next transmission datum ...

Page 807: ...NUC126 Aug 08 2018 Page 807 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 0 Receive buffer is not empty 1 Receive buffer is empty ...

Page 808: ...rved Reserved 2 PDBOPT Power Down Blocking Option 0 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring MCU will stop the transfer and enter Power down mode immediately 1 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring the on going transfer will not be stopped and MCU will enter idle mode immediately 1 WK...

Page 809: ... Value USPI_WKSTS USPIx_BA 0x58 R W USCI Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKF Bits Description 31 1 Reserved Reserved 0 WKF Wake up Flag When chip is woken up from Power down mode this bit is set to 1 Software can write 1 to clear this bit ...

Page 810: ...Slave mode this bit field is used for Slave time out period This bit field indicates how many clock periods selected by TMCNTSRC USPI_BRGEN 5 between the two edges of input SCLK will assert the Slave time out event Writing 0x0 into this bit field will disable the Slave time out function Example Assume SLVTOCNT is 0x0A and TMCNTSRC USPI_BRGEN 5 is 1 it means the time out event will occur if the sta...

Page 811: ...gh level Data is transmitted with falling edge and received with rising edge 5 4 Reserved Reserved 3 AUTOSS Automatic Slave Select Function Enable Master Only 0 Slave select signal will be controlled by the setting value of SS USPI_PROTCTL 2 bit 1 Slave select signal will be generated automatically The slave select signal will be asserted by the SPI controller when transmit receive is started and ...

Page 812: ...H USPI_LINECTL 11 8 Bit count error event occurs 0 The Slave mode bit count error interrupt Disabled 1 The Slave mode bit count error interrupt Enabled 2 SLVTOIEN Slave Time out Interrupt Enable Bit In SPI protocol this bit enables the interrupt generation in case of a Slave time out event 0 The Slave time out interrupt Disabled 1 The Slave time out interrupt Enabled 1 SSACTIEN Slave Select Active...

Page 813: ...does not occur 1 Slave transmit under run event occurs 17 BUSY Busy Status Read Only 0 SPI is in idle state 1 SPI is in busy state The following lists the bus busy conditions a USPI_PROTCTL 31 1 and the TXEMPTY 0 b For SPI Master mode the TXEMPTY 1 but the current transaction is not finished yet c For SPI Slave mode the USPI_PROTCTL 31 1 and there is serial clock input into the SPI core logic when...

Page 814: ...ent occurs Note It is cleared by software write 1 to this bit 5 SLVTOIF Slave Time out Interrupt Flag for Slave Only 0 Slave time out event did not occur 1 Slave time out event occurred Note This bit is cleared by software writing 1 to it 4 RXENDIF Receive End Interrupt Flag 0 Receive end event does not occur 1 Receive end event occurred Note This bit is cleared by software writing 1 to it 3 RXSTI...

Page 815: ...STA tSU_STO STOP tr Figure 6 22 1 I 2 C Bus Timing The device s on chip I 2 C provides the serial interface that meets the I 2 C bus standard mode specification The I 2 C port handles byte transfers autonomously The I 2 C mode is selected by FUNMODE UI2C_CTL 2 0 100b When enable this port the USCI interfaces to the I 2 C bus via two pins SDA and SCL When I O pins are used as I 2 C ports user must ...

Page 816: ...rol Baud Rate Generation fPCLK Output Configuration Figure 6 22 2 USCI I C Mode Block Diagram 6 22 4 Basic Configuration 6 22 4 1 Basic Configuration of USCI0 I2C Clock Source Configuration Enable USCI0 I2C peripheral clock in USCI0CKEN CLK_APBCLK1 8 Reset Configuration Reset USCI0 I2C controller in USCI0RST SYS_IPRST2 8 Pin Configuration Group Pin Name GPIO MFP USCI0 USCI0_CLK PE 5 MFP4 PC 4 MFP5...

Page 817: ...ion Group Pin Name GPIO MFP USCI1 USCI1_CLK PD 15 MFP1 PA 15 MFP4 PA 3 MFP8 USCI1_CTL0 PD 12 MFP1 PA 0 MFP4 PA 2 MFP8 USCI1_CTL1 PD 7 MFP1 PA 1 PA 14 MFP4 USCI1_DAT0 PD 14 MFP1 PB 0 MFP6 USCI1_DAT1 PD 13 MFP1 PB 1 MFP8 6 22 4 3 Basic Configuration of USCI2 I2C Clock Source Configuration Enable USCI2 I2C peripheral clock in USCI2CKEN CLK_APBCLK1 10 Reset Configuration Reset USCI2 I2C controller in ...

Page 818: ...a master can initiate a transfer by sending a START signal A START signal usually referred to as the S bit is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH The START signal denotes the beginning of a new data transmission A Repeated START is a START signal between START signal and STOP signal and usually referred to as the Sr bit The master uses this method to communicate w...

Page 819: ...7 bits of a received first address byte are compared to the programmed slave address UI2C_DEVADDRn 6 0 If these bits match the slave sends an acknowledge In addition to this if the slave address is programmed to 1111 0XXB the XX bits are compared to the bits UI2C_DEVADDR 9 8 to check for address match and also sends an acknowledge when ADDR10EN UI2C_PROTCTL 4 is set The slave waits for a second ad...

Page 820: ...ion please refer to Figure 6 19 9 basic clock divider counter The data baud rate of I 2 C is determines by UI2C_BRGEN register when I 2 C is in Master Mode and it is not necessary in a Slave mode In the Slave mode I 2 C will automatically synchronize it with any clock frequency from master I 2 C device The bits RCLKSEL SPCLKSEL PDSCNT and DSCNT define the baud rate setting RCLKSEL UI2C_BRGEN 0 to ...

Page 821: ...orruption If two masters sometimes initiate I 2 C command at the same time the arbitration procedure determines which master wins and can continue with the command Arbitration is performed on the SDA signal while the SCL signal is high Each master checks if the SDA signal on the bus corresponds to the generated SDA signal If the SDA signal on the bus is low but it should be high then this master h...

Page 822: ...the baud rate as a function of fPCLK and fPROT_CLK We suggest user adopt fPCLK 6 22 5 9 Non Acknowledge and Error Conditions In case of a non acknowledge NACKIF UI2C_PROTSTS 10 or an error ERRIF UI2C_PROTSTS 12 no further transmission will take place User software doesn t invalidate the transmit buffer and disable transmissions before configuring the transmission by writing TXDAT again with approp...

Page 823: ...r by setting the AA bit acknowledge pulse will be transmitted out on the 9th clock hence an interrupt is requested on both master and slave devices if interrupt is enabled When the microcontroller wishes to become the bus master hardware waits until the bus is free before entering Master mode so that a possible slave action is not be interrupted If address arbitration is lost in Master mode I 2 C ...

Page 824: ...NUC126 Aug 08 2018 Page 824 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL Figure 6 22 8 Control I 2 C Bus according to Current I 2 C Status ...

Page 825: ...rt transmitting data after the slave returns acknowledge to the master 1 read S SLAVE ADDRESS R W A DATA A DATA A A P data transfer n bytes acknowlegde Figure 6 22 10 Master Reads Data from Slave with a 7 bit address Figure 6 22 11 shows a master transmits data to slave by 10 bit address A master addresses a slave with a 10 bit address First byte contains 10 bit address indicator 5 b11110 and 2 bi...

Page 826: ...ear protocol status register ACKIF 1 NACKIF 1 ACKIF 1 NACKIF 1 TXDAT Data PTRG STA STO AA 1 0 0 x Writing 1 to ACKIF Writing 1 to NACKIF STARIF 1 PTRG STA STO AA 1 1 0 x Writing 1 to ACKIF Writing 1 to NACKIF STORIF 1 PTRG STA STO AA 1 0 1 x Writing 1 to ACKIF Writing 1 to NACKIF STARIF 1 PTRG STA STO AA 1 1 1 x Writing 1 to ACKIF Writing 1 to NACKIF TXDAT SLA W ARBLOIF 1 TXDAT SLA W PTRG STA STO ...

Page 827: ... 0 1 ARBLOIF 1 ACK To corresponding states in slave mode Figure 6 22 14 Master Receiver Mode Control Flow with 7 bit Address If the I 2 C is in Master mode and gets arbitration lost the bit of ARBLOIF UI2C_PROTSTS 11 will be set User may writing 1 to ARBLOIF UI2C_PROTSTS 11 and set PTRG STA STO AA 1 1 0 X to send START to re start Master operation when bus become free Otherwise user may writing 1 ...

Page 828: ...1 0 0 1 Writing 1 to ACKIF RXDAT Data PTRG STA STO AA 1 0 0 0 Writing 1 to ACKIF ACKIF 1 NACKIF 1 Arbitration Lost Master to Slave Slave to Master STORIF 1 ARBLOIF 1 Sr Sr Sr PTRG STA STO AA 1 0 0 1 Writing 1 to ACKIF Writing 1 to NACKIF Writing 1 to STORIF Switch to not addressed mode Own SLA will be recognized Become I2 C Slave STORIF 1 Sr TXDAT Data PTRG STA STO AA 1 0 0 X Writing 1 to ACKIF Wr...

Page 829: ...upt flag slave will not receive any I 2 C signal or address from master At this status I 2 C should be reset by setting FUNMODE UI2C_CTL 2 0 000b to leave this status General Call GC Mode If the GCFUNC bit UI2C_PROTCTL 0 is set the I 2 C port hardware will respond to General Call address 00H User can clear GC bit to disable general call function When the GC bit is set and the I 2 C in slave mode i...

Page 830: ...essed mode Own SLA will be recognized Become I2 C Slave Become I2 C Slave RXDAT SLA W 0x00 ARBLOIF 1 Arbitraion Lost Arbitraion Lost Master to Slave Master to Slave Slave to Master Slave to Master STORIF 1 Sr Sr Sr PTRG STA STO AA 1 0 0 X Writing 1 to ACKIF Writing 1 to ARBLOIF PTRG STA STO AA 1 0 0 X Writing 1 to ACKIF Writing 1 to ARBLOIF S ACK NAK ACK NAK P STARIF 1 Figure 6 22 16 GC Mode with ...

Page 831: ...e data register to see what was actually transmitted on the bus Loss of arbitration in Monitor mode In monitor mode the I 2 C module will not be able to respond to a request for information by the bus master or issue an ACK Some other slave on the bus will respond instead Software should be aware of the fact that the module is in monitor mode and should not respond to any loss of arbitration state...

Page 832: ...ion HTlimit UI2C_BRGEN 25 16 1 9 For example if user decide PCLK 12MHz and baud rate 100k the UI2C_BRGEN 25 16 must set 59 and the HTCTL 5 0 maximum value is 51 SCL SDA SDA delay over SCL low duty Bus error Figure 6 22 18 Hold Time Wrong Adjustment I 2 C Time out Function There is a time out counter TOCNT UI2C_PROTCTL 25 16 which can be used to deal with the I 2 C bus hang up If the time out count...

Page 833: ...he frequency of SCL is low speed and the system has wakeup from address match frame the user shall check this bit to confirm this frame has transaction done and then to do the wakeup procedure Note that user must clear WKIF after clearing the WKAKDONE bit to 0 The WRSTSWK UI2C_PROTSTS 17 bit records the Read Write command on the address match wake up frame The user can use read this bit s status t...

Page 834: ...PTRG STA STO AA 0 1 0 x Clear protocol status register ACKIF 1 TXDAT SLA W PTRG STA STO AA 1 0 0 x Write 1 to STARIF ACKIF 1 TXDAT Data PTRG STA STO AA 1 0 0 x Writing 1 to ACKIF STARIF 1 PTRG STA STO AA 1 1 0 x Clear protocol status register STORIF 1 PTRG STA STO AA 1 0 1 x Writing 1 to NACKIF TXDAT SLA W PTRG STA STO AA 1 0 0 x Write 1 to STARIF ACKIF 1 NAK NACKIF 1 TXDAT ROM Address Low Byte AC...

Page 835: ...DDR0 UI2Cx_BA 0x44 R W USCI Device Address Register 0 0x0000_0000 UI2C_DEVADDR1 UI2Cx_BA 0x48 R W USCI Device Address Register 1 0x0000_0000 UI2C_ADDRMSK0 UI2Cx_BA 0x4C R W USCI Device Address Mask Register 0 0x0000_0000 UI2C_ADDRMSK1 UI2Cx_BA 0x50 R W USCI Device Address Mask Register 1 0x0000_0000 UI2C_WKCTL UI2Cx_BA 0x54 R W USCI Wake up Control Register 0x0000_0000 UI2C_WKSTS UI2Cx_BA 0x58 R W...

Page 836: ...tion 31 3 Reserved Reserved 2 0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller Selecting a protocol that is not available or a reserved combination disables the USCI When switching between two protocols the USCI has to be disabled before selecting a new protocol Simultaneously the USCI will be reset when user write 000 to FUNMODE 000 The USCI is disabled All pro...

Page 837: ...he user can use revised CLKDIV and new BRDETITV UI2C_PROTCTL 24 16 to calculate the precise baud rate 15 Reserved Reserved 14 10 DSCNT Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK The divided frequency fDS_CNT fPDS_CNT DSCNT 1 Note The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled...

Page 838: ... 11 fSAMP_CLK fREF_CLK 1 PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock fPROT_CLK 0 Reference clock fREF_CLK 1 fREF_CLK2 its frequency is half of fREF_CLK 0 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock fREF_CLK 0 Peripheral device clock fPCLK 1 Reserved ...

Page 839: ...ion and transmission The data word is always right aligned in the data buffer USCI support word length from 4 to 16 bits 0x0 The data word contains 16 bits located at bit positions 15 0 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 The data word contains 4 bits located at bit positions 3 0 0x5 The data word contains 5 bits located at bit positions 4 0 0xF The data word contains 15 bits located at bit...

Page 840: ...scription Reset Value UI2C_TXDAT UI2Cx_BA 0x30 W USCI Transmit Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TXDAT 7 6 5 4 3 2 1 0 TXDAT Bits Description 31 16 Reserved Reserved 15 0 TXDAT Transmit Data Software can use this bit field to write 8 bit transmit data for transmission ...

Page 841: ... UI2C_RXDAT UI2Cx_BA 0x34 R USCI Receive Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXDAT 7 6 5 4 3 2 1 0 RXDAT Bits Description 31 16 Reserved Reserved 15 0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer Note1 In I2 C protocol only use RXDAT 7 0 ...

Page 842: ...8 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved DEVADDR 7 6 5 4 3 2 1 0 DEVADDR Bits Description 31 10 Reserved Reserved 9 0 DEVADDR Device Address In I2 C protocol this bit field contains the programmed slave address If the first received address byte is b1111 0AAX the AA bits are compared to the bits DEVADDR 9 8 to check for address match where the X is R W...

Page 843: ... 14 13 12 11 10 9 8 Reserved ADDRMSK 7 6 5 4 3 2 1 0 ADDRMSK Bits Description 31 10 Reserved Reserved 9 0 ADDRMSK USCI Device Address Mask 0 Mask Disabled the received corresponding register bit should be exact the same as address register 1 Mask Enabled the received corresponding address bit is don t care USCI support multiple address recognition with two address mask register When the bit in the...

Page 844: ...rol Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKADDREN WKEN Bits Description 31 2 Reserved Reserved 1 WKADDREN Wake up Address Match Enable Bit 0 The chip is woken up according data toggle 1 The chip is woken up according address match 0 WKEN Wake up Enable Bit 0 Wake up function Disabled 1 Wake up...

Page 845: ... Value UI2C_WKSTS UI2Cx_BA 0x58 R W USCI Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKF Bits Description 31 1 Reserved Reserved 0 WKF Wake up Flag When chip is woken up from Power down mode this bit is set to 1 Software can write 1 to clear this bit ...

Page 846: ...TOCNT bigger than 0 Note The TMCNTSRC UI2C_BRGEN 5 must be set zero on I2 C mode 15 10 Reserved Reserved 9 MONEN Monitor Mode Enable Bit This bit enables monitor mode In monitor mode the SDA output will be put in high impedance mode This prevents the I2 C module from outputting data of any kind including ACK onto the I2 C data bus 0 Monitor mode Disabled 1 Monitor mode Enabled Note Depending on th...

Page 847: ...ART or repeat START condition to bus when the bus is free 2 STO I2 C STOP Control In Master mode setting STO to transmit a STOP condition to bus then I2 C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically In a slave mode setting STO resets I2 C hardware to the defined not addressed slave mode when bus error UI2C_PROTSTS ERRIF 1...

Page 848: ...rotocol interrupt if an I2 C error condition is detected indicated by ERR UI2C_PROTSTS 16 0 The error interrupt Disabled 1 The error interrupt Enabled 4 ARBLOIEN Arbitration Lost Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an arbitration lost event is detected 0 The arbitration lost interrupt Disabled 1 The arbitration lost interrupt Enabled 3 NACKIEN Non Acknow...

Page 849: ...MANUAL 0 The start condition interrupt Disabled 1 The start condition interrupt Enabled 0 TOIEN Time out Interrupt Enable Bit In I2 C protocol this bit enables the interrupt generation in case of a time out event 0 The time out interrupt Disabled 1 The time out interrupt Enabled ...

Page 850: ... for transmission Note This bit has no interrupt signal and it will be cleared automatically by hardware 18 Reserved Reserved 17 WRSTSWK Read Write Status Bit in Address Wakeup Frame 0 Write command be record on the address match wakeup frame 1 Read command be record on the address match wakeup frame 16 WKAKDONE Wakeup Address Frame Acknowledge Bit Done 0 The ACK bit cycle of address match frame i...

Page 851: ...are writing 1 to it 10 NACKIF Non Acknowledge Received Interrupt Flag This bit indicates that a non acknowledge has been received in master mode A protocol interrupt can be generated if UI2C_PROTCTL NACKIEN 1 0 A non acknowledge has not been received 1 A non acknowledge has been received Note This bit is cleared by software writing 1 to it 9 STORIF Stop Condition Received Interrupt Flag This bit i...

Page 852: ... 852 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 0 A time out interrupt status has not occurred 1 A time out interrupt status has occurred Note This bit is cleared by software writing 1 to it 0 Reserved Reserved ...

Page 853: ...d 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ADMAT1 ADMAT0 Bits Description 31 2 Reserved Reserved 1 ADMAT1 USCI Address 1 Match Status When address 1 is matched hardware will inform which address used This bit will set to 1 and software can write 1 to clear this bit 0 ADMAT0 USCI Address 0 Match Status When address 0 is matched hardware will inform wh...

Page 854: ...ed 15 14 13 12 11 10 9 8 Reserved HTCTL 7 6 5 4 3 2 1 0 HTCTL STCTL Bits Description 31 8 Reserved Reserved 11 6 HTCTL Hold Time Configure Control This field is used to generate the delay timing between SCL falling edge SDA edge in transmission mode The delay hold time is numbers of peripheral clock HTCTL x fPCLK 5 0 STCTL Setup Time Configure Control This field is used to generate a delay timing ...

Page 855: ...ts nCTS incoming data Received Data FIFO reached threshold and RS 485 Address Match AAD mode wake up function Supports 8 bit receiver buffer time out detection function Programmable transmitting data delay time between the last stop and the next start bit by setting DLY UART_TOUT 15 8 Supports Auto Baud Rate measurement and baud rate compensation function Supports break error frame error parity er...

Page 856: ...CKEN CLK_APBCLK0 16 UART1CKEN CLK_APBCLK0 17 UART2CKEN CLK_APBCLK0 18 UART0_CLK UART1_CLK UART2_CLK Note Before clock switching both the pre selected and newly selected clock sources must be turned on and stable Figure 6 23 1 UART Clock Control Diagram UART_CLK IrDA Encode TX Shift Register TX_FIFO RX_FIFO RX Shift Register IrDA Decode Baud Out Baud Out Status Control Status Control Baud Rate Gene...

Page 857: ...rol register UART_FIFO FIFO status register UART_FIFOSTS and line control register UART_LINE for transmitter and receiver The time out register UART_TOUT identifies the condition of time out interrupt Auto Baud Rate Measurement This block is responsible for auto baud rate measurement Interrupt Control and Status Register There are ten types of interrupts Receive Data Available Interrupt RDAINT Tra...

Page 858: ...ect the source of UART0 peripheral clock on UARTSEL CLK_CLKSEL1 25 24 Select the clock divider number of UART0 peripheral clock on UARTDIV CLK_CLKDIV0 11 8 Enable UART0 peripheral clock in UART0CKEN CLK_APBCLK0 16 Reset Configuration Reset UART0 controller in UART0RST SYS_IPRST1 16 Pin Configuration Group Pin Name GPIO MFP UART0 UART0_RXD PA 3 MFP2 PD 0 PD 6 PD 9 PD 13 PE 6 MFP3 UART0_TXD PA 2 MFP...

Page 859: ...11 PE 11 MFP3 PB 8 PE 2 MFP4 6 23 4 3 Basic Configurations of UART2 Clock Source Configuration Select the source of UART2 peripheral clock on UARTSEL CLK_CLKSEL1 25 24 Select the clock divider number of UART2 peripheral clock on UARTDIV CLK_CLKDIV0 11 8 Enable UART2 peripheral clock in UART2CKEN CLK_APBCLK0 18 Reset Configuration Reset UART2 controller in UART2RST SYS_IPRST1 18 Pin Configuration G...

Page 860: ...de 0 is set by UART_BAUD 29 28 with 00 Mode 1 is set by UART_BAUD 29 28 with 10 Mode 2 is set by UART_BAUD 29 28 with 11 Mode BAUDM1 BAUDM0 Baud Rate Equation Mode 0 0 0 UART_CLK 16 BRD 2 Mode 1 1 0 UART_CLK EDIVM1 1 BRD 2 EDIVM1 must 8 Mode 2 1 1 UART_CLK BRD 2 If UART_CLK 3 HCLK BRD must 9 If UART_CLK 3 HCLK BRD must 3 N 1 N is the smallest integer larger than or equal to the ratio of UART_CLK H...

Page 861: ...x2800_00FE 0x2B00_00BE 0x2F00_008E 0x3000_08FE 4800 0x0000_011E 0x2800_01FE 0x2B00_017E 0x2F00_011E 0x3000_11FE Table 6 23 5 UART Controller Baud Rate Register Setting Example Table 6 23 5 2 UART Controller Baud Rate Compensation The UART controller supports baud rate compensation function It is used to optimize the precision in each bit The precision of the compensation is half of UART module clo...

Page 862: ...DAT 7 0 717 0 304 0 413 1 0 283 9 Parity 0 130 0 283 0 413 0 0 13 Table 6 23 6 Baud Rate Compensation Example Table 1 the BRCOMP UART_BRCOMP 8 0 can be set as 9 b010100101 0xa5 2 UART s peripheral clock 32 768K and baud rate is 4800 Baud rate is 4800 UART peripheral clock is 32 768K 6 827 peripheral clock bit If the baud divider is set 5 7 peripheral clock bit the inaccuracy of each bit is 0 173 p...

Page 863: ...ABRDBITS UART_ALTCTL 20 19 is loaded to BRD UART_BAUD 15 0 automatically ABRDEN UART_ALTCTL 18 is cleared Once the auto baud rate measurement is finished the ABRDIF UART_FIFOSTS 1 is set When auto baud rate counter is overflow ABRDTOIF UART_FIFOSTS 2 is set ABRDIF UART_FIFOSTS 1 or ABRDTOIF UART_FIFOSTS 2 cause the auto baud rate flag ABRIF UART_ALTCTL 17 is generated If the ABRIEN UART_INTEN 18 i...

Page 864: ...FIFO control and status function 6 23 5 6 UART Controller Wake up Function The UART controller supports wake up system function The wake up function includes nCTS pin incoming data wake up Received Data FIFO reached threshold wake up RS 485 Address Match AAD mode wake up and Received Data FIFO threshold time out wake up function CTSWKF UART_WKSTS 0 DATWKF UART_WKSTS 1 RFRTWKF UART_WKSTS 2 RS485WKF...

Page 865: ...Note1 The UART controller clock source should be selected as HIRC and the compensation time for start bit is about 35us It means that the value of STCOMP UART_DWKCOMP 15 0 can be set as 774 Note2 The value of BRD UART_BAUD 15 0 should be greater than STCOMP UART_DWKCOMP 15 0 Power down mode UART_CLK UART_RXD DATWKF UART_CLK stable count CPU run start HCLK stable count Note1 Stable count means HCLK...

Page 866: ...tch AAD mode wake up flag RS485WKF UART_WKSTS 3 is generated Note The UART controller clock source should be selected as LXT in Power down mode to receive data HCLK Start D0 D7 ADD Address Match Power down mode RS485WKF UART_RXD STO stable count Note Stable count means HCLK source recovery stable count Figure 6 23 9 UART RS 485 AAD Mode Address Match Wake up Received Data FIFO threshold time out w...

Page 867: ...Error Flag FEF Parity Error Flag PEF RS 485 Address Byte Detect Flag ADDRDETF MODEM Status Interrupt MODEMINT Detect nCTS State Change Flag CTSDETF Receiver Buffer Time out Interrupt RXTOINT Buffer Error Interrupt BUFERRINT TX Overflow Error Interrupt Flag TXOVIF RX Overflow Error Interrupt Flag RXOVIF LIN Bus Interrupt LININT LIN Break Detection Flag BRKDETF Bit Error Detect Status Flag BITEF LIN...

Page 868: ... TXENDIF N A Write UART_DAT Receive Line Status Interrupt RLSINT RLSIEN RLSIF RLSIF BIF Write 1 to BIF RLSIF FEF Write 1 to FEF RLSIF PEF Write 1 to PEF RLSIF ADDRDETF Write 1 to ADDRDETF Modem Status Interrupt MODEMINT MODEMIEN MODEMIF MODEMIF CTSDETF Write 1 to CTSDETF Receiver Buffer Time out Interrupt RXTOINT RXTOIEN RXTOIF N A Read UART_DAT Buffer Error Interrupt BUFERRINT BUFERRIEN BUFERRIF ...

Page 869: ...buffer time out detection for receiver The transmitting data delay time between the last stop and the next start bit can be programed by setting DLY UART_TOUT 15 8 register The UART supports hardware auto flow control that provides programmable nRTS flow control trigger level The number of data bytes in RX FIFO is equal to or greater than RTSTRGLV UART_FIFO 19 16 the nRTS is de asserted UART Line ...

Page 870: ...rced Space Parity 1 1 0 1 Parity bit always logic 0 Parity bit on the serial byte is set to 0 regardless of total number of 1 s even or odd counts Table 6 23 10 UART Line Control of Parity Bit Setting UART Auto Flow Control Function The UART supports auto flow control function that uses two signals nCTS clear to send and nRTS request to send to control the flow of data transfer between the UART an...

Page 871: ...12 UART nCTS Auto Flow Control Enabled As shown in Figure 6 23 13 in UART nRTS auto flow control mode ATORTSEN UART_INTEN 12 1 the nRTS internal signal is controlled by UART FIFO controller with RTSTRGLV UART_FIFO 19 16 trigger level Setting RTSACTLV UART_MODEM 9 can control the nRTS pin output is inverse or non inverse from nRTS signal User can read the RTSSTS UART_MODEM 13 bit to get real nRTS p...

Page 872: ...pecification defines a short range infrared asynchronous serial transmission mode with one start bit 8 data bits and 1 stop bit The maximum data rate is 115 2 kbps The IrDA SIR block contains an IrDA SIR protocol encoder decoder The IrDA SIR protocol is half duplex only So it cannot transmit and receive data at the same time The IrDA SIR physical layer specifies a minimum 10 ms transfer delay betw...

Page 873: ...3 16 is IrDA encoder decoder waveform SOUT from UART TX IR_ SOUT encoder output IR_SIN decorder input SIN to UART RX 0 0 1 0 1 1 1 0 0 1 1 1 Bit cycle width 3 16 bit width STOP BIT START BIT IrDA TX Timing IrDA RX Timing 0 1 0 0 1 0 1 0 0 START BIT STOP BIT 3 16 bit width 1 Figure 6 23 16 IrDA TX RX Timing Diagram 6 23 5 10LIN Function Mode Local Interconnection Network The UART Controller support...

Page 874: ...o select LIN function mode operation A complete header consists of a break field and sync field followed by a frame identifier frame ID The UART controller can be selected header sending by three header selected modes The header selected mode can be break field or break field and sync field or break field sync field and frame ID field by setting HSEL UART_LINCTL 23 22 If the selected header is bre...

Page 875: ...limiter length Note2 The default setting of break sync delimiter length is 1 bit time and the inter byte spaces default setting is also 1 bit time Setting BSL UART_LINCTL 21 20 and DLY UART_TOUT 15 8 can change break sync delimiter length and inter byte spaces Note3 If the header includes the break field sync field and frame ID field software must fill frame ID to PID UART_LINCTL 31 24 before trig...

Page 876: ...be 0 Delimiter BRKDETF 1 2 3 4 5 6 7 8 9 10 11 Case 1 Break signal is not long enough to ignore this break signal and BRKDETF UART_LINSTS 8 is not set BRKDETF Figure 6 23 19 Break Detection in LIN Mode LIN Frame ID and Parity Format The LIN frame ID value in LIN function mode is shown the frame ID parity can be generated by software or hardware depends on IDPEN UART_LINCTL 9 If the parity generate...

Page 877: ...e by filling data to the UART_DAT register If the slave node is the subscriber of the response the slave node receives data from LIN bus LIN Header Time out Error The LIN slave controller contains a header time out counter If the entire header is not received within the maximum time limit of 57 bit times the header error flag SLVHEF UART_LINSTS 1 will be set The time out counter is enabled at each...

Page 878: ...n is enabled after each LIN break field the time duration between five falling edges is sampled on peripheral clock and the result of this measurement is stored in an internal 13 bit register and the UART_BAUD register value will be automatically updated at the end of the fifth falling edge If the measure timer 13 bit overflows before five falling edges then the header error flag SLVHEF UART_LINST...

Page 879: ...reload initial baud Rate which back up in TEMP_REG and cleared SLVDUEN to 0 by H W UART_BAUD UART_BAUD UART_BAUD update UART UART TEMP_REG value is UART_BAUD n BAUD_LIN value is UART_BAUD m Figure 6 23 22 UART_BAUD Update Sequence in AR Mode if SLVDUEN is 1 Data1 Data2 Data N Check Sum Protected Identifier field Response Inter frame space Frame slot Synch field Break Field Measurement time n m _ B...

Page 880: ...interrupt is generated if the LINIEN UART_INTEN 8 bit is set When header error is detected user must reset the detect circuit to re search a new frame header by writing 1 to SLVSYNCF UART_LINSTS 3 to re search a new frame header The LIN header error flag SLVHEF UART_LINSTS 1 is set if one of the following conditions occurs Break Delimiter is too short less than 0 5 bit time Frame error in sync fie...

Page 881: ... data until an address byte is detected bit 9 1 and the address byte data matches the ADDRMV UART_ALTCTL 31 24 value The address byte data will be stored in the RX FIFO The all received byte data will be accepted and stored in the RX FIFO until an address byte data not match the ADDRMV UART_ALTCTL 31 24 value RS 485 Auto Direction Function AUD Another option function of RS 485 controllers is RS 48...

Page 882: ...are control only Figure 6 23 25 RS 485 nRTS Driving Level with Software Control Programming Sequence Example 1 Program FUNCSEL in UART_FUNCSEL to select RS 485 function 2 Program the RXOFF UART_FIFO 8 to determine enable or disable the receiver RS 485 receiver 3 Program the RS485NMM UART_ALTCTL 8 or RS485AAD UART_ALTCTL 9 mode 4 If the RS485AAD UART_ALTCTL 9 mode is selected the ADDRMV UART_ALTCTL...

Page 883: ... PDMA transmission process automatically By configuring PDMA parameter and set UART_DAT as the PDMA source address When RXPDMAEN UART_INTEN 15 is set to 1 the controller will start the PDMA reception process UART controller will issue request to PDMA controller automatically when there is data in the RX FIFO buffer Note If STOPn PDMA_STOP n is set to stop UART RXPDMA task and the UART receive is n...

Page 884: ... Modem Control Register 0x0000_0200 UART_MODEM STS UARTx_BA 0x14 R W UART Modem Status Register 0x0000_0110 UART_FIFOST S UARTx_BA 0x18 R W UART FIFO Status Register 0xB040_4000 UART_INTSTS UARTx_BA 0x1C R W UART Interrupt Status Register 0x0040_0002 UART_TOUT UARTx_BA 0x20 R W UART Time out Register 0x0000_0000 UART_BAUD UARTx_BA 0x24 R W UART Baud Rate Divider Register 0x0F00_0000 UART_IRDA UART...

Page 885: ...UARTx_BA 0x3C R W UART Baud Rate Compensation Register 0x0000_0000 UART_WKCTL UARTx_BA 0x40 R W UART Wake up Control Register 0x0000_0000 UART_WKSTS UARTx_BA 0x44 R W UART Wake up Status Register 0x0000_0000 UART_DWKCO MP UARTx_BA 0x48 R W UART Imcoming Data Wake up Compensation Register 0x0000_0000 ...

Page 886: ...he parity bit will be stored in transmitter FIFO If PBE UART_LINE 3 and PSS UART_LINE 7 are set the UART controller will send out this bit follow the DAT UART_DAT 7 0 through the UART_TXD Read Operation If PBE UART_LINE 3 and PSS UART_LINE 7 are enabled the parity bit can be read by this bit Note This bit has effect only when PBE UART_LINE 3 and PSS UART_LINE 7 are set 7 0 DAT Data Receive Transmi...

Page 887: ...transmitted 0 Transmitter empty interrupt Disabled 1 Transmitter empty interrupt Enabled 21 19 Reserved Reserved 18 ABRIEN Auto baud Rate Interrupt Enable Bit 0 Auto baud rate interrupt Disabled 1 Auto baud rate interrupt Enabled 17 16 Reserved Reserved 15 RXPDMAEN RX PDMA Enable Bit This bit can enable or disable RX PDMA service 0 RX PDMA Disabled 1 RX PDMA Enabled Note If RLSIEN UART_INTEN 2 is ...

Page 888: ...s interrupt Disabled 1 LIN bus interrupt Enabled Note This bit is used for LIN function mode 7 Reserved Reserved 6 WKIEN Wake up Interrupt Enable Bit 0 Wake up Interrupt Disabled 1 Wake up Interrupt Enabled 5 BUFERRIEN Buffer Error Interrupt Enable Bit 0 Buffer error interrupt Disabled 1 Buffer error interrupt Enabled 4 RXTOIEN RX Time out Interrupt Enable Bit 0 RX time out interrupt Disabled 1 RX...

Page 889: ...is field is used for auto nRTS flow control 15 9 Reserved Reserved 8 RXOFF Receiver Disable Bit The receiver is disabled or not set 1 to disable receiver 0 Receiver Enabled 1 Receiver Disabled Note This bit is used for RS 485 Normal Multi drop mode It should be programmed before RS485NMM UART_ALTCTL 8 is programmed 7 4 RFITL RX FIFO Interrupt Trigger Level When the number of bytes in the receive F...

Page 890: ...Before setting this bit it should wait for the TXEMPTYF UART_FIFOSTS 28 be set 1 RXRST RX Field Software Reset When RXRST UART_FIFO 1 is set all the byte in the receiver FIFO and RX internal state machine are cleared 0 No effect 1 Reset the RX internal state machine and pointers Note1 This bit will automatically clear at least 3 UART peripheral clock cycles Note2 Before setting this bit it should ...

Page 891: ...ignal inverted Disabled 1 Transmitted data signal inverted Enabled Note1 Before setting this bit TXRXDIS UART_FUNCSEL 3 should be set then waited for TXRXACT UART_FIFOSTS 31 is cleared When the configuration is done cleared TXRXDIS UART_FUNCSEL 3 to activate UART controller Note2 This bit is valid when FUNCSEL UART_FUNCSEL 1 0 is select UART LIN or RS485 function 7 PSS Parity Bit Source Selection ...

Page 892: ... of logic 1 s is transmitted and checked in each word 1 Even number of logic 1 s is transmitted and checked in each word Note This bit has effect only when PBE UART_LINE 3 is set 3 PBE Parity Bit Enable Bit 0 Parity bit generated Disabled 1 Parity bit generated Enabled Note Parity bit is generated on each outgoing character and is checked on each incoming data 2 NSB Number of STOP Bit 0 One STOP b...

Page 893: ...TS pin output 0 nRTS pin output is high level active 1 nRTS pin output is low level active Default Note1 Refer to Figure 6 23 13 and Figure 6 23 14 for UART function mode Note2 Refer to Figure 6 23 24 and Figure 6 23 25 for RS 485 function mode Note3 Before setting this bit TXRXDIS UART_FUNCSEL 3 should be set then waited for TXRXACT UART_FIFOSTS 31 is cleared When the configuration is done cleare...

Page 894: ...ing this bit TXRXDIS UART_FUNCSEL 3 should be set then waited for TXRXACT UART_FIFOSTS 31 is cleared When the configuration is done cleared TXRXDIS UART_FUNCSEL 3 to activate UART controller 7 5 Reserved Reserved 4 CTSSTS nCTS Pin Status Read Only This bit mirror from nCTS pin input of voltage logic status 0 nCTS pin input is low level voltage logic state 1 nCTS pin input is high level voltage log...

Page 895: ... transmit or receive data at this moment Otherwise this bit is set 30 Reserved Reserved 29 RXIDLE RX Idle Status Read Only This bit is set by hardware when RX is idle 0 RX is busy 1 RX is idle Default 28 TXEMPTYF Transmitter Empty Flag Read Only This bit is set by hardware when TX FIFO UART_DAT is empty and the STOP bit of the last byte has been transmitted 0 TX FIFO is not empty or the STOP bit o...

Page 896: ...sage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware 14 RXEMPTY Receiver FIFO Empty Read Only This bit initiate RX FIFO empty or not 0 RX FIFO is not empty 1 RX FIFO is empty Note When the last byte of RX FIFO has been read by CPU hardware sets this bit high It will be cleared when UART receives any new data 13 8 RXPTR RX FIFO Pointer Read Only This field indicates the RX FIFO...

Page 897: ...can be cleared by writing 1 to it 2 ABRDTOIF Auto baud Rate Detect Time out Interrupt Flag This bit is set to logic 1 in Auto baud Rate Detect mode when the baud rate counter is overflow 0 Auto baud rate counter is underflow 1 Auto baud rate counter is overflow Note This bit can be cleared by writing 1 to it 1 ABRDIF Auto baud Rate Detect Interrupt Flag This bit is set to logic 1 when auto baud ra...

Page 898: ...it is set if TXENDIEN UART_INTEN 22 and TXENDIF UART_INTSTS 22 are both set to 1 0 No Transmitter Empty interrupt is generated 1 Transmitter Empty interrupt is generated 29 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator Read Only This bit is set if BUFERRIEN UART_INTEN 5 and HWBUFEIF UART_INTSTS 21 are both set to 1 0 No buffer error interrupt is generated in PDMA mode 1 Buffer error interru...

Page 899: ...INTEN 4 is enabled the RX time out interrupt will be generated 0 No RX time out interrupt flag is generated in PDMA mode 1 RX time out interrupt flag is generated in PDMA mode Note This bit is read only and user can read UART_DAT RX is in active to clear it 19 HWMODIF PDMA Mode MODEM Interrupt Flag Read Only This bit is set when the nCTS pin has state change CTSDETF UART_MODEMSTS 0 1 If MODEMIEN U...

Page 900: ...INT Receive Line Status Interrupt Indicator Read Only This bit is set if RLSIEN UART_INTEN 2 and RLSIF UART_INTSTS 2 are both set to 1 0 No RLS interrupt is generated 1 RLS interrupt is generated 9 THREINT Transmit Holding Register Empty Interrupt Indicator Read Only This bit is set if THREIEN UART_INTEN 1 and THREIF UART_INTSTS 1 are both set to 1 0 No THRE interrupt is generated 1 THRE interrupt...

Page 901: ...errupt flag is generated Note This bit is read only and user can read UART_DAT RX is in active to clear it 3 MODEMIF MODEM Interrupt Flag Read Only This bit is set when the nCTS pin has state change CTSDETF UART_MODEMSTS 0 1 If MODEMIEN UART_INTEN 3 is enabled the Modem interrupt will be generated 0 No Modem interrupt flag is generated 1 Modem interrupt flag is generated Note This bit is read only...

Page 902: ...eceive Data Available Interrupt Flag Read Only When the number of bytes in the RX FIFO equals the RFITL then the RDAIF UART_INTSTS 0 will be set If RDAIEN UART_INTEN 0 is enabled the RDA interrupt will be generated 0 No RDA interrupt flag is generated 1 RDA interrupt flag is generated Note This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the thres...

Page 903: ...out counter resets and starts counting the counting clock baud rate whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN UART_INTEN 11 Once the content of time out counter is equal to that of time out interrupt comparator TOIC UART_TOUT 7 0 a receiver time out interrupt RXTOINT UART_INTSTS 12 is generated if RXTOIEN UART_INTEN 4 enabled A new incoming dat...

Page 904: ...o select baud rate calculation mode The detail description is shown in Table 6 23 3 Note In IrDA mode must be operated in mode 0 28 BAUDM0 BAUD Rate Mode Selection Bit 0 This bit is baud rate mode selection bit 0 UART provides three baud rate calculation modes This bit combines with BAUDM1 UART_BAUD 29 to select baud rate calculation mode The detail description is shown in Table 6 23 3 27 24 EDIVM...

Page 905: ...nfiguration is done cleared TXRXDIS UART_FUNCSEL 3 to activate UART controller Note2 This bit is valid when FUNCSEL UART_FUNCSEL 1 0 is select IrDA function 5 TXINV IrDA Inverse Transmitting Output Signal 0 None inverse transmitting signal Default 1 Inverse transmitting output signal Note1 Before setting this bit TXRXDIS UART_FUNCSEL 3 should be set then waited for TXRXACT UART_FIFOSTS 31 is clear...

Page 906: ...2 10 4 bit time from Start bit to the 1st rising edge The input pattern shall be 0x08 11 8 bit time from Start bit to the 1st rising edge The input pattern shall be 0x80 Note The calculation of bit number includes the START bit 18 ABRDEN Auto baud Rate Detect Enable Bit 0 Auto baud rate detect function Disabled 1 Auto baud rate detect function Enabled Note This bit is cleared automatically after a...

Page 907: ... Note It cannot be active with RS 485_NMM operation mode 8 RS485NMM RS 485 Normal Multi drop Operation Mode NMM 0 RS 485 Normal Multi drop Operation mode NMM Disabled 1 RS 485 Normal Multi drop Operation mode NMM Enabled Note It cannot be active with RS 485_AAD operation mode 7 LINTXEN LIN TX Break Mode Enable Bit 0 LIN TX Break mode Disabled 1 LIN TX Break mode Enabled Note When TX break field tr...

Page 908: ... 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TXRXDIS Reserved FUNCSEL Bits Description 31 4 Reserved Reserved 3 TXRXDIS TX and RX Disable Bit Setting this bit can disable TX and RX 0 TX and RX Enabled 1 TX and RX Disabled Note The TX and RX will not disable immediately when this bit is set The TX and RX compelet current task before disable TX and RX When TX and RX disable the TXRXACT UART_FIFOSTS 31 ...

Page 909: ...Note2 This field can be used for LIN master mode or slave mode 23 22 HSEL LIN Header Select 00 The LIN header includes break field 01 The LIN header includes break field and sync field 10 The LIN header includes break field sync field and frame ID field 11 Reserved Note This bit is used to master mode for LIN to send header field SENDH UART_LINCTL 8 1 or used to slave to indicates exit from mute m...

Page 910: ...SEL UART_LINCTL 23 22 10 or be used for enable LIN slave received frame ID parity checked Note2 This bit is only used when the operation header transmitter is in HSEL UART_LINCTL 23 22 10 8 SENDH LIN TX Send Header Enable Bit The LIN TX header can be break field or break and sync field or break sync and frame ID field it is depend on setting HSEL UART_LINCTL 23 22 0 Send LIN TX header Disabled 1 S...

Page 911: ...ion mode the baud rate setting must be mode2 BAUDM1 UART_BAUD 29 and BAUDM0 UART_BAUD 28 must be 1 Note3 The control and interactions of this field are explained in 6 23 5 10 Slave mode with automatic resynchronization 1 SLVHDEN LIN Slave Header Detection Enable Bit 0 LIN slave header detection Disabled 1 LIN slave header detection Enabled Note1 This bit only valid when in LIN slave mode SLVEN UAR...

Page 912: ...1 to it Note2 This bit is only valid when enable bit error detection function BITERREN UART_LINCTL 12 1 8 BRKDETF LIN Break Detection Flag This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software 0 LIN break not detected 1 LIN break detected Note1 This bit can be cleared by writing 1 to it Note2 This bit is only valid when LIN break detection function...

Page 913: ...ield deviation error with Automatic Resynchronization mode sync field measure time out with Automatic Resynchronization mode and LIN header reception time out 0 LIN header error not detected 1 LIN header error detected Note1 This bit can be cleared by writing 1 to it Note2 This bit is only valid when UART is operated in LIN slave mode SLVEN UART_LINCTL 0 1 and enables LIN slave header detection fu...

Page 914: ...6 Reserved 15 14 13 12 11 10 9 8 Reserved BRCOMP 7 6 5 4 3 2 1 0 BRCOMP Bits Description 31 BRCOMPDEC Baud Rate Compensation Decrease 0 Positive increase one module clock compensation for each compensated bit 1 Negative decrease one module clock compensation for each compensated bit 30 9 Reserved Reserved 8 0 BRCOMP Baud Rate Compensation Patten These 9 bits are used to define the relative bit is ...

Page 915: ...p Enable Bit 0 RS 485 Address Match AAD mode wake up system function Disabled 1 RS 485 Address Match AAD mode wake up system function Enabled when the system is in Power down mode RS 485 Address Match will wake up system from Power down mode Note This bit is used for RS 485 Auto Address Detection AAD mode in RS 485 function mode and ADDRDEN UART_ALTCTL 15 is set to 1 2 WKRFRTEN Received Data FIFO ...

Page 916: ...e this bit is set to 1 Note2 This bit can be cleared by writing 1 to it 3 RS485WKF RS 485 Address Match AAD Mode Wake up Flag This bit is set if chip wake up from power down state by RS 485 Address Match AAD mode 0 Chip stays in power down state 1 Chip wake up from power down state by RS 485 Address Match AAD mode wake up Note1 If WKRS485EN UART_WKCTL 3 is enabled the RS 485 Address Match AAD mode...

Page 917: ...d the Incoming Data wake up cause this bit is set to 1 Note2 This bit can be cleared by writing 1 to it 0 CTSWKF nCTS Wake up Flag This bit is set if chip wake up from power down state by nCTS wake up 0 Chip stays in power down state 1 Chip wake up from power down state by nCTS wake up Note1 If WKCTSEN UART_WKCTL 0 is enabled the nCTS wake up cause this bit is set to 1 Note2 This bit can be cleare...

Page 918: ...pensation Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 STCOMP 7 6 5 4 3 2 1 0 STCOMP Bits Description 31 16 Reserved Reserved 15 0 STCOMP Start Bit Compensation Value These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit start bit when the device is wake up from power down mode ...

Page 919: ...reset state about 63 WDT_CLK period time after system reset event occurred Supports to force WDT function enabled after chip powered on or reset by setting CWDTEN 2 0 in Config0 register Supports WDT time out wake up function only if WDT clock source is selected as LIRC or LXT 6 24 3 Block Diagram 0 15 3 16 17 RSTCNT WDT_RSTCNT 31 0 Write 0x00005AA5 to reset counter Time Out Interval Period Select...

Page 920: ...set system function and system will be reset after IF WDT_CTL 3 is generated and WDT counter is not reset before TRSTD reset delay period expired User can program 0x00005AA5 in WDT_RSTCNT register to reset the 18 bit WDT up counter value to avoid generate WDT time out reset system signal Moreover user can set RSTDSEL WDT_ALTCTL 1 0 to select reset delay period for adjusting delay period after IF o...

Page 921: ...et Period 63 TWDT WDT_CLK IF 1 RSTF 1 if RSTEN 1 IF RSTF Figure 6 24 3 Watchdog Timer Time out Interval and Reset Period Timing WDT Wake up If WDT clock source is selected to LIRC 10 kHz or LXT 32 kHz system can be waken up from Power down mode while WDT time out interrupt signal is generated and both INTEN WDT_CTL 6 and WKEN WDT_CTL 4 are enabled In the meanwhile the WKF WDT_CTL 5 will set to 1 a...

Page 922: ...only W write only R W both read and write Register Offset R W Description Reset Value WDT Base Address WDT_BA 0x4000_4000 WDT_CTL WDT_BA 0x00 R W WDT Control Register 0x0000_0700 WDT_ALTCTL WDT_BA 0x04 R W WDT Alternative Control Register 0x0000_0000 WDT_RSTCNT WDT_BA 0x08 W WDT Reset Counter Register 0x0000_0000 ...

Page 923: ...nter will keep going no matter CPU is held by ICE or not Note This bit is write protected Refer to the SYS_REGLCTL register 30 SYNC WDT Enable Control SYNC Flag Indicator Read Only If user execute enable disable WDTEN WDT_CTL 7 this flag can be indicated enable disable WDTEN function is completed or not 0 Set WDTEN bit is completed 1 Set WDTEN bit is synchronizing and not become active yet Note Pe...

Page 924: ...1 while WDT time out interrupt flag IF WDT_CTL 3 is generated and interrupt enable bit INTEN WDT_CTL 6 is enabled the WDT time out interrupt signal will generate a event to trigger CPU wake up 0 Trigger wake up event function Disabled if WDT time out interrupt signal generated 1 Trigger wake up event function Enabled if WDT time out interrupt signal generated Note1 This bit is write protected Refe...

Page 925: ...d Reserved 1 0 RSTDSEL WDT Reset Delay Period Selection Write Protect When WDT time out event happened user has a time named WDT Reset Delay Period to execute WDT counter reset to prevent WDT time out reset system occurred User can select a suitable setting of RSTDSEL for application program 00 WDT Reset Delay Period is 1026 WDT_CLK 01 WDT Reset Delay Period is 130 WDT_CLK 10 WDT Reset Delay Perio...

Page 926: ...BA 0x08 W WDT Reset Counter Register 0x0000_0000 31 30 29 28 27 26 25 24 RSTCNT 23 22 21 20 19 18 17 16 RSTCNT 15 14 13 12 11 10 9 8 RSTCNT 7 6 5 4 3 2 1 0 RSTCNT Bits Description 31 0 RSTCNT WDT Reset Counter Register Writing 0x00005AA5 to this field will reset the internal 18 bit WDT up counter value to 0 Note Perform RSTCNT to reset counter needs 2 WDT_CLK period to become active ...

Page 927: ...WWDT compare time out window period flexible Supports PSCSEL WWDT_CTL 11 8 to programmable maximum 11 bit prescale counter period of WWDT counter WWDT counter suspends in Idle Power down mode WWDT counter only can be reloaded within in valid window period to prevent system reset 6 25 3 Block Diagram 6 bit down counter 11 bit Prescale 6 bit compare value CMPDAT WWDT_CTL 21 16 WWDT_CLK 0x3F comparat...

Page 928: ...ce of WWDT counter is based on system clock divide 2048 PCLK 2048 or 10 kHz internal low speed RC oscillator LIRC with programmable maximum 11 bit prescale which controlled by PSCSEL WWDT_CTL 11 8 Also the maximum WWDT counter compare time out period and the correlate of PSCSEL WWDT_CTL 11 8 and prescale value are listed in Table 6 25 1 PSCSEL Prescale Value Max Time Out Period Max Time Out Interv...

Page 929: ...WDT counter compare match interrupt WWDTIF WWDT_STATUS 0 will be generated and it can be cleared by writing 1 Figure 6 17 13 shows an example of WWDT compare match interrupt when PSCSEL WWDT_CTL 11 8 is 0x2 and prescale value is 4 WWDT_CLK WWDTIF WWDT_STATUS 0 CMPDAT WWDT_CTL 21 16 0x3E CNTDAT WWDT_CNT 5 0 0x3F 0x3E 0x3D 0x3C 0x3B x Prescale counter 3 1 0 3 2 1 0 3 2 1 0 2 3 2 1 0 3 2 1 WWDTEN WWD...

Page 930: ...ounter value to 0x3F it needs WWDT_CLK 3 period to sync the reload command to actually perform reload action Note that if user sets PSCSEL WWDT_CTL 11 8 to 0x0 the counter prescale value should be as 1 and the CMPDAT WWDT_CTL 21 16 must be larger than 2 Otherwise when WWDTIF WWDT_STATUS 0 is generated writing WWDT_RLDCNT register to reload WWDT counter value to 0x3F is unavailable and WWDT reset s...

Page 931: ...nd write Register Offset R W Description Reset Value WWDT Base Address WWDT_BA 0x4000_4100 WWDT_RLDC NT WWDT_BA 0x00 W WWDT Reload Counter Register 0x0000_0000 WWDT_CTL WWDT_BA 0x04 R W WWDT Control Register 0x003F_0800 WWDT_STAT US WWDT_BA 0x08 R W WWDT Status Register 0x0000_0000 WWDT_CNT WWDT_BA 0x0C R WWDT Counter Value Register 0x0000_003F ...

Page 932: ... RLDCNT Bits Description 31 0 RLDCNT WWDT Reload Counter Register Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F Note1 User can only execute the reload WWDT counter value command when current CNTDAT WWDT_CNT 5 0 is between 1 and CMPDAT WWDT_CTL 21 16 If user writes 0x00005AA5 in WWDT_RLDCNT register when current CNTDAT is larger than CMPDAT WWDT reset system ev...

Page 933: ... WWDTIF WWDT_STATUS 0 is generated Note User can only write WWDT_RLDCNT register to reload WWDT counter value when current CNTDAT WWDT_CNT 5 0 is between 1 and CMPDAT If user writes 0x00005AA5 in WWDT_RLDCNT register when current CNTDAT is larger than CMPDAT WWDT reset system event will be generated immediately 15 12 Reserved Reserved 11 8 PSCSEL WWDT Counter Prescale Period Selection 0000 Pre sca...

Page 934: ...Pre scale is 2048 Max time out period is 2048 64 WWDT_CLK 7 2 Reserved Reserved 1 INTEN WWDT Interrupt Enable Bit If this bit is enabled when WWDTIF WWDT_STATUS 0 is set to 1 the WWDT counter compare match interrupt signal is generated and inform to CPU 0 WWDT counter compare match interrupt disabled 1 WWDT counter compare match interrupt enabled 0 WWDTEN WWDT Enable Bit Set this bit to start WWDT...

Page 935: ...F WWDTIF Bits Description 31 2 Reserved Reserved 1 WWDTRF WWDT Timer out Reset System Flag If this bit is set to 1 it indicates that system has been reset by WWDT counter time out reset system event 0 WWDT time out reset system event did not occur 1 WWDT time out reset system event occurred Note This bit is cleared by writing 1 to it 0 WWDTIF WWDT Compare Match Interrupt Flag This bit indicates th...

Page 936: ...Offset R W Description Reset Value WWDT_CNT WWDT_BA 0x0C R WWDT Counter Value Register 0x0000_003F 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CNTDAT Bits Description 31 6 Reserved Reserved 5 0 CNTDAT WWDT Counter Value CNTDAT will be updated continuously ...

Page 937: ...D TXD DVCC Smart Card Slot SC_PWR SC_RST SC_CLK SC_DAT SC_ Detect DVCC 10uF 10V 10K nRST 4 24 MHz crystal 20p 20p XT1_OUT XT1_IN VDD VSS I2 CLK DIO I2C_SDA I2C_SCL 4 7K DVCC 4 7K DVCC VDDIO VBAT VDD VSS nRESET ICE_DAT ICE_CLK SWD Interface VREF 32 768kHz crystal 20p 20p X32_OUT X32_IN LDO CAP _ 1uF Reset Circuit VDD VSS SPI Device CS CLK MISO SPI_SS MOSI SPI_CLK SPI_MISO SPI_MOSI DVCC USB OTG Slot...

Page 938: ...NUC126 Aug 08 2018 Page 938 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 8 PACKAGE DIMENSIONS 8 1 LQFP 100L 14x14x1 4 mm footprint 2 0 mm ...

Page 939: ...NUC126 Aug 08 2018 Page 939 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 8 2 LQFP 64L 7x7x1 4 mm footprint 2 0 mm ...

Page 940: ... 0 039 0 030 0 024 0 018 9 10 9 00 8 90 0 358 0 354 0 350 0 50 0 20 0 25 1 45 1 40 0 10 0 15 1 35 0 008 0 010 0 057 0 055 0 026 7 10 7 00 6 90 0 280 0 276 0 272 0 004 0 006 0 053 Symbol Min Nom Max Max Nom Min Dimension in inch Dimension in mm A b c D e HD HE L Y 0 A A L1 1 2 E 0 008 0 006 0 15 0 20 7 0 020 0 35 0 65 0 10 0 05 0 002 0 004 0 006 0 15 9 10 9 00 8 90 0 358 0 354 0 350 7 10 7 00 6 90 ...

Page 941: ...NUC126 Aug 08 2018 Page 941 of 943 Rev 1 03 NUC126 SERIES TECHNICAL REFERENCE MANUAL 8 4 QFN 48L 7x7x0 8 mm ...

Page 942: ... 2 2 Updated Basic Configuration sections in Chapter 6 2017 12 15 1 02 1 Revised HIRC trim description in section 6 2 8 and 6 2 12 2 Revised Clock Output description in section 6 3 5 2018 08 08 1 03 1 Revised VDDIO description in section 1 1 and 4 1 2 2 Revised Timer PWM PWM mode description in section 2 1 3 Revised VBAT pin description in section 4 1 2 4 Added NUC126 QFN48 information in section ...

Page 943: ...es but is not limited to equipment for surgical implementation atomic energy control instruments airplane or spaceship instruments the control or operation of dynamic brake or safety systems designed for vehicular use traffic signal instruments all types of safety devices and other applications intended to support or sustain life All Insecure Usage shall be made at customer s risk and in the event...

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