93
CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U16035EJ1V0UM
Figure 5-3. Format of Processor Clock Control Register (PCC)
Address: FFFBH After reset: 04H R/W
Note 1
Symbol
7
6
5
4
3
2
1
0
PCC
MCC
FRC
CLS
CSS
0
PCC2
PCC1
PCC0
MCC
Main system clock oscillation control
Note 2
0
Oscillation possible
1
Oscillation stopped
FRC
Subsystem clock feedback resistor selection
Note 3
0
Internal feedback resistor used
1
Internal feedback resistor not used
CLS
CPU clock status
0
Main system clock
1
Subsystem clock
CSS
PCC2
PCC1
PCC0
CPU clock (f
CPU
) selection
0
0
0
0
f
X
0
0
1
f
X
/2
0
1
0
f
X
/2
2
0
1
1
f
X
/2
3
1
0
0
f
X
/2
4
1
0
0
0
f
XT
/2
0
0
1
0
1
0
0
1
1
1
0
0
Other than above
Setting prohibited
Notes 1. Bit 5 is Read Only.
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system clock
oscillation. A STOP instruction should not be used.
3. The feedback resistor is required to adjust the bias point of the oscillation waveform to close to the middle
of the power supply voltage. Setting FRC to 1 can further reduce the current consumption in the STOP
mode, but only when the subsystem clock is not used.
Cautions 1. Be sure to set bit 3 to 0.
2. When the external clock is input, MCC should not be set. This is because the X2 pin is
connected to V
DD1
via a pull-up resistor.
Remarks 1. f
X
:
Main system clock oscillation frequency
2. f
XT
: Subsystem clock oscillation frequency
