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CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U16035EJ1V0UM
5.4.3 Divider
The divider divides the main system clock oscillator output (f
X
) and generates various clocks.
5.4.4 When no subsystem clocks are used
If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect
the XT1 and XT2 pins as follows.
XT1: Connect to V
DD0
XT2: Open
In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator
when the main system clock stops. To minimize leakage current, the above internal feedback resistor can be removed
with bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2 pins as
described above.
