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CHAPTER 15 INTERRUPT FUNCTIONS
Preliminary User’s Manual U16035EJ1V0UM
15.4.5 Interrupt request hold
There are instructions where, even if an interrupt request is issued for them while another instruction is executed,
request acknowledge is held pending until the end of execution of the next instruction. These instructions (interrupt
request hold instructions) are listed below.
•
MOV PSW, #byte
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MOV A, PSW
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MOV PSW, A
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MOV1 PSW. bit, CY
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MOV1 CY, PSW. bit
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AND1 CY, PSW. bit
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OR1 CY, PSW. bit
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XOR1 CY, PSW. bit
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SET1 PSW. bit
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CLR1 PSW. bit
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RETB
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RETI
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PUSH PSW
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POP PSW
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BT PSW. bit, $addr16
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BF PSW. bit, $addr16
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BTCLR PSW. bit, $addr16
•
EI
•
DI
•
Manipulate instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, and PR1L registers
Caution
The BRK instruction is not one of the above-listed interrupt request hold instructions. However,
the software interrupt activated by executing the BRK instruction causes the IE flag to be
cleared to 0. Therefore, even if a maskable interrupt request is generated during execution of
the BRK instruction, the interrupt request is not acknowledged. However, a non-maskable
interrupt request is acknowledged.
Figure 15-15 shows the timing with which interrupt requests are held pending.
Figure 15-15. Interrupt Request Hold
Remarks 1.
Instruction N: Interrupt request hold instruction
2.
Instruction M: Instruction other than interrupt request hold instruction
3.
The
××
PR (priority level) values do not affect the operation of
××
IF (interrupt request).
Instruction N
Instruction M
Save PSW and PC, Jump
to interrupt servicing
Interrupt servicing
program
CPU processing
××
IF
