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CHAPTER 9 WATCHDOG TIMER
Preliminary User’s Manual U16035EJ1V0UM
(2) Watchdog timer mode register (WDTM)
This register sets the watchdog timer operating mode and enables/disables counting.
WDTM is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets WDTM to 00H.
Figure 9-3. Format of Watchdog Timer Mode Register (WDTM)
Address: FFF9H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
WDTM
RUN
0
0
WDTM4
WDTM3
0
0
0
RUN
Watchdog timer operation mode selection
Note 1
0
Count stop
1
Counter is cleared and counting starts
WDTM4
WDTM3
Watchdog timer operation mode selection
Note 2
0
×
Interval timer mode
Note 3
(Maskable interrupt request occurs upon generation of an overflow)
1
0
Watchdog timer mode 1
(Non-maskable interrupt request occurs upon generation of an overflow)
1
1
Watchdog timer mode 2
(Reset operation is activated upon generation of an overflow)
Notes 1.
Once set to 1, RUN cannot be cleared to 0 by software.
Thus, once counting starts, it can only be stopped by RESET input.
2.
Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software.
3.
The watchdog timer starts operations as the interval timer when 1 is set to RUN.
Caution
When 1 is set to RUN so that the watchdog timer is cleared, the actual overflow time is up to
2
8
/f
X
seconds shorter than the time set by watchdog timer clock select register (WDCS).
Remark
×
: don’t care
