188
CHAPTER 11 8-BIT A/D CONVERTER (
µ
PD780024AS SUBSERIES)
Preliminary User’s Manual U16035EJ1V0UM
(7) Interrupt request flag (ADIF0)
The interrupt request flag (ADIF0) is not cleared even if the analog input channel specification register 0 (ADS0)
is changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and conversion
end interrupt request flag for the pre-change analog input may be set just before the ADS0 rewrite. Caution is
therefore required since, at this time, when ADIF0 is read immediately just after the ADS0 rewrite, ADIF0 is set
despite the fact that the A/D conversion for the post-change analog input has not ended.
When the A/D conversion is restarted after it is stopped, clear ADIF0 before restart.
Figure 11-17. A/D Conversion End Interrupt Request Generation Timing
ADM0 rewrite
(start of ANIn conversion)
A/D conversion
ADCR0
INTAD0
ANIn
ANIn
ANIm
ANIm
ANIn
ANIn
ANIm
ANIm
ADS0 rewrite
(start of ANIm conversion)
ADIF is set but ANIm conversion
has not ended.
Remarks 1.
n = 0, 1, ......, 3
2.
m = 0, 1, ......, 3
(8) Conversion results just after A/D conversion start
The first A/D conversion value just after A/D conversion operations start may not fall within the rating. Polling
A/D conversion end interrupt request (INTAD0) and take measures such as removing the first conversion results.
(9) A/D conversion result register 0 (ADCR0) read operation
When writing is performed to the A/D converter mode register 0 (ADM0) and analog input channel specification
register 0 (ADS0), the contents of ADCR0 may become undefined. Read the conversion result following
conversion completion before writing to ADM0, ADS0. Using a timing other than the above may cause an incorrect
conversion result to be read.
